KR20150069356A - Driving circuit and method for driving the same - Google Patents

Abstract

The present invention relates to a driving circuit for a display device, and a driving method thereof wherein the number of signal transmission lines between a timing controller and a power control integrated circuit can be reduced. The present invention comprises: a timing controller for generating an on-clock pulse and an off-clock pulse both having different output timings and for outputting thereof in a time period displayed on a frame; and a gate control signal generating unit for generating a gate clock pulse which is shifting to an active voltage according to the on-clock pulse and which is shifting to a non-active voltage according to the off-clock pulse.

Description

TECHNICAL FIELD [0001] The present invention relates to a driving circuit for a display device,

The present invention relates to a driving circuit for a display device, and more particularly to a driving circuit for a display device and a driving method thereof for reducing the number of signal transmission lines between a timing controller and a power supply control integrated circuit.

The gate driver receives gate drive signals from the timing controller through a power control integrated circuit.

The conventional power supply control integrated circuit functions to simply level-convert the gate driving signals outputted in timing from the timing controller and provide them to the gate driver. As a result, the timing controller must directly generate all the gate driving signals and supply them to the power supply control integrated circuit. Therefore, a large number of signal transmission lines must be installed between the timing controller and the power supply control integrated circuit. For example, to supply four modulated clock pulses for modulating the 8-phase gate clock pulse, the first AC voltage, the second AC voltage, and the 8-phase gate clock pulse to the power supply control integrated circuit, A total of 15 transmission lines are required between the control integrated circuits.

Therefore, in the conventional structure, when the space of the printed circuit board is narrow, it is difficult to pattern the signal transmission lines. Also, as the number of signal transmission lines increases, the interval between the signal transmission lines becomes narrower.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems as described above and it is an object of the present invention to provide a display device drive circuit and a driving method thereof capable of supplying all the signals required for the operation of the gate driver to the power source control integrated circuit by using only four signal transmission lines The purpose is to provide.

According to an aspect of the present invention, there is provided a driving circuit for a display device, comprising: a timing controller for generating on-clock pulses and off-clock pulses having different output timings and outputting them during a display period of a frame; And a gate control signal generator for generating a gate clock pulse that transitions to an active voltage in response to the on-clock pulse and transitions to an inactive voltage in accordance with the off-clock pulse.

The timing controller further outputs an AC control pulse after the last impulse of the impulses included in the off-clock pulse is generated; The gate control signal generator further performs an operation of inverting the level of the first and second AC voltages according to the AC control pulse from the timing controller so that the first AC voltage and the second AC voltage have opposite voltages .

And the AC control pulse is outputted during the blank period of the frame.

Wherein the gate control signal generator inverts a level of the second AC control voltage from a high logic level to a low logic level in accordance with a polling edge point of the AC control pulse; And inverting from a low logic level to a high logic level of the first AC control voltage in accordance with a rising edge of the AC control pulse.

The timing controller generates a first control pulse for controlling an active time point of gate dummy pulses, an active time point of a first impulse among the impulses included in the on-clock pulse, and an inactive time point of a gate start pulse, Outputting it during a blank period and a display period of the frame; A second control pulse for controlling an active time of the gate dummy pulses and an inactive time point of a gate dummy pulse having the longest pulse width among the gate dummy pulses and outputting the second control pulse during a blank period of the frame ; Generating an active time point of the gate dummy pulses and a third control pulse for controlling an inactive time point of a gate dummy pulse having a shortest pulse width among the gate dummy pulses and outputting the third control pulse during a blank period of the frame; Generating a fourth control pulse for controlling the inactive timing of the remaining gate dummy pulses except for the gate dummy pulse having the widest width and the gate dummy pulse having the shortest width, and outputting the fourth control pulse during the blank period of the frame ; A fifth control pulse for controlling the active time point and the inactive time point of the gate start pulse is generated, and during the display period of the frame preceding the active point of the first impulse of the on- And outputting the output signal.

Wherein the gate control signal generator further receives the second to fifth control pulses output from the timing controller; The second control pulse and the on-clock pulse are supplied from the timing controller to the gate control signal generator through the same signal transmission line; The third to fifth control pulses and the off-clock pulses are supplied from the timing controller to the gate control signal generator through the same signal transmission line.

And the active timings of the first to third control pulses are the same.

A level shifter for receiving a gate clock pulse from the gate control signal generator and shifting the gate clock pulse and outputting the shifted level; And a gate driver for generating a gate signal by using a gate clock pulse from the level shifter.

The level shifter further receives an on-clock pulse and an off-clock pulse from the timing controller; The step of increasing the amplitude of the gate clock pulse located in the active section of the on-clock pulse stepwise decreases the amplitude of the gate clock pulse corresponding to the active section of the off-clock pulse step by step .

According to another aspect of the present invention, there is provided a method of driving a driving circuit for a display device, the method including generating on-clock pulses and off-clock pulses having different output timings, and outputting the on- step; And generating a gate clock pulse that transitions to an active voltage in response to the on-clock pulse and transitions to an inactive voltage in accordance with the off-clock pulse.

Further comprising: outputting an AC control pulse after a last impulse of the impulses included in the off-clock pulse is generated; And the AC control pulse is a signal for instructing to invert the level of the first and second AC control voltages so that the first AC voltage and the second AC voltage have opposite voltages.

And the AC control pulse is outputted during the blank period of the frame.

Inverting a level of the second AC voltage from a high logic level to a low logic level in accordance with an active time of the AC control pulse; And inverting the level of the first AC voltage from the low logic level to the high logic level in accordance with the inactive timing of the AC control pulse.

A first control pulse for controlling the active time of the gate dummy pulses, the active time of the first impulse among the impulses contained in the on-clock pulse, and the inactive time of the gate start pulse, Outputting during a period and a display period; Generating a second control pulse for controlling an active point of the gate dummy pulses and an inactive point of a gate dummy pulse having the longest pulse width among the gate dummy pulses and outputting the second control pulse during a blank period of the frame ; Generating an active time point of the gate dummy pulses and a third control pulse for controlling an inactive time point of a gate dummy pulse having a shortest pulse width among the gate dummy pulses and outputting the third control pulse during a blank period of the frame; Generating a fourth control pulse for controlling the inactive timing of the remaining gate dummy pulses except for the gate dummy pulse having the widest width and the gate dummy pulse having the shortest width and outputting the fourth control pulse during the blank period of the frame ; And a fifth control pulse for controlling an active time point and an inactive time point of the gate start pulse, and for generating a fifth control pulse during the display period of the frame preceding the active point of the first impulse of the on- And outputting the output signal.

The second control pulse and the on-clock pulse are transmitted through the same signal transmission line; The third to fifth control pulses and the off-clock pulses are transmitted through the same signal transmission line.

And the active timings of the first to third control pulses are the same.

Shifting and outputting the level of the gate clock pulse; And generating a gate signal using the level shifted gate clock pulse.

Incrementing the amplitude of the gate clock pulse located in an active period of the on-clock pulse step by step; And decreasing the amplitude of the gate clock pulse corresponding to the active period of the off-clock pulse step by step.

The driving circuit for a display device and the driving method thereof according to the present invention have the following effects.

First, all signals necessary for the operation of the gate driver can be supplied to the power supply control integrated circuit by only four signal transmission lines, thereby reducing the width of the total signal transmission lines used.

Second, the number of pins of the timing controller and the power control integrated circuit can be reduced, and the manufacturing cost of the timing controller and the power control integrated circuit can be reduced.

Third, since the intervals between the signal transmission lines can be widened, it is possible to minimize the human signal interference.

1 is a block diagram of a display device having a driving circuit according to an embodiment of the present invention.
2 is a diagram showing a connection relationship between the timing controller and the gate control unit in Fig. 1
3 is a block diagram showing a specific configuration of the gate control unit
4 is a diagram for explaining a method of generating gate clock pulses using on-clock pulses, off-clock pulses, and ac control pulses;
5 is a diagram for explaining a method of generating the first gate clock pulse in FIG. 4;
FIG. 6 is a view for explaining a method of generating the first AC voltage and the second AC voltage in FIG. 4; FIG.
FIG. 7 is a view for explaining a method of generating gate start pulses and gate dummy pulses indicated by dotted lines in FIG. 4;
8 is a diagram for explaining the configuration of the level shifter

1 is a block diagram of a display device having a driving circuit according to an embodiment of the present invention.

A display device according to an embodiment of the present invention includes a display unit (DSP), a data driver (DD), a gate driver (GD), a timing controller (TC), and a power source control integrated circuit (PMIC) The data driver DD, the gate driver GD, the timing controller TC and the power source control integrated circuit PMIC are connected to a display unit DSP for driving a display unit DSP so that an image is displayed on the display unit DSP. Respectively. The following is a detailed description of the listed components.

The display unit DSP includes a plurality of pixels PXL and i data lines DL1 to DLi and j gate lines GL1 to GLn for transmitting the various signals required for these pixels PXL to display an image, GLj. Here, i and j are natural numbers.

The pixels PXL are arranged in a matrix on the display unit DSP. I pixels PXL are arranged in each horizontal line of the display section. The pixels PXL are divided into a red pixel R for displaying a red image, a green pixel G for displaying a green image, and a blue pixel B for displaying a blue image. At this time, three red pixels R, green pixels G and blue pixels B connected to the same gate line and located adjacent to each other constitute one unit pixel. This unit pixel displays a unit image by mixing a red image, a green image, and a blue image.

The timing controller TC receives a horizontal synchronizing signal Hsync, a vertical synchronizing signal Vsync, a dot-clock signal d-clk and image data img_data from the system. The data control signal dcs and the gate control signal gcs are generated by using the inputted horizontal synchronizing signal Hsync, vertical synchronizing signal Vsync and dot-clock signal d-clk.

The data control signal dcs includes a source clock pulse signal, a source start pulse signal, a source output enable signal, and a polarity inversion control signal. The data control signal dcs is supplied to the data driver DD.

The gate control signal gcs includes first to fifth control pulses, on-clock pulses, off-clock pulses, and ac control pulses. The gate control signal gcs is input to the power source control integrated circuit PMIC and instructs the power source control integrated circuit PMIC to generate gate driving signals necessary for driving the gate driver GD.

The gate driver GD generates gate signals using the gate driving signals generated by the gate control signal gcs and sequentially supplies the gate signals to the plurality of gate lines GL1 to GLj, To GLj. Here, the gate driver GD may be a driver embedded in a display panel, that is, a gate-in-panel driver. In this case, the gate driver GD is formed in the non-display portion of the display panel.

The data driver DD samples the video data (video data from the timing controller) in accordance with the data control signal dcs from the timing controller TC and then outputs the video data to each horizontal period (1H, 2H,. ..), and supplies the latched image data of one horizontal line to the data lines DL1 to DLj. At this time, the data driver DD converts the video data from the timing controller TC into analog data signals using the gamma reference voltages supplied from the power source control integrated circuit (PMIC), and supplies the analog data signals to the data lines DL1 to DLj. .

The power supply control integrated circuit (PMIC) generates various driving signals required for the display unit (DSP), the gate driver (GD), and the data driver (DD). For example, the power supply control integrated circuit (PMIC) boosts or downstages an input voltage (Vin) provided from a power supply of a system (not shown) to generate a digital logic voltage, a reference voltage, a common voltage, Voltage, gate-low voltage, and the like. Here, the reference voltage may be used as a voltage corresponding to the highest gradation or the lowest gradation of the data, and the gamma reference voltage may be used as a voltage corresponding to the intermediate gradations of the data. The gate high voltage may be a high logic Voltage, and the gate-low voltage can be used as the low logic voltage of the gate signal. The power supply control integrated circuit PMIC includes a gate control unit GC. The gate control unit GC controls the gate driver GD using the gate control signal gcs provided from the timing controller TC. Lt; / RTI >

Here, the connection relationship between the timing controller and the gate control unit (GC) will be described with reference to FIG.

2 is a diagram showing the connection relationship between the timing controller TC and the gate control unit GC of FIG.

As shown in FIG. 2, the gate control signal gcs includes a first to a fifth control pulses CP1 to CP5, an on-clock pulse on-CLK, an off-clock pulse off- Pulse (ACCP). The timing controller TC and the gate control unit GC are connected to each other through the first to fourth signal transmission lines SL1 to SL4. The timing controller TC and the gate control unit GC are connected to each other through the signal transmission lines SL1 to SL4. The gate control signal gcs from the gate terminal TC is supplied to the gate control unit GC. Specifically, the first control pulse CP1 is transmitted through the first signal transmission line SL1, and the second control pulse CP2 and the on-clock pulse on-CLK are transmitted through the second signal transmission line SL2 And the third to fifth control pulses CP3 to CP5 and the off-clock pulses off-CLK are transmitted through the third signal transmission line SL3 and the AC control pulse ACCP is transmitted through the fourth signal transmission line SL3, And from the timing controller TC to the gate control unit GC via the clock signal line SL4.

The gate control unit GC uses the first to fifth control pulses CP1 to CP5, the on-clock pulses on-CLK, the off-clock pulses off-CLK and the ac control pulses ACCP , And gate drive signals necessary for the operation of the gate driver GD. For example, the gate control unit GC may control the gate start pulse Vst and the plurality of gate clock pulses Vc and Vc using the above-mentioned signals CP1 to CP5, on-CLK, off-CLK, (G-CLK1 to G-CLK8). On the other hand, according to the configuration of the gate driver GD, the gate control part GC includes, for example, a plurality of gate dummy pulses DM1 to DM8, a first AC voltage PVDD_O and a second AC voltage PVDD_E ) Can be further generated.

As described above, according to the present invention, all the signals necessary for the operation of the gate driver GD can be transmitted to the gate control unit GC with only four signal transmission lines SL1 to SL4.

On the other hand, the first to fifth control pulses CP1 to CP5, the on-clock pulses (on-CLK), the off-clock pulses (off-CLK) A Schmitt trigger circuit may be further provided between the timing controller TC and the gate control part GC so that the control pulse ACCP has a shape closer to a square wave.

Here, the gate control unit GC will be described in more detail with reference to FIG.

3 is a block diagram showing a specific configuration of the gate control unit GC.

The gate control section GC includes a gate control signal generation section (GCSG) and a level shifter (LS) as shown in Fig.

The gate control signal generator GCSG generates the gate control signal GCSG based on the first to fifth control pulses CP1 to CP5, the on-clock pulse on-CLK, the off-clock pulse off- ), A plurality of gate clock pulses G-CLK1 to G-CLK8, a plurality of gate dummy pulses DM1 to DM8, a first AC voltage PVDD_O, and a second Thereby generating an AC voltage (PVDD_E).

The level shifter LS includes a gate start pulse Vst from the gate control signal generator GCSG, a plurality of gate clock pulses G-CLK1 to G-CLK8, a plurality of gate dummy pulses DM1 to DM8 ), The first AC voltage PVDD_O and the second AC voltage PVDD_E to a level suitable for driving the gate driver GD. For example, a gate clock pulse having a low logic voltage of the ground level and a high logic voltage of 1.8 [V] is applied to the gate low voltage of -4 [V] as the low logic voltage through the level shifter LS above, And its level is shifted to have a gate high voltage of 20 [V] as its high logic voltage.

On-clock pulses (on-CLK) and off-clock pulses (off-CLK) of the signals included in the gate control signal gcs described above are supplied not only to the gate control signal generator GCSG but also to the level shifter LS. The level shifter LS modulates the amplitude level of the front end section of each of the gate clock pulses G-CLK1 to G-CLK8 using the on-clock pulse on-CLK, off-CLK) to modulate the amplitude level of the rear end section of each of the gate clock pulses G-CLK1 to G-CLK8. This will be described in more detail later.

A gate start pulse Vst, a plurality of gate clock pulses G-CLK1 to G-CLK8, and a plurality of gate dummy pulses DM1 to DM8, which are level shifted from the level shifter LS described above, The first AC voltage PVDD_O and the second AC voltage PVDD_E are input to the gate driver GD which generates the gate signals using the gate driving signals listed above .

Hereinafter, a method of generating gate driving signals from the gate control signal generator (GCSG) will be described with reference to FIGS. 4 to 7. FIG.

4 shows a method of generating gate clock pulses G-CLK1 to G-CLK8 using an on-clock pulse (on-CLK), an off-clock pulse (off-CLK) and an ac control pulse ACCP Fig.

In FIG. 4, the number shown next to each signal indicates the name of the remaining signal except the signals indicated by dotted lines.

The on-clock pulses (on-CLK) and off-clock pulses (off-CLK) provided from the timing controller TC are clock pulses consisting of a plurality of impulses periodically output, (off-CLK) is output later than the on-clock pulse (on-CLK). For example, Figure 4, on as shown in-clock pulses (on-CLK) fourth impulse (④) immediately followed off after the occurrence of - the first impulse of the clock pulse (off-CLK) (ⓐ) . In other words, the off-the first output point (ⓐ) of the second impulse of the clock pulse (off-CLK), the on-position between the clock fourth impulse of a pulse (on-CLK) (④) and a fifth impulse (⑤) do.

The gate clock pulses G-CLK1 to G-CLK8 are generated by the on-clock pulse on-CLK and the off-clock pulse off-CLK. That is, each of the gate clock pulses G-CLK1 to G-CLK8 has a pair of on-clock pulses (on-CLK) and off-clock pulses (off-CLK) . Here, the active time of the signal means a time point at which the signal transits from the inactive voltage to the active voltage, and the inactive time point of the signal means a time point at which the signal transits from the active voltage to the inactive voltage. At this time, when the active voltage is a high logic voltage and the inactive voltage corresponds to a low logic voltage, the active time becomes the rising edge of the signal and the inactive time becomes the falling edge of the signal ). On the other hand, when the active voltage is a low logic voltage and the inactive voltage corresponds to a high logic voltage, the active point is the polling edge point of the signal and the inactive point is the rising edge point of the signal. The active period of the signal means a period in which the signal is maintained in the state of the active voltage.

Thus, the active and inactive timings of the respective gate clock pulses G-CLK1 to G-CLK8 correspond to the corresponding impulses of the on-clock pulses on-CLK and the corresponding off-clock pulses off-CLK The determination is made by the impulse, and a specific example will be described with reference to FIG. 5 as follows.

FIG. 5 is a diagram for explaining a method of generating the first gate clock pulse (G-CLK1) in FIG.

As shown in FIG. 5, the first gate clock pulse G-CLK1 (the first-most impulse output) is generated by applying the first impulse ( 1 ) of the on-clock pulse on- that the active time and the inactive time by the first impulse (ⓐ) of clock pulses (CLK-off) is determined. Specifically, the first gate clock pulse G-CLK1 starts to transition to the high logic voltage (active voltage) in accordance with the rising edge time of the first impulse ( 1 ) of the on-clock pulse (on-CLK) and that the impulse (①) off corresponding to - begins to switch to the first clock pulse a low logic voltage (non-active voltage) according to the falling edge point of the second impulse (ⓐ) of (off-CLK).

In other words, the gate control signal generator GCSG rises to the high logic voltage in accordance with the rising edge time of the first impulse ( 1 ) of the above-mentioned on-clock pulse (on-CLK) generates a first gate clock pulse (G-CLK1) to transition to a low voltage set by the first falling edge point of the second impulse (ⓐ) in the (off-CLK).

In this manner, the second gate clock pulse (G-CLK2; the first-most impulse output) is applied to the second impulse ( 2 ) of the on-clock pulse on-CLK and the corresponding off- CLK), and the third gate clock pulse (first impulse output) is determined by the second impulse ( b ) of the on-clock pulse (on-CLK) a third impulse (③) and its corresponding off-clock pulses (off-CLK) by the three first impulse (ⓒ) is determined that the active time and the inactive time of, ..., and an eighth gate clock pulse (The first impulse output first) is generated by the eighth impulse of the on-clock pulse (on-CLK) and the eighth impulse of the corresponding off-clock pulse (off-CLK) Is determined.

Each of the first to eighth gate clock pulses G-CLK1 to G-CLK8 has a pulse width interval corresponding to four horizontal periods, and pulse width intervals of two adjacent gate clock pulses are 3 / 4 horizontal periods. Meanwhile, the pulse width section of the gate start pulse Vst corresponds to two horizontal periods, and the pulse width section of the first control pulse CP1 corresponds to four horizontal periods.

The gate clock pulses G-CLK1 to G-CLK8 thus generated actually rise to the active voltage at the rising edge of the on-clock pulse on-CLK, and has a square wave falling directly to the inactive voltage at the falling edge of the off-CLK. However, when these gate clock pulses pass through the level shifter LS, their leading and trailing edges are stepped up and down by modulation. For example, as illustrated in Figure 5, the level shifter (LS), the on-clock pulses (on-CLK) (i.e., ①) in the active region (A1) a first gate clock pulse (G-CLK1 of ) progressively increased over the amplitude in the second step and, the off-the amplitude of the first gate clock pulse (G-CLK1) corresponding to the active region (A2) of the clock pulse (off-CLK) (i.e., ⓐ) Decrease gradually in two steps. If the above-described modulation is performed in the level shifting of the gate clock pulses as described above, the magnitude of the amplitude at which the signal is transited can be reduced, which is effective in reducing the power consumption.

On the other hand, the AC control pulse ACCP provided from the timing controller TC is a signal generated after the last impulse ( ⓩ ) among the impulses included in the off-clock pulse (off-CLK) is generated. This AC control pulse ACCP can be output during the blank period BLK of the frame FR, for example.

The AC control pulse ACCP is controlled so that the levels of the first and second AC control voltages PVDD_O and PVDD_E are inverted so that the first AC voltage PVDD_O and the second AC voltage PVDD_E have voltages opposite to each other . The level reversal of the first AC voltage PVDD_O and the second AC voltage PVDD_E by the AC control pulse ACCP will be described with reference to FIG.

FIG. 6 is a diagram for explaining a method of generating the first AC voltage PVDD_O and the second AC voltage PVDD_E in FIG.

As shown in Fig. 6, the level of the second AC voltage PVDD_E is inverted from the high logic level to the low logic level in accordance with the polling edge point of the AC control pulse ACCP. On the other hand, the level of the first AC voltage PVDD_O is inverted from the low logic level to the high logic level in accordance with the inactive timing of the AC control pulse ACCP.

Hereinafter, a method of generating gate dummy pulses and gate start pulses will be described with reference to FIG.

FIG. 7 is a diagram for explaining a method of generating gate start pulses and gate dummy pulses indicated by dotted lines in FIG.

7 shows the names of the remaining signals excluding the signals indicated by the dotted lines.

The first control pulse CP1 is applied to the active time T8 of the first impulse 1 of the impulses included in the active time T1 of the first to eighth gate dummy pulses and the on- ) And an inactive time point T7 of the gate start pulse, which is output during the blank period BLK of the frame FR and the display period DP.

The second control pulse CP2 is applied to an active time point T1 of the first to eighth gate dummy pulses DM1 to DM8 and a second control pulse CP2 having the longest pulse width among the gate dummy pulses DM1 to DM8 4 and the inactive timing T5 of the eighth gate dummy pulses DM4 and DM8, which are output during the blank period BLK of the frame FR.

The third control pulse CP3 is applied to the active time point T1 of the first to eighth gate dummy pulses DM1 to DM8 and the first control pulse CP2 having the shortest pulse width among the gate dummy pulses DM1 to DM8 And the inactive timing T2 of the fifth gate dummy pulses DM1 and DM5, which are output during the blank period BLK of the frame FR.

The fourth control pulse CP4 is generated by applying the fourth and eighth gate dummy pulses DM4 and DM8 having the widest width and the remaining gates except for the first and fifth gate dummy pulses DM1 and DM5 having the shortest width. (T3, T4) of the dummy pulses, that is, the second, third, sixth and seventh gate dummy pulses DM2, DM3, DM6 and DM7, And is output during the blank period BLK. That is, the second and sixth gate dummy pulses DM2 and DM6 are transitioned to the inactive voltage at the rising edge of the fourth control pulse CP4, and the third and eighth gate dummy pulses CP3 and CP8 And transits to the inactive voltage at the polling edge of the fourth control pulse CP4.

The fifth control pulse CP5 is a signal for controlling the active time point T6 and the inactive time point T7 of the gate start pulse Vst which is the first impulse of the on-clock pulse on-CLK Is output during the display period DP of the frame FR preceding the active time of the frame FR. The first impulse ( 1 ) of the on-clock pulse (on-CLK) is generated after the inactive point of time T7 of the fifth control pulse CP5.

The respective active timings T1 of the first to third control pulses CP1 to CP3 described above are all the same.

8 is a diagram for explaining the configuration of the level shifter LS.

The level shifter LS according to the present invention may include a gate control signal generator (GCSG) therein. That is, the gate control signal generator GCSG in FIG. 3 may be embedded in the level shifter LS. In this case, the level shifter LS further performs the function of the gate control signal generator GCSG.

As described above, the first to fifth control pulses CP1 to CP5, the on-clock pulses on-CLK, the off-clock pulses off-CLK, and the AC control pulses ACCP, The number of signal transmission lines between the timing controller TC and the power supply control integrated circuit (PMIC) can be greatly reduced compared to the related art. As a result, the total width of the entire signal transmission lines is also reduced, which enables pattern optimization of signal transmission lines on the printed circuit board.

In addition, the number of pins of the timing controller (TC) and the power source control integrated circuit (PMIC) can be reduced, and the manufacturing cost of the timing controller (TC) and the power source control integrated circuit (PMIC) can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

TC: timing controller GC: gate control section
GD: Gate driver SL #: 1st signal transmission line
CP #: No. Control pulse on-CLK: On-clock pulse
off-CLK: off-clock pulse ACCP: AC control pulse
DM #: 1st gate dummy pulse Vst: Gate start pulse
G-CLK #: 1st gate clock pulse PVDD_O: first AC voltage
PVDD_E: Second AC voltage

Claims (18)

A timing controller for generating on-clock pulses and off-clock pulses having different output timings and outputting them during a display period of a frame; And
And a gate control signal generator for generating a gate clock pulse that transitions to an active voltage in response to the on-clock pulse and transitions to an inactive voltage in accordance with the off-clock pulse. The method according to claim 1,
The timing controller further outputs an AC control pulse after the last impulse of the impulses included in the off-clock pulse is generated;
The gate control signal generator further performs an operation of inverting the level of the first and second AC voltages according to the AC control pulse from the timing controller so that the first AC voltage and the second AC voltage have opposite voltages And a driving circuit for driving the display device. 3. The method of claim 2,
And the AC control pulse is outputted during the blank period of the frame. 3. The method of claim 2,
Wherein the gate control signal generator comprises:
Inverting a level of the second AC control voltage from a high logic level to a low logic level in accordance with a polling edge point of the AC control pulse; And,
And reverses from a low logic level to a high logic level of the first AC control voltage in accordance with a rising edge of the AC control pulse. The method according to claim 1,
The timing controller includes:
A first control pulse for controlling the active time of the gate dummy pulses, the active time of the first impulse among the impulses contained in the on-clock pulse, and the inactive time of the gate start pulse, An operation for outputting during a period and a display period;
A second control pulse for controlling an active time of the gate dummy pulses and an inactive time point of a gate dummy pulse having the longest pulse width among the gate dummy pulses and outputting the second control pulse during a blank period of the frame ;
Generating an active time point of the gate dummy pulses and a third control pulse for controlling an inactive time point of a gate dummy pulse having a shortest pulse width among the gate dummy pulses and outputting the third control pulse during a blank period of the frame;
Generating a fourth control pulse for controlling the inactive timing of the remaining gate dummy pulses except for the gate dummy pulse having the widest width and the gate dummy pulse having the shortest width, and outputting the fourth control pulse during the blank period of the frame ; And,
A fifth control pulse for controlling an active time point and an inactive point of time of the gate start pulse and outputting the fifth control pulse during the display period of the frame preceding the active point of the first impulse of the on- Wherein the driving circuit further performs the operation of driving the display device. 6. The method of claim 5,
Wherein the gate control signal generator further receives the second to fifth control pulses output from the timing controller;
The second control pulse and the on-clock pulse are supplied from the timing controller to the gate control signal generator through the same signal transmission line; And,
Wherein the third to fifth control pulses and the off-clock pulses are supplied from the timing controller to the gate control signal generator through the same signal transmission line. 6. The method of claim 5,
And the active timings of the first to third control pulses are the same. The method according to claim 1,
A level shifter for receiving a gate clock pulse from the gate control signal generator and shifting the gate clock pulse and outputting the shifted level; And
And a gate driver for generating a gate signal by using a gate clock pulse from the level shifter. 9. The method of claim 8,
The level shifter further receives an on-clock pulse and an off-clock pulse from the timing controller; And,
The method further comprises the step of increasing the amplitude of the gate clock pulse located in the active section of the on-clock pulse step by step and decreasing the amplitude of the gate clock pulse corresponding to the active section of the off- And a driving circuit for driving the display device. Generating on-clock pulses and off-clock pulses having different output timings and outputting them during a display period of a frame;
And generating a gate clock pulse that transitions to an active voltage in response to the on-clock pulse and transitions to an inactive voltage in accordance with the off-clock pulse. 11. The method of claim 10,
Further comprising: outputting an AC control pulse after a last impulse of the impulses included in the off-clock pulse is generated;
Wherein the AC control pulse is a signal for instructing to invert the levels of the first and second AC control voltages so that the first AC voltage and the second AC voltage have opposite voltages to each other Way. 12. The method of claim 11,
And the AC control pulse is outputted during a blank period of the frame. 12. The method of claim 11,
Inverting a level of the second AC voltage from a high logic level to a low logic level in accordance with an active time of the AC control pulse; And
And reversing the level of the first AC voltage from a low logic level to a high logic level in accordance with an inactive timing of the AC control pulse. 11. The method of claim 10,
A first control pulse for controlling the active time of the gate dummy pulses, the active time of the first impulse among the impulses contained in the on-clock pulse, and the inactive time of the gate start pulse, Outputting during a period and a display period;
Generating a second control pulse for controlling an active point of the gate dummy pulses and an inactive point of a gate dummy pulse having the longest pulse width among the gate dummy pulses and outputting the second control pulse during a blank period of the frame ;
Generating an active time point of the gate dummy pulses and a third control pulse for controlling an inactive time point of a gate dummy pulse having a shortest pulse width among the gate dummy pulses and outputting the third control pulse during a blank period of the frame;
Generating a fourth control pulse for controlling the inactive timing of the remaining gate dummy pulses except for the gate dummy pulse having the widest width and the gate dummy pulse having the shortest width and outputting the fourth control pulse during the blank period of the frame ; And
A fifth control pulse for controlling an active time point and an inactive point of time of the gate start pulse and outputting the fifth control pulse during the display period of the frame preceding the active point of the first impulse of the on- The method further comprising the step of: 15. The method of claim 14,
The second control pulse and the on-clock pulse are transmitted through the same signal transmission line; And,
Wherein the third to fifth control pulses and the off-clock pulses are transmitted through the same signal transmission line. 15. The method of claim 14,
And the active timings of the first to third control pulses are the same. 11. The method of claim 10,
Shifting and outputting the level of the gate clock pulse; And
Further comprising the step of generating a gate signal using a level shifted gate clock pulse. 18. The method of claim 17,
Incrementing the amplitude of the gate clock pulse located in an active period of the on-clock pulse step by step; And
Further comprising the step of decreasing the amplitude of the gate clock pulse corresponding to the active period of the off-clock pulse step by step.

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