KR20150040998A - 두 개 이상의 다이에 대한 다중 다이 페이스-다운 적층 - Google Patents

두 개 이상의 다이에 대한 다중 다이 페이스-다운 적층 Download PDF

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Publication number
KR20150040998A
KR20150040998A KR1020157005424A KR20157005424A KR20150040998A KR 20150040998 A KR20150040998 A KR 20150040998A KR 1020157005424 A KR1020157005424 A KR 1020157005424A KR 20157005424 A KR20157005424 A KR 20157005424A KR 20150040998 A KR20150040998 A KR 20150040998A
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South Korea
Prior art keywords
microelectronic
extending
opening
substrate
dimension
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Ceased
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KR1020157005424A
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English (en)
Korean (ko)
Inventor
벨가셈 하바
와엘 조니
리차드 드윗 크리스프
일야스 모하메드
프랭크 람브레히트
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테세라, 인코포레이티드
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Priority claimed from US13/741,890 external-priority patent/US9013033B2/en
Application filed by 테세라, 인코포레이티드 filed Critical 테세라, 인코포레이티드
Publication of KR20150040998A publication Critical patent/KR20150040998A/ko
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0657—Stacked arrangements of devices
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    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/4805—Shape
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/732—Location after the connecting process
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)
KR1020157005424A 2012-08-02 2013-08-01 두 개 이상의 다이에 대한 다중 다이 페이스-다운 적층 Ceased KR20150040998A (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201213565613A 2012-08-02 2012-08-02
US13/565,613 2012-08-02
US13/741,890 2013-01-15
US13/741,890 US9013033B2 (en) 2011-04-21 2013-01-15 Multiple die face-down stacking for two or more die
PCT/US2013/053240 WO2014022675A1 (en) 2012-08-02 2013-08-01 Multiple die face-down stacking for two or more die

Publications (1)

Publication Number Publication Date
KR20150040998A true KR20150040998A (ko) 2015-04-15

Family

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KR1020157005424A Ceased KR20150040998A (ko) 2012-08-02 2013-08-01 두 개 이상의 다이에 대한 다중 다이 페이스-다운 적층

Country Status (5)

Country Link
EP (1) EP2880685A1 (enExample)
JP (1) JP2015523742A (enExample)
KR (1) KR20150040998A (enExample)
CN (1) CN104718619A (enExample)
WO (1) WO2014022675A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114040579B (zh) * 2021-11-08 2023-12-22 艾科微电子(深圳)有限公司 电子器件及其制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02174255A (ja) 1988-12-27 1990-07-05 Mitsubishi Electric Corp 半導体集積回路装置
US5679977A (en) 1990-09-24 1997-10-21 Tessera, Inc. Semiconductor chip assemblies, methods of making same and components for same
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5861666A (en) 1995-08-30 1999-01-19 Tessera, Inc. Stacked chip assembly
JP2004063767A (ja) * 2002-07-29 2004-02-26 Renesas Technology Corp 半導体装置
US7462936B2 (en) 2003-10-06 2008-12-09 Tessera, Inc. Formation of circuitry with modification of feature height
US7061121B2 (en) * 2003-11-12 2006-06-13 Tessera, Inc. Stacked microelectronic assemblies with central contacts
JP4579258B2 (ja) * 2007-01-18 2010-11-10 力成科技股▲分▼有限公司 Ｂｇａ型パッケージ
JP2008277660A (ja) * 2007-05-02 2008-11-13 Powertech Technology Inc Ｌｇａ半導体実装構造
KR101479461B1 (ko) * 2008-10-14 2015-01-06 삼성전자주식회사 적층 패키지 및 이의 제조 방법
US8553420B2 (en) * 2010-10-19 2013-10-08 Tessera, Inc. Enhanced stacked microelectronic assemblies with central contacts and improved thermal characteristics
KR101061531B1 (ko) * 2010-12-17 2011-09-01 테세라 리써치 엘엘씨 중앙 콘택을 구비하며 접지 또는 배전을 개선한 적층형 마이크로전자 조립체

Also Published As

Publication number Publication date
JP2015523742A (ja) 2015-08-13
WO2014022675A1 (en) 2014-02-06
CN104718619A (zh) 2015-06-17
EP2880685A1 (en) 2015-06-10

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