KR20150015601A - Memory device - Google Patents

Abstract

The present invention relates to a memory device. The memory device includes a lower electrode, a magnetic tunnel junction, a capping layer, a composite exchange diamagnetic layer, and an upper electrode laminated onto each other on a substrate. The lower electrode is formed by laminating a first lower electrode having a polycrystalline structure and a second lower electrode having an amorphous structure. The magnetic resistance change ratio of the capping layer according to the thickness change is within 35%.

Description

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, and more particularly, to a magnetic memory device using a magnetic tunnel junction (MTJ).

Next-generation nonvolatile memory devices that have lower power consumption and higher integration than flash memory devices are being studied. These next generation non-volatile memory devices include a phase change memory (PRAM) that utilizes a state change of a phase change material such as a chalcogenide alloy, a magnetic tunnel junction (PMR) according to a magnetization state of a ferromagnetic material, (MRAM) using resistance change of MTJ, ferroelectric RAM using polarization of ferroelectric material, resistance change RAM (ReRAM) using resistance change of variable resistance material, etc. .

An STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) device for inverting magnetization by using a spin transfer torque (STT) phenomenon by electron injection as a magnetic memory and discriminating the difference in resistance before and after magnetization inversion . The STT-MRAM devices each include a pinned layer and a free layer formed of a ferromagnetic material, and a magnetic tunnel junction formed with a tunnel barrier therebetween. If the magnetization directions of the free layer and the pinned layer are the same (i.e., parallel), the magnetic tunnel junction has a low resistance state due to easy current flow, and if the magnetization directions are different (i.e., anti parallel) Resistance state. These STT-MRAM devices can theoretically be cycled at 10 ¹⁵ or more, and can be switched at a speed as high as nanoseconds (ns). In particular, the vertical magnetization type STT-MRAM device has no scaling limit in theory, and the current density of the driving current can be lowered as the scaling progresses. Therefore, the research is being conducted as a next generation memory device that can replace the DRAM device . On the other hand, an example of an STT-MRAM device is disclosed in Korean Patent No. 10-1040163.

In the STT-MRAM device, a seed layer is formed under the free layer, a capping layer is formed on the fixed layer, and a synthetic exchangeable semi-magnetic layer and an upper electrode are formed on the capping layer. In this STT-MRAM device, a silicon oxide film is formed on a silicon substrate, and then a seed layer and a magnetic tunnel junction are formed thereon. Therefore, the STT-MRAM device has a stacked structure of a silicon oxide film, a seed layer, a free layer, a tunnel barrier, a fixed layer, a capping layer, a synthetic exchange ferromagnetic layer and an upper electrode on a silicon substrate. Here, the seed layer and the capping layer are formed using tantalum (Ta). The synthetic exchange ferromagnetic layer includes a lower magnetic layer and an upper magnetic layer in which magnetic metal and non-magnetic metal are alternately stacked, and a structure in which a non- .

However, since an amorphous seed layer and a magnetic tunnel junction are formed on the amorphous silicon oxide film, the crystallinity of the magnetic tunnel junction is deteriorated. That is, the fixed layer and the free layer are formed of amorphous CoFeB. However, the crystallinity of the magnetic tunnel junction is not greatly improved even when heat treatment is performed for vertical anisotropy characteristics. If the crystallinity of the magnetic tunnel junction is low, even if a magnetic field is applied to change the magnetization direction, the magnetization direction does not change abruptly, and the amount of current flowing in the parallel state becomes small. Therefore, the read / write time may be delayed, making it difficult to realize a high-speed memory device, and an operation error of the read / write may occur.

In order to implement a large-capacity STT-MRAM device, it is necessary to reduce the dispersion of the magneto-resistance (MR) ratio according to the resistance in the parallel state between the fixed layer and the free layer and the resistance in the anti- It is important to do. That is, when the magnetoresistive ratios of a plurality of magnetic tunnels formed on the same substrate are different, the operation speed of each element becomes different, and the reliability of the element is deteriorated accordingly. The thickness uniformity of the capping layer is important to reduce the dispersion of the magnetoresistance ratio. However, the conventional STT-MRAM device forms a capping layer by using tantalum. Tantalum increases the thickness scattering on the substrate and seriously affects the dispersion of the magnetoresistive ratio. The yield can be reduced.

The present invention relates to a memory device capable of rapidly changing the magnetization direction of a magnetic tunnel junction so as to speed up the operation speed of the read / write operation and to reduce the dispersion of the magnetoresistance ratio, Lt; / RTI >

The present invention provides a memory device capable of improving the crystallinity of a magnetic tunnel junction, thereby rapidly changing the magnetization direction.

The present invention provides a memory device capable of reducing the scattering of the thickness of the capping layer and thereby reducing the dispersion of the magnetoresistive ratio.

A memory device according to an exemplary embodiment of the present invention includes a lower electrode, a magnetic tunnel junction, a capping layer, a synthetic exchange ferromagnetic layer, and an upper electrode laminated on a substrate, wherein the lower electrode includes a first lower electrode of polycrystalline, A lower electrode is laminated.

The second lower electrode and the magnetic tunnel junction are grown amorphously along the crystal structure of the first lower electrode of the polycrystal.

The first lower electrode includes a polycrystalline metal nitride, and the second lower electrode includes an amorphous metal.

The first lower electrode includes TiN, and the second lower electrode includes Ta.

The capping layer is formed of a material having a change in the magnetoresistance ratio of the magnetic tunnel junction within a range of 35% or less as the thickness of the capping layer changes.

The change of the magnetoresistance ratio is 0% to 35% with respect to the thickness variation of 0.3 to 1.2 nm of the capping layer.

The change in the magnetoresistance ratio is 0% to 20% with respect to the thickness variation of 0.4 to 1.0 nm of the capping layer.

The capping layer comprises Ti.

The magnetic tunnel junction has a perpendicularity of magnetization change of more than 0.8 and 1 or less.

A memory device according to another exemplary embodiment of the present invention includes a substrate on which a lower electrode, a magnetic tunnel junction, a capping layer, a composite exchange ferromagnetic layer, and an upper electrode are laminated, the capping layer having a magnetic And a change in the resistance ratio is within 35%.

The lower electrode is formed by stacking a polycrystalline first lower electrode and an amorphous second lower electrode.

The second lower electrode and the magnetic tunnel junction are grown amorphously along the crystal structure of the first lower electrode of the polycrystal.

The first lower electrode includes a polycrystalline metal nitride, and the second lower electrode includes an amorphous metal.

The first lower electrode includes TiN, and the second lower electrode includes Ta.

The change of the magnetoresistance ratio is 0% to 35% with respect to the thickness variation of 0.3 to 1.2 nm of the capping layer.

The change in the magnetoresistance ratio is 0% to 20% with respect to the thickness variation of 0.4 to 1.0 nm of the capping layer.

The capping layer comprises Ti.

The magnetic tunnel junction has a perpendicularity of magnetization change of more than 0.8 and 1 or less.

A memory device according to embodiments of the present invention has a magnetic tunnel junction formed on a lower electrode on which a second lower electrode of an amorphous structure is stacked on a first lower electrode of a polycrystalline structure. In addition, the capping layer on the magnetic tunnel junction is formed using a material having a small change in magnetoresistance ratio according to the thickness distribution.

According to the present invention, an amorphous second lower electrode and an amorphous magnetic tunnel junction are formed along the crystal structure of the crystalline first lower electrode, and the magnetic tunnel junction is further improved in crystallinity by the heat treatment. Therefore, when a magnetic field is applied to the magnetic tunnel junction, the present invention generates a larger magnetization than the conventional magnetization, thereby increasing the amount of current flowing through the magnetic tunnel junction. Further, the change of the magnetization direction of the magnetic tunnel junction can be abrupt. As a result, the operating speed of the memory device can be improved quickly, and operational errors can be reduced to improve reliability.

Further, the capping layer is formed by using a material having a small change in the magnetoresistance ratio according to the thickness distribution, so that the capping layer can be applied to an actual semiconductor process to reduce a change in the magnetoresistance ratio. Therefore, the reliability of the memory element can be improved.

1 is a cross-sectional view of a memory device according to one embodiment of the present invention.
2 is a cross-sectional view of a memory device according to another embodiment of the present invention;
FIGS. 3 and 4 are graphs of characteristics of a conventional memory device and a memory device according to the present invention.
5 is a graph showing a change in the magnetoresistance ratio according to the thickness variation of the capping layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of other various forms of implementation, and that these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know completely.

1 is a cross-sectional view of a memory device according to an embodiment of the present invention, and is a cross-sectional view of an STT-MRAM device.

Referring to FIG. 1, a memory device according to an embodiment of the present invention includes a lower electrode 110 formed on a substrate 100, a free layer 120, a tunneling barrier 130, a pinning layer 140, a capping layer (not shown) 150, a composite exchangeable semiconductive layer 160, and an upper electrode 170. Here, the free layer 120, the tunneling barrier 130, and the pinned layer 140 form a magnetic tunnel junction.

The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a silicon oxide film substrate, or the like. In this embodiment, a silicon substrate is used. An insulating layer 105 may be formed on the substrate 100. As the insulating layer 105, a silicon oxide film (SiO ₂ ) having an amorphous structure or the like can be used.

The lower electrode 110 is formed on the insulating layer 105. The lower electrode 110 may be formed using a conductive material, such as a metal, a metal oxide, a metal nitride, or the like. In addition, the lower electrode 110 of the present invention may be formed as a double structure of the first and second lower electrodes 112 and 114. Here, the first lower electrode 112 may be formed on the insulating layer 105, and the second lower electrode 114 may be formed on the first lower electrode 112. In addition, the first lower electrode 112 may be formed of a polycrystalline material, and the second lower electrode 114 may be formed of an amorphous material. For example, the first lower electrode 112 may be formed of a metal nitride such as a titanium nitride (TiN), and the second lower electrode 114 may be formed of tantalum (Ta), ruthenium (Ru), titanium (Ti) May be formed of palladium (Pd), platinum (Pt), magnesium (Mg), aluminum (Al), or alloys thereof, specifically Ta. Since the first lower electrode 112 is formed of a polycrystalline material, the crystallinity of the magnetic tunnel junction formed later can be improved. That is, when the polycrystalline first lower electrode 112 is formed, the amorphous second lower electrode 114 and the amorphous magnetic tunnel junction formed on the first lower electrode 112 are grown along the crystal direction of the first lower electrode 112, Then, if the heat treatment is performed for perpendicular anisotropy, the magnetic tunnel junction can be improved in crystallinity. That is, since an amorphous seed layer and an amorphous magnetic tunnel junction are conventionally formed on an amorphous insulating layer, the crystallinity is not improved as compared with the present invention even after the heat treatment. When the crystallinity of the magnetic tunnel junction is improved, the magnetization becomes larger when the magnetic field is applied and the current flowing through the magnetic tunnel junction becomes larger in the parallel state. Therefore, application of such a magnetic tunnel junction to a memory device can improve the operating speed and reliability of the device.

The free layer 120 is formed on the second lower electrode 114, and is formed of a ferromagnetic material. The free layer 120 can be changed from one direction to the opposite direction, in which magnetization is not fixed in one direction. That is, the free layer 120 may have the same (i.e., parallel) magnetization direction as the pinned layer 140 and vice versa (i.e., antiparallel). The magnetic tunnel junction can be utilized as a memory element by mapping information of '0' or '1' to a resistance value that varies depending on the magnetization arrangement of the free layer 120 and the pinned layer 140. For example, when the magnetization direction of the free layer 120 is parallel to the fixed layer 140, the resistance value of the magnetic tunnel junction becomes small, and this case can be defined as data '0'. In addition, when the magnetization direction of the free layer 120 is antiparallel to the fixed layer 140, the resistance value of the magnetic tunnel junction becomes large, and this case can be defined as data '1'. The free layer 120 may be formed of, for example, an amorphous rare-earth element alloy, a multilayer thin film in which a ferromagnetic metal and a nonmagnetic metal are alternately stacked, an alloy having a L10 type crystal structure, a cobalt-based alloy, or the like Of a ferromagnetic material. The amorphous rare earth element alloys include alloys such as TbFe, TbCo, TbFeCo, DyTbFeCo, and GdTbCo. Co / Pt, Co / Ru, Co / Os, Co / Au, Ni / Cu, CoFeAl / Pd, and CoFeAl as the multilayered thin film in which the nonmagnetic metal and the magnetic metal are alternately stacked. / Pt, CoFeB / Pd, CoFeB / Pt, and the like. Examples of alloys having an L10 type crystal structure include Fe50Pt50, Fe50Pd50, Co50Pt50, Fe30Ni20Pt50, Co30Ni20Pt50, and the like. Examples of the cobalt-based alloys include CoCr, CoPt, CoCrPt, CoCrTa, CoCrPtTa, CoCrNb and CoFeB. Among these materials, the CoFeB single layer can be formed thicker than the multi-layer structure of CoFeB and Co / Pt or Co / Pd, thereby increasing the magnetoresistance ratio. In addition, since CoFeB is easier to etch than metals such as Pt or Pd, the CoFeB single layer is easier to manufacture than a multilayer structure containing Pt or Pd. Thus, an embodiment of the present invention forms a free layer 120 using a CoFeB monolayer, and CoFeB is formed into amorphous and then textured into BCC 100 by heat treatment.

A tunneling barrier 130 is formed on the free layer 120 to separate the free layer 120 and the pinning layer 140. The tunneling barrier 130 allows quantum mechanical tunneling between the free layer 120 and the pinned layer 140. The tunneling barrier 130 is magnesium oxide (MgO), aluminum oxide (Al ₂ O _3), silicon oxide (SiO _2), tantalum oxide (Ta ₂ O _5), silicon nitride (SiNx) or aluminum nitride (AlNx), etc. As shown in FIG. In an embodiment of the present invention, polycrystalline magnesium oxide is used as the tunneling barrier 130. The magnesium oxide is then textured to the BCC 100 by heat treatment.

The pinned layer 140 is formed on the tunnel barrier 130. The fixed layer 140 is fixed in one direction in a magnetic field within a predetermined range, and may be formed of a ferromagnetic material. For example, the magnetization may be fixed in the direction from the bottom to the top. The pinning layer 140 may be formed of a ferromagnetic material such as an amorphous rare earth element alloy, a multilayer thin film in which a magnetic metal and a nonmagnetic metal are alternately laminated, or an alloy having an L10 type crystal structure. At this time, the pinned layer 140 may be formed of the same ferromagnetic material as the free layer 120, and may be formed of a single CoFeB layer. CoFeB is formed into an amorphous material and then textured into a BCC (100) by heat treatment.

The capping layer 150 is formed on the pinned layer 140 to magnetically separate the pinned layer 140 and the composite exchangeable magnetic layer 160. By forming the capping layer 150, the magnetization of the composite exchange-forming semi-magnetic layer 160 and the pinning layer 140 are generated independently of each other. The capping layer 150 may be formed in consideration of the magnetoresistance ratio of the free layer 120 and the pinned layer 140 for the operation of the magnetic tunnel junction. The capping layer 150 may be formed of a material that allows the synthetic exchangeable semiconductive layer 160 to undergo crystal growth. In addition, the capping layer 150 can be formed using a material having a small dispersion of the magnetoresistance ratio according to the thickness distribution. Here, the thickness distribution of the capping layer 150 can be defined as the difference in thickness between the capping layer 150 formed on the same plane and the thickness average value. That is, it is possible to implement a memory device using each of a plurality of magnetic tunnel junctions as one cell. If the thickness distribution of the capping layer 150 of each cell is increased, the dispersion of the magnetoresistance ratio of each cell becomes larger, Reliability may be deteriorated. Therefore, the capping layer 150 of the present invention can be formed of a material having a small change in magnetoresistance ratio according to a change in thickness. For example, the capping layer 150 may be formed using a material whose magnetoresistance ratio varies from 0% to 35% in accordance with a thickness variation of 0.3 nm to 1.2 nm. As such a material, titanium (Ti) can be used and can be formed by epitaxial sputtering.

A composite exchangeable semiconductive layer 160 is formed on the capping layer 150. The composite exchangeable semi-magnetic layer 160 serves to fix the magnetization of the pinned layer 140. The synthetic exchange semiconductive layer 160 includes a first magnetic layer 161, a nonmagnetic layer 162, and a second magnetic layer 163. That is, the first magnetic layer 161 and the second magnetic layer 163 are antiferromagnetically coupled through the non-magnetic layer 162 in the synthetic exchange magnetic layer 160. At this time, the magnetization directions of the first magnetic layer 161 and the second magnetic layer 163 are arranged antiparallel. For example, the first magnetic layer 161 may be magnetized upward (i.e., in the direction of the upper electrode 170), and the second magnetic layer 163 may be magnetized in a downward direction (i.e., magnetic tunnel junction direction). The first magnetic layer 161 and the second magnetic layer 163 may be formed by alternately stacking a magnetic metal and a non-magnetic metal. As the magnetic metal, a single metal selected from the group consisting of iron (Fe), cobalt (Co) and nickel (Ni), or an alloy thereof may be used. As the nonmagnetic metal, chromium (Cr), platinum A single metal selected from the group consisting of palladium (Pd), iridium (Ir), rhodium (Rh), ruthenium (Ru), osmium (Os), rhenium (Re), gold (Au) Can be used. For example, the first magnetic layer 161 and the second magnetic layer 163 may be formed of [Co / Pd] n, [Co / Pt] n or [CoFe / Pt] n . The nonmagnetic layer 162 is formed between the first magnetic layer 161 and the first magnetic layer 163 and is made of a nonmagnetic material that allows the first magnetic layer 161 and the second magnetic layer 163 to perform a half- . For example, the nonmagnetic layer 162 may be formed of a single material selected from the group consisting of ruthenium (Ru), rhodium (Rh), osmium (Os), rhenium (Re), and chromium (Cr) or an alloy thereof.

The upper electrode 170 is formed on the composite exchangeable semi-magnetic layer 160. The upper electrode 170 may be formed using a conductive material, such as a metal, a metal oxide, a metal nitride, or the like. For example, the upper electrode 170 may be a single electrode selected from the group consisting of tantalum (Ta), ruthenium (Ru), titanium (Ti), palladium (Pd), platinum (Pt), magnesium (Mg) Metal, or an alloy thereof.

2 is a cross-sectional view of a memory device according to another embodiment of the present invention.

Referring to FIG. 2, a memory device according to another embodiment of the present invention includes a lower electrode 110 formed on a substrate 100, a free layer 120, a tunneling barrier 130, a pinning layer 140, a capping layer 150, a buffer layer 180, a composite exchangeable semiconductive layer 160, and an upper electrode 170. In other words, the memory device according to another embodiment of the present invention further includes a buffer layer 180 between the capping layer 150 and the synthetic exchange semiconductive layer 160, as compared to the memory device according to an embodiment of the present invention. The buffer layer 180 allows the first and second magnetic layers 161 and 163 of the composite exchangeable semi-magnetic layer 160 to grow in a desired crystal orientation. For example, it may be formed of a metal that facilitates crystal growth in a (111) direction of a face centered cubic (FCC) or a (001) direction of a hexagonal close-packed structure have. These metals include metals selected from the group consisting of tantalum (Ta), ruthenium (Ru), titanium (Ti), palladium (Pd), platinum (Pt), magnesium (Mg), cobalt (Co) These alloys may be formed, for example, by a stacked structure of Pt / Co.

As described above, in the memory device according to the embodiments of the present invention, the lower electrode 110 under the magnetic tunnel junction is formed in a stacked structure of the polycrystalline first lower electrode 112 and the amorphous second lower electrode 112 And the capping layer 150 are formed by using a material having a small change in magnetoresistance ratio according to the thickness distribution. The first lower electrode 112 is formed of a polycrystalline material so that an amorphous second lower electrode 112 and an amorphous magnetic tunnel junction formed on the first lower electrode 112 are formed along the crystal structure of the first lower electrode 112, Thereafter, by a heat treatment, a crystal structure is further improved as compared with the conventional one. That is, in the vertical magnetization type magnetic tunnel junction, the (100) direction texturing of the body centered cubic (BCC) structure of the free layer, the tunneling barrier and the fixed layer is important. For this purpose, a magnetic tunnel junction is formed by forming an amorphous free layer, a polycrystalline tunneling barrier, an amorphous fixed layer, and an amorphous capping layer on an amorphous seed layer, and annealing for vertical anisotropy property to form CoFeB B is diffused into the Ta seed layer and the Ta capping layer, respectively, and the orthorhombic characteristic of the interface is obtained by orbital mixing of Co or Fe of CoFeB and O of the MgO tunneling barrier. In addition, the fixed and free layers and the seed layer from the tunneling barrier are textured to the BCC 100. However, in the present invention, a polycrystalline TiN layer is formed as a first lower electrode, and an amorphous Ta second lower electrode is formed thereon, thereby securing an interface of a flat seed layer and improving BCC (100) crystallinity of a magnetic tunnel junction . The characteristics of the memory device according to an embodiment of the present invention and the conventional memory device are as follows.

FIGS. 3 and 4 are characteristic graphs of a conventional memory device and a memory device according to an embodiment of the present invention. Fig. 3 is a schematic view showing a state in which a silicon oxide film, a Ta seed layer (5 nm), a CoFeB free layer (1.05 nm), a MgO tunneling barrier (1 nm), a CoFeB pinning layer (1.2 nm) and a Ta capping layer Which is a graph of magnetization according to the magnetic field of a conventional pseudo spin valve. 4 shows a silicon oxide film, a TiN first lower electrode, a Ta second lower electrode (5 nm), a CoFeB free layer (1.05 nm), a MgO tunneling barrier (1 nm), a CoFeB pinning layer And a Ta capping layer (5 nm) are stacked on a silicon substrate, according to embodiments of the present invention. 3 (a) and 4 (a) are graphs of horizontal and vertical magnetizations when vertical and horizontal magnetic fields are applied to the pseudo-spin valve according to the prior art and the present invention, b) is a detailed graph of the vertical magnetization of the conventional and the pseudo-spin valve according to the present invention. That is, FIGS. 3B and 4B are enlarged graphs showing the vertical portions of the vertical magnetization shown in FIGS. 3A and 4A in detail. The direction of the arrow in the graph is the magnetization direction of the free layer and the pinned layer.

As shown in FIG. 4 (a), the pseudo-spindle valve according to the present invention has a larger magnetization in accordance with the same magnetic field as the conventional pseudo-spin valve, as shown in FIG. If a large magnetization is generated, more current flows in the parallel state, and it can be understood that the crystallinity of the magnetic tunnel junction is improved as compared with the conventional one. In addition, a triangular crossing space is provided between the graph of the vertical magnetization and the graph of the horizontal magnetization, and the intersection space of these triangles represents the perpendicular magnetic anisotropy (Ku). The larger the crossing space of the triangle is, the larger the perpendicular magnetic anisotropy is, and the larger the perpendicular magnetic anisotropy, the greater the mobility from the horizontal magnetization to the vertical magnetization. However, in the conventional case, the vertical magnetic anisotropy Ku is about 2.6 × 10 ⁶ erc / cc, and in the present invention, the vertical magnetic anisotropy Ku is 3.2 × 10 ⁶ erc / cc. That is, it can be seen that the present invention improves the perpendicular magnetic anisotropy by about 23% as compared with the prior art.

3 (b) and 4 (b), when the free layer and the pinned layer are magnetized in a direction in which the magnetization in one direction is generated and the magnetization is changed in a direction opposite to the other direction After maintaining the magnetization of the current one direction to some extent, it changes into magnetization of the other direction, which is called a coercive force. As shown in FIG. 3 (b), in the conventional pseudo spin valve, when a magnetic field is applied to change the magnetization in the other direction after the magnetization is generated in the fixed layer and the free layer in one direction, At least one of the magnetizations changes later. For example, the magnetization changes in the direction between the upper side and the lower side without changing directly from the magnetization in the upper direction to the lower direction, and then the magnetization changes in the lower direction. If the change of magnetization does not occur immediately, the operation time of the read / write operation may be delayed by being applied to the memory device. That is, the operation speed of the memory element can be slowed down. However, as shown in FIG. 4 (b), in the pseudo spin valve of the present invention, when the fixed layer and the free layer are magnetized in one direction and then the magnetization is changed in the other direction, the magnetization of the fixed layer immediately reacts. When the change of magnetization occurs immediately, the operation time of the read / write can be increased by applying to the memory device. That is, the operating speed of the memory element can be increased. On the other hand, when magnetization changes from magnetization in one direction to magnetization in the other direction, a substantially quadrilateral graph is formed by the coercive force as shown in Figs. 3 (b) and 4 (b). At this time, if the squareness of the rectangle is 1 in the case of the present invention, it is 0.8 in the conventional case, and the present invention has an improvement effect of about 25% as compared with the conventional case. As the perpendicularity increases, the magnetization changes rapidly, so that the operating speed of the memory device can be increased.

5 is a graph showing the change of the magnetoresistance ratio with the thickness variation of the capping layer of the memory element. Table 1 also shows the change of the magnetoresistance ratio and the exchange magnetic field (Hex) according to the thickness of the capping layer. Here, the comparative example uses Ta as the capping layer, and the embodiment of the present invention uses Ti as the capping layer. That is, a TiN first lower electrode, a Ta second lower electrode (5 nm), a CoFeB free layer (1.05 nm), a MgO tunneling barrier (1 nm), a CoFeB pinned layer (1 nm) , A Co (Pd) ₇ first magnetic layer, a Ru nonmagnetic layer (0.6 nm), a [Co / Pd] ₁₀ second magnetic layer and a Ru upper electrode (15 nm) The comparative example uses Ta as the capping layer, and the embodiment of the present invention uses Ti as the capping layer. Here, the first and second magnetic layers were formed to have a thickness of 0.25 nm of Co, a Pd of 1 nm, and laminated seven times and nine times, respectively. In addition, heat treatment was performed at 275 ° C for perpendicular anisotropy.

Thickness (nm) 0.3 0.4 0.6 0.8 1.0 1.2 Comparative Example
MR (%) 59 64 54 40 One 0 Hex (kOe) 2.0 2.0 1.9 2.0 2.1 2.1 Example
MR (%) 44 55 68 62 58 49 Hex (kOe) 2.0 2.1 2.0 2.0 2.0 2.0

As shown in Fig. 5 and Table 1, the thickness with the optimum magnetoresistive ratio is 0.4 nm for Ta and 0.6 nm for Ti. In addition, when the thickness increases or decreases from the thickness having the optimum magnetoresistance ratio, (A), the magnetoresistance ratio of Ta is changed abruptly, but Ti is slightly changed (B). That is, as the thickness increases, the magnetoresistance ratio of Ta changes abruptly from 59 to 0, but the magnetoresistance ratio of Ti changes gently from 68 to 44. That is, Ti has a magnetoresistance ratio varying within 35% according to the thickness change from the thickness having the optimum magnetoresistance ratio. Also, the magnetoresistance ratio of Ti is changed within 20% according to the thickness variation of 0.4 nm to 1.0 nm. From this, considering the fact that the actual sputtering process uniformity distribution in the semiconductor process is about 2 Å, which is the interval between one atomic layer, the magnetoresistance ratio changes by 5.3% and the magnetoresistance ratio by Ti changes by 2.5%. Therefore, the dispersion of the magnetoresistance ratio can be reduced to 47% of Ti compared to Ta. On the other hand, both the Ti and Ta capping layers maintain an exchange magnetic field (Hex) of 2000 Oe.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

100: substrate 110: lower electrode
120: fixed layer 130: tunneling barrier
140: free layer 150: capping layer
160: Synthetic exchange-ferromagnetic layer 170: Upper electrode
180: buffer layer

Claims (18)

A lower electrode, a magnetic tunnel junction, a capping layer, a composite exchange ferromagnetic layer and an upper electrode are laminated on a substrate,
Wherein the lower electrode comprises a polycrystalline first lower electrode and an amorphous second lower electrode.
The memory element according to claim 1, wherein the second lower electrode and the magnetic tunnel junction are grown amorphously along a crystal structure of the first lower electrode of the polycrystal.
The memory element of claim 2, wherein the first lower electrode comprises a polycrystalline metal nitride and the second lower electrode comprises an amorphous metal.
4. The memory element of claim 3, wherein the first lower electrode comprises TiN and the second lower electrode comprises Ta.
[2] The memory device of claim 1, wherein the capping layer is formed of a material having a change in magnetoresistance ratio of the magnetic tunnel junction within a range of 35% or less.
The memory element according to claim 5, wherein a change in the magnetoresistance ratio with respect to a change in thickness of 0.3 to 1.2 nm of the capping layer is 0% to 35%.
7. The memory element according to claim 6, wherein a change in the magnetoresistance ratio of the capping layer with respect to a change in thickness of 0.4 nm to 1.0 nm is 0% to 20%.
7. The memory element of claim 6, wherein the capping layer comprises Ti.
The memory device of claim 1, wherein the magnetic tunnel junction has a perpendicularity of magnetization change of more than 0.8 and less than or equal to 1.
A lower electrode, a magnetic tunnel junction, a capping layer, a composite exchange ferromagnetic layer and an upper electrode are laminated on a substrate,
Wherein the capping layer is formed of a material having a change in the magnetoresistive ratio of the magnetic tunnel junction within a range of 35% or less.
The memory element of claim 10, wherein the lower electrode comprises a polycrystalline first lower electrode and an amorphous second lower electrode.
The memory element according to claim 11, wherein the second lower electrode and the magnetic tunnel junction are grown amorphously along the crystal structure of the first lower electrode of the polycrystal.
13. The memory device of claim 12, wherein the first lower electrode comprises a polycrystalline metal nitride and the second lower electrode comprises an amorphous metal.
14. The memory element of claim 13, wherein the first lower electrode comprises TiN and the second lower electrode comprises Ta.
The memory element according to claim 10 or 11, wherein a change in the magnetoresistance ratio with respect to a change in thickness of 0.3 to 1.2 nm of the capping layer is 0% to 35%.
16. The memory element according to claim 15, wherein a change in the magnetoresistance ratio with respect to a thickness variation of 0.4 to 1.0 nm of the capping layer is 0% to 20%.
16. The memory element of claim 15, wherein the capping layer comprises Ti.
12. The memory device according to claim 10 or 11, wherein the magnetic tunnel junction has a perpendicularity of magnetization change of more than 0.8 and less than or equal to 1.

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