KR101956977B1 - Memory device - Google Patents
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- KR101956977B1 KR101956977B1 KR1020160015154A KR20160015154A KR101956977B1 KR 101956977 B1 KR101956977 B1 KR 101956977B1 KR 1020160015154 A KR1020160015154 A KR 1020160015154A KR 20160015154 A KR20160015154 A KR 20160015154A KR 101956977 B1 KR101956977 B1 KR 101956977B1
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- H01L43/02—
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
- G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
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- H01L43/08—
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- H01L43/10—
Abstract
The present invention discloses a memory device in which a seed layer, a synthetic exchange ferromagnetic layer, a separation layer, a magnetic tunnel junction and a capping layer are laminated between two electrodes, and a synthetic exchange ferromagnetic layer has one magnetic layer and a non-magnetic layer, respectively .
Description
BACKGROUND OF THE
Studies are being made on a next generation nonvolatile memory device having a lower power consumption and higher integration than a flash memory device. These next generation non-volatile memory devices include a phase change memory (PRAM) that utilizes a state change of a phase change material such as a chalcogenide alloy, a magnetic tunnel junction (PMR) according to a magnetization state of a ferromagnetic material, (MRAM) using resistance change of MTJ, ferroelectric RAM using polarization of ferroelectric material, resistance change RAM (ReRAM) using resistance change of variable resistance material, etc. .
An STT-MRAM (Spin-Transfer Torque Magnetic Random Access Memory) device for inverting magnetization by using a spin transfer torque (STT) phenomenon by electron injection as a magnetic memory and discriminating the difference in resistance before and after magnetization inversion . The STT-MRAM devices each include a pinned layer and a free layer formed of a ferromagnetic material, and a magnetic tunnel junction formed with a tunnel barrier therebetween. If the magnetization directions of the free layer and the pinned layer are the same (i.e., parallel), the magnetic tunnel junction has a low resistance state due to easy current flow, and if the magnetization directions are different (i.e., anti parallel) Resistance state. In addition, since the magnetization direction of the magnetic tunnel junction must change only in the direction perpendicular to the substrate, the free layer and the pinned layer must have perpendicular magnetization values. The vertical magnetic anisotropy (PMA) is superior when the vertical magnetization value is symmetrical with respect to zero according to the intensity and direction of the magnetic field and the shape of the squareness (S) becomes clear (S = 1) . These STT-MRAM devices can theoretically be cycled at 10 15 or more, and can be switched at a speed as high as nanoseconds (ns). In particular, the vertical magnetization type STT-MRAM device has no scaling limit in theory, and the current density of the driving current can be lowered as the scaling progresses. Therefore, the research is being actively conducted as a next generation memory device that can replace the DRAM device . On the other hand, an example of an STT-MRAM device is disclosed in Korean Patent No. 10-1040163.
In the STT-MRAM device, a seed layer is formed under the free layer, a separation layer is formed on the fixed layer, and a synthetic exchange ferromagnetic layer and an upper electrode are formed on the separation layer. In the STT-MRAM device, a silicon oxide film is formed on a silicon substrate, and then a seed layer and a magnetic tunnel junction are formed thereon. A selection element such as a transistor may be formed on the silicon substrate, and a silicon oxide film may be formed so as to cover the selection element. Therefore, the STT-MRAM device has a stacked structure of a silicon oxide film, a seed layer, a free layer, a tunnel barrier, a fixed layer, a separation layer, a synthetic exchange ferromagnetic layer and an upper electrode on a silicon substrate on which a selection element is formed. Here, the separating layer and the capping layer are formed using tantalum (Ta), and the synthetic exchange ferromagnetic layer includes a lower magnetic layer and an upper magnetic layer in which magnetic metal and nonmagnetic metal are alternately stacked, and a structure in which a nonmagnetic layer is formed therebetween . That is, a magnetic tunnel junction is formed on the lower side of the substrate, and a composite exchangeable semi-magnetic layer is formed on the upper side.
However, since the synthetic exchange ferromagnetic layer of fcc (111) is formed on the magnetic tunnel junction textured in the bcc (100) direction, the fcc (111) structure diffuses into the magnetic tunnel junction when forming the synthetic exchange ferromagnetic layer, ) Decision. That is, when forming the composite exchangeable semi-magnetic layer, a part of the material diffuses into the magnetic tunnel junction, which may deteriorate the crystallinity of the magnetic tunnel junction. Therefore, the magnetization direction of the magnetic tunnel junction can not be changed suddenly, so that the operation speed of the memory may decrease or the operation may not be performed.
Further, the synthetic exchangeable semiconductive layer is mainly composed of a laminate of a first magnetic layer having a multilayer structure, a non-magnetic layer, and a second magnetic layer having a multilayer structure. For example, the first magnetic layer is formed by laminating Co and Pt repeatedly at least six times, and the second magnetic layer is formed by laminating Co and Pt repeatedly at least three times. Since the first and second magnetic layers are each formed in a multi-layered structure, the thickness of the memory element becomes thick. In addition, since rare-earth is often used for the first and second magnetic layers, the process cost is also increased.
The present invention provides a memory device capable of preventing the diffusion of a synthetic exchange-semiconductive layer material to a magnetic tunnel junction to improve the crystallinity of a magnetic tunnel junction.
The present invention provides a memory device capable of reducing the thickness of the synthetic exchange ferromagnetic layer to reduce the process cost and reduce the overall thickness.
A memory device according to an aspect of the present invention includes a seed layer, a composite exchange ferromagnetic layer, a separation layer, a magnetic tunnel junction and a capping layer laminated between two electrodes, and the synthetic exchange ferromagnetic layer has a single magnetic layer and a non- Respectively.
A magnetic tunnel junction is formed on the composite exchange-ferromagnetic layer.
And a buffer layer provided between the composite exchangeable semiconductive layer and the separation layer.
The buffer layer has a single layer formed of a magnetic material, and is formed to be thinner than the magnetic layer of the synthetic exchange-ferromagnetic layer.
And an oxide layer formed between the magnetic tunnel junction and the capping layer.
The memory element according to another aspect of the present invention is characterized in that the magnetic tunnel junction comprises a pinned layer, a tunnel barrier and a free layer, wherein the free layer comprises first and second free layers and an interposed layer formed therebetween.
The first and second free layers are formed of a material including CoFeB, and the first free layer is formed to be thinner or the same thickness as the second free layer.
The isolation layer is formed of a material having a bcc structure and is formed to a thickness of 0.1 nm to 0.5 nm.
In the present invention, the lower electrode is formed of a polycrystalline material, and a synthetic exchange ferromagnetic layer is formed on the lower electrode, followed by formation of a magnetic tunnel junction. Therefore, since the fcc (111) structure of the composite exchange ferromagnetic layer is not diffused into the magnetic tunnel junction, the bcc (100) crystal of the magnetic tunnel junction can be conserved and the magnetization direction of the magnetic tunnel junction can be rapidly changed The operating speed of the memory can be improved.
Furthermore, by forming the composite exchangeable semi-magnetic layer so as to have one magnetic layer and a nonmagnetic layer, respectively, the thickness of the composite exchangeable semi-magnetic layer can be reduced, and the thickness of the entire memory device can be reduced. In addition, the amount of material used for forming the composite exchangeable semiconductive layer can be reduced to reduce the process cost.
1 is a cross-sectional view of a memory device according to one embodiment of the present invention.
2 is a view showing a magnetoresistive ratio of a comparative example according to a thickness of a separation layer and an embodiment of the present invention.
3 is a diagram showing the tunnel magnetoresistance ratio according to the position of the composite exchange-ferromagnetic layer and the thickness of the separation layer in the embodiments of the present invention.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but is capable of other various forms of implementation, and that these embodiments are provided so that this disclosure will be thorough and complete, It is provided to let you know completely.
1 is a cross-sectional view of a memory device according to an embodiment of the present invention, and is a cross-sectional view of an STT-MRAM device.
1, a memory device according to an embodiment of the present invention includes a
The
A
The
A seed layer (130) is formed on the first buffer layer (120). The
A composite exchangeable
A
The
The pinned
The
A
A
The
The
As described above, in the memory device according to the embodiments of the present invention, the
FIG. 2 is a view showing a comparative example according to the thickness of the separation layer and a magnetic resistance (MR) ratio of the embodiment of the present invention. That is, a magnetic tunnel junction including a lower electrode, a seed layer, a synthetic exchange ferromagnetic layer, a separation layer, a free layer of a dual structure, a capping layer and an upper electrode are laminated from a substrate, Magnetic layer, a nonmagnetic layer, and a second magnetic layer, and the examples were formed by the structure of the magnetic exchange layer and the nonmagnetic layer in the synthetic exchangeable semiconductive layer. In the comparative example, the first magnetic layer was formed of [Co / Pt] 6 and the second magnetic layer was formed of [Co / Pt] 3. In this example, the magnetic layer was formed of [Co / Pt] 3. In addition, the embodiment formed a buffer layer of Co / Pt between the synthetic exchangeable semiconductive layer and the separation layer. The separation layer was formed using W, and the thickness was varied from 0.1 nm to 0.5 nm. As shown in Fig. 2, in the comparative example (A), the magnetoresistance ratio of the separation layer is 0.2% to 0.3 nm, which is the maximum at about 160%. Incidentally, in the embodiment, the magnetoresistive ratio of the (B) separating layer is 0.2 nm to 0.3 nm and the maximum is shown by about 179%. Therefore, it can be seen that the embodiment of the present invention has a magnetoresistance ratio as high as about 20% as compared with the comparative example. This is because the amount of metal diffused into the magnetic tunnel junction decreases as the thickness of the composite exchange-bismuth layer decreases.
FIG. 3 is a diagram showing the tunnel magnetoresistance ratio according to the position of the composite exchangeable semi-magnetic layer and the thickness of the separation layer. FIG. That is, the magnetoresistive ratio in the case where the composite exchangeable semi-magnetic layer having one magnetic layer and the non-magnetic layer are located on the upper side of the tunnel magnetic junction (Example 1) and the case where the composite exchange magnetic domain is located on the lower side of the tunnel magnetic junction Respectively. Example 1 is a lamination of a tunneling magnetic junction having a lower electrode, a seed layer, a double free layer, a separation layer, a composite exchangeable semiconductive layer according to the present invention, a capping layer and an upper electrode on a substrate, A tunneling magnetic junction having a lower electrode, a seed layer, a composite exchangeable semiconductive layer according to the present invention, a separation layer, a double free layer, a capping layer, and an upper electrode were laminated on the substrate. As shown in FIG. 3, in the case of Example 1 (C), the magnetoresistance ratio of the isolation layer at 0.55 nm is the maximum at about 158%. Incidentally, in Example 2 (D), the magnetoresistance ratio of the separation layer at the thickness of 0.2 nm to 0.3 nm is the maximum at about 179%. Therefore, it can be seen that the magneto-resistance ratio of Example 2 of the present invention is higher than that of Comparative Example 2 by about 20%. This is because the material of the synthetic exchange ferromagnetic layer diffuses into the magnetic tunnel junction when the synthetic exchange ferromagnetic layer is formed on the upper side of the magnetic tunnel junction, but when the synthetic exchange ferromagnetic layer is formed below the magnetic tunnel junction, Because it does not diffuse into the tunnel junction.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.
100: substrate 110: lower electrode
120: first buffer layer 130: seed layer
140: synthetic exchange ferromagnetic layer 150: second buffer layer
160: separation layer 170: fixed layer
180: tunnel barrier 190: free layer
200: third buffer layer 210: capping layer
220: upper electrode
Claims (9)
Wherein the composite exchangeable semi-magnetic layer has one magnetic layer and one non-magnetic layer,
Wherein the one magnetic layer is formed of a structure in which a magnetic metal and a non-magnetic metal are repeatedly laminated a plurality of times.
Wherein the free layer comprises first and second free layers and an interposed layer formed therebetween.
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020160015154A KR101956977B1 (en) | 2016-02-05 | 2016-02-05 | Memory device |
US16/075,474 US10453510B2 (en) | 2016-02-05 | 2017-02-03 | Memory device |
PCT/KR2017/001234 WO2017135767A1 (en) | 2016-02-05 | 2017-02-03 | Memory device |
CN202310098689.5A CN115915906A (en) | 2016-02-05 | 2017-02-03 | Memory device |
CN201780022500.7A CN109155360A (en) | 2016-02-05 | 2017-02-03 | memory device |
US16/389,458 US10643681B2 (en) | 2016-02-05 | 2019-04-19 | Memory device |
US16/671,501 US10854254B2 (en) | 2016-02-05 | 2019-11-01 | Memory device |
US16/686,510 US10783945B2 (en) | 2016-02-05 | 2019-11-18 | Memory device |
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KR1020160015154A KR101956977B1 (en) | 2016-02-05 | 2016-02-05 | Memory device |
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KR20170093576A KR20170093576A (en) | 2017-08-16 |
KR101956977B1 true KR101956977B1 (en) | 2019-03-11 |
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Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
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US20140306305A1 (en) * | 2011-01-19 | 2014-10-16 | Headway Technologies, Inc. | Magnetic Tunnel Junction for MRAM Applications |
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KR101040163B1 (en) | 2008-12-15 | 2011-06-09 | 한양대학교 산학협력단 | STT-MRAM device comprising multi-level cell and driving method thereof |
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US20140306305A1 (en) * | 2011-01-19 | 2014-10-16 | Headway Technologies, Inc. | Magnetic Tunnel Junction for MRAM Applications |
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