KR20140083680A - Organic light emitting display device and method for driving thereof - Google Patents

Abstract

An organic light emitting display device according to the present invention, which can minimize an output deviation between analog to digital converters, comprises: a display panel including multiple pixels formed in the intersection region of gate lines, data lines, and sensing lines; a gate driving unit to supply a gate signal to the gate lines; multiple data driving integrated circuits, each including a data driving unit to supply a data voltage to the data lines and a sensing unit having multiple analog to digital converters which generate sensing data by sensing characteristic change information of a driving transistor included in each pixel through the sensing lines; a memory to store a gain error and an offset error of each analog to digital converter; and a timing control unit to correct the sensing data based on the gain error and the offset error, modulate input data based on the corrected sensing data, and supply the modulated data to the data driving integrated circuits.

Description

Technical Field [0001] The present invention relates to an organic light emitting diode (OLED) display device,

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to an organic light emitting display, and more particularly, to an organic light emitting display and a method of driving the same, which can improve brightness uniformity of an image by compensating for a change in characteristics of a driving transistor.

Recently, with the development of multimedia, the importance of flat panel display devices is increasing. In response to this, flat panel display devices such as liquid crystal display devices, plasma display devices, and organic light emitting display devices have been commercialized.

Of the flat panel display devices, the organic light emitting display device displays an image using an organic light emitting device that generates light by recombination of electrons and holes. The organic light emitting display device has a high response speed and self- Devices.

One pixel of a general organic light emitting display includes a pixel circuit including an organic light emitting element and a driving transistor for driving the organic light emitting element. However, since the threshold voltage / mobility characteristic of the driving transistor is different for each pixel in accordance with the non-uniformity of the manufacturing process of the thin film transistor and the driving time of a general organic light emitting display device, the amount of current flowing to the driving transistor of each pixel . The deviation of the amount of current flowing to the driving transistor of each of these pixels causes a luminance variation between the pixels, thereby lowering the uniformity of image quality. A method for solving such a problem is disclosed in Korean Patent Laid-Open No. 10-2010-0047505 (hereinafter referred to as "Prior Patent Document 1"), Korean Patent Laid-Open Publication No. 10-2011-0066506 (hereinafter referred to as " Patent Document 2 "), and Korean Patent Registration No. 10-1073226 (hereinafter referred to as" Prior Patent Document 3 ").

The above prior art documents disclose a technique of forming a sensing transistor and a sensing line in each pixel and using the analog-to-digital converter of a sensing part included in a data driver, i.e., a data driver integrated circuit, And corrects the data according to the sensed voltage, thereby compensating for a change in the characteristics of the driving transistor, thereby preventing a deterioration in image quality due to a luminance deviation between the pixels.

However, in general, the analog-to-digital converter has a gain error and an offset error, and is output from the analog-to-digital converter according to the process deviation between the data driving integrated circuits by the manufacturing process of the data driving integrated circuit A deviation occurs in the output data, and a deviation also occurs between the analog-digital converters in the data driving integrated circuit.

The gain error refers to an error in which the actual digital output deviates by a certain ratio as compared with an ideal digital output for the analog input. The gain error occurs when the value exactly matched at the center of the analog input range approaches the minimum value and the maximum value of the analog input range .

Offset error refers to an error in which the actual digital output deviates by a certain amount from the ideal digital output to the analog input. This means that the measured value is totally high or low when the user knows the signal.

FIG. 1 is a waveform diagram showing output data according to an input voltage of an analog-to-digital converter, and FIG. 2 is a waveform diagram for explaining an output deviation between a plurality of data driving integrated circuits in a general organic light emitting display.

In FIG. 1, a graph A is a graph showing ideal output data according to an input voltage, and a graph B is a graph showing actual output data according to an input voltage.

1, even if the same input voltage is applied to the input terminal of the analog-to-digital converter, a deviation occurs in the output data of the analog-to-digital converter. That is, the output data of the ideal analog-to-digital converter without the gain error and the offset error is determined by the multiplication operation (X) of the input voltage x and the ideal gain error (a) However, since the analog-to-digital converter in general has a gain error and an offset error, the output data of the actual analog-to-digital converter is obtained by multiplying the input voltage (x) x x a ') and an actual offset error (that is, an output according to an input voltage of 0) (b).

As can be seen from Fig. 2, such an output deviation between the analog-digital converters is also generated between the data driving ICs (D-IC # 1 to D-IC # 8).

Therefore, the above-mentioned prior art documents have a problem in that it is impossible to more accurately compensate for a change in the characteristics of the driving transistor since the data is corrected based on the distorted sensing data due to the deviation of the sensing data of the analog-digital converter.

As a result, there is a need for a method of minimizing an output deviation between the analog-digital converters that senses a change in the characteristics of the driving transistor.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an organic light emitting diode (OLED) display device and a driving method thereof that can minimize an output deviation between analogue-digital converters.

According to an aspect of the present invention, there is provided an organic light emitting display including: a display panel including gate lines, a plurality of pixels formed at intersections of data lines and sensing lines; A gate driver for supplying a gate signal to the gate lines; A data driver for supplying data voltages to the data lines, and a sensing unit having a plurality of analog-to-digital converters for sensing the characteristic change information of the driving transistors included in the plurality of pixels through the sensing lines to generate sensing data, A plurality of data driving integrated circuits comprising: A memory in which a gain error and an offset error of each of the plurality of analog-to-digital converters are stored; And a timing controller for correcting the sensing data based on the gain error and the offset error, modulating the input data based on the corrected sensing data, and supplying the modulated input data to the plurality of data driving integrated circuits .

Wherein the timing control unit subtracts the offset error from the sensing data and divides the result of the subtraction by the gain error to calculate the corrected sensing data.

Wherein the timing control unit divides the sensing unit into a precharging period and a sensing period during an ADC deviation correction mode and the sensing unit supplies a test voltage to each of the sensing lines during the precharging interval, And supplies measurement data output from the digital converter to the timing control unit.

Wherein the timing control unit gradually increases a voltage level of the test voltage, acquires measurement data according to a voltage level output from the analog-to-digital converter, and supplies the measurement data to an external error correcting apparatus, The gain error and the offset error are stored in the memory.

Wherein the sensing unit senses the characteristic change information of the driving transistor included in the pixels of the selected horizontal line through the sensing lines to supply the sensing data to the timing control unit and the timing control unit adjusts the gain error and the offset Corrects the sensing data based on the error, and modulates the input data to be supplied to the pixels of the horizontal line based on the corrected sensing data.

According to an aspect of the present invention, there is provided a method of driving an organic light emitting display including a display panel having gate lines, a plurality of pixels formed at intersections of data lines and sensing lines, And a plurality of data driving ICs each including a sensing unit having a plurality of analog-to-digital converters selectively connected to the sensing lines, the driving method comprising: (A) calculating a gain error and an offset error of each of the plurality of analog-to-digital converters based on output data of each of the plurality of analog-to-digital converters according to the output data; A step (B) of sensing the characteristic change information of the driving transistor included in each of the plurality of pixels through each of the plurality of analog-to-digital converters to generate sensing data of each pixel; (C) correcting the sensing data based on the gain error and the offset error; And a step (D) of modulating input data inputted based on the corrected sensing data and supplying the modulated input data to the plurality of data driving integrated circuits.

Wherein the step (C) calculates the corrected sensing data by subtracting the offset error from the sensing data and dividing the result of the subtraction by the gain error.

Wherein the step (A) comprises: (A1) supplying a gate signal of a gate off voltage level to the gate lines; (A2) supplying a test voltage to the sensing lines and sensing a voltage of each of the sensing lines supplied with the test voltage using each of the plurality of analog-to-digital converters; (A3) acquiring measurement data corresponding to the data voltage output from each of the plurality of analog-to-digital converters; And calculating (A4) a gain error and an offset error of each of the plurality of analog-to-digital converters using a least square method based on the measurement data and storing the calculated gain error and offset error in a memory.

Wherein the step (A2) comprises the step of increasing the voltage level of the test voltage step by step, sensing the voltage of each of the sensing lines supplied with the stepwise increasing test voltage by using each of the plurality of analog-digital converters, In step A4, the gain error and the offset error are calculated for each constant interval of the test voltage.

Wherein the step (A4) calculates the same gain error and offset error for each of the plurality of analog-to-digital converters, and the step (C) calculates the same gain error and offset error for each of the plurality of analog- .

According to an aspect of the present invention, there is provided an organic light emitting display device and a method of driving the same, wherein distortion of sensing data according to an output deviation between analog-digital converters sensing a change in characteristics of a driving transistor can be minimized, It is possible to more accurately compensate the change in the characteristics of the driving transistor included in the driving transistor.

1 is a waveform diagram showing output data according to an input voltage of an analog-to-digital converter.
2 is a waveform diagram for explaining an output deviation between a plurality of data driving integrated circuits in a general organic light emitting display device.
3 is a view for explaining an organic light emitting display according to an embodiment of the present invention.
4 is a diagram showing the structure of one pixel shown in Fig.
5 is a diagram for explaining the data driving integrated circuit shown in FIG.
6 is a diagram for explaining an error correcting apparatus of an analog-to-digital converter according to an embodiment of the present invention.
FIG. 7 is a diagram for explaining a configuration of the error correction apparatus shown in FIG. 8. FIG.
8 is a diagram for explaining a process of calculating a circuit operation, a gain error, and an offset error in the ADC deviation correction mode using the error correction apparatus according to the present invention.
9 is a waveform diagram showing measurement data according to a test voltage of the analog-digital converter shown in FIG.
10 and 11 are diagrams for explaining calculation and correction of a gain error and an offset error for each section of the test voltage.
FIG. 12 is a diagram showing comparison of sensing data before and after application of a gain error and an offset error according to the present invention, for each data driving IC.
13 is a diagram for explaining a deviation between sensing data of a plurality of data driving integrated circuits.

The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms.

It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one.

Hereinafter, preferred embodiments of the organic light emitting diode display and the driving method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a view for explaining an organic light emitting display according to an embodiment of the present invention, FIG. 4 is a diagram illustrating the structure of one pixel shown in FIG. 3, and FIG. 5 is a cross- Fig.

3 to 5, an OLED display according to an exemplary embodiment of the present invention includes a display panel 100, a gate driver 200, a plurality of data driver ICs 300, a memory 400, And a control unit 500.

The display panel 100 includes a plurality of pixels P. The plurality of pixels P are defined by a plurality of gate line groups GL, a plurality of data lines DLi, and a plurality of sensing lines SLi aligned with the plurality of data lines DLi Is formed in the pixel region.

Each of the plurality of gate line groups GLi is formed along a first direction of the display panel 100, for example, in a horizontal direction. At this time, each of the plurality of gate line groups GLi includes first and second gate lines GLa and GLb adjacent to each other. The first and second gate signals GSa and GSb are separately supplied from the gate driver 200 to the first and second gate lines GLa and GLb of each gate line group GLi.

Each of the plurality of data lines DLi is formed to be parallel to a second direction of the display panel 100, for example, a vertical direction so as to intersect each of the plurality of gate line groups GLi. The data voltage Vdata is separately supplied from the data driving IC 300 to each data line DLi. At this time, a data voltage Vdata compensated for the threshold voltage and the mobility of the driving transistor included in the pixel P is supplied to each of the plurality of data lines DLi.

Each of the plurality of sensing lines SLi is formed in parallel with each of the plurality of data lines DLi. The reference voltage Vref or the precharging voltage Vpre is selectively supplied from the data driving IC 300 to each sensing line SLi. That is, the reference voltage Vref is selectively supplied to each sensing line SLi in the display mode, and the precharging voltage Vpre is selectively supplied to the sensing line SLi in the sensing mode. On the other hand, a test voltage is supplied to each of the sensing lines SLi in the analog-to-digital converter deviation correction mode (hereinafter referred to as "ADC deviation correction mode").

The display panel 100 is formed with a plurality of driving voltage lines PLi arranged in parallel to a plurality of data lines DLi. A driving voltage VDD is supplied to each of the plurality of driving voltage lines PLi from a voltage supply unit (not shown).

Each of the plurality of pixels P includes an organic light emitting diode (OLED) and a pixel circuit (PC).

The organic light emitting diode OLED emits light in proportion to the data current Ioled flowing from the driving voltage line PLi to the cathode voltage VSS line according to driving of the pixel circuit PC. To this end, the organic light emitting device OLED includes an anode electrode (not shown), an organic layer (not shown) formed on the anode electrode, and a cathode electrode CE formed on the organic layer. At this time, the organic layer may have a structure of a hole transporting layer / an organic light emitting layer / an electron transporting layer or a structure of a hole injecting layer / a hole transporting layer / an organic light emitting layer / an electron transporting layer / an electron injecting layer. Further, the organic layer may further include a functional layer for improving the luminous efficiency and / or lifetime of the organic light emitting layer. The cathode electrode CE may be formed individually in each of the plurality of pixels P or may be formed so as to be connected to a plurality of pixels P in common.

The pixel circuit PC may include a first switching transistor Tsw1, a second switching transistor Tsw2, a driving transistor Tdr, and a capacitor Cst. Here, the transistors Tsw1, Tsw2, and Tdr may be an a-Si TFT, a poly-Si TFT, an oxide TFT, an organic TFT, or the like as an N-type thin film transistor (TFT).

The first switching transistor Tsw1 includes a gate electrode connected to the first gate line GLa of the gate line group GLi, a first electrode connected to the adjacent data line DLi, and a gate electrode connected to the gate of the driving transistor Tdr And a second electrode connected to a first node n1 which is an electrode. The first switching transistor Tsw1 may receive the data voltage Vdata supplied to the data line DLi according to the first gate signal GSa of the gate-on voltage level supplied to the first gate line GLa To the gate electrode of the first node n1, that is, the driving transistor Tdr.

The second switching transistor Tsw2 includes a gate electrode connected to the second gate line GLb of the gate line group GLi, a first electrode connected to the adjacent sensing line SLi, and a source of the driving transistor Tdr And a second electrode connected to a second node n2 which is an electrode. The second switching transistor Tsw2 is connected to the reference voltage Vref supplied to the sensing line SLi according to the second gate signal GSb of the gate-on voltage level supplied to the second gate line GLb The precharging voltage Vpre) to the second node n2, that is, the source electrode of the driving transistor Tdr.

The capacitor Cst includes first and second electrodes connected between the gate electrode and the source electrode of the driving transistor Tdr, that is, the first and second nodes n1 and n2. The capacitor Cst charges the difference voltage between the voltages supplied to the first and second nodes n1 and n2, and then switches the driving transistor Tdr according to the charged voltage.

The driving transistor Tdr includes a gate electrode commonly connected to the second electrode of the first switching transistor Tsw1 and the first electrode of the capacitor Cst, a first electrode of the second switching transistor Tsw2, and a capacitor Cst A source electrode commonly connected to the organic light emitting device OLED, and a drain electrode connected to the driving voltage line PLi. This driving transistor Tdr controls the amount of current flowing from the driving voltage line PLi to the organic light emitting element OLED by being turned on by the voltage of the capacitor Cst.

The pixel circuit PC operates in a data charging period and a light emitting period in accordance with a gate signal supplied from the gate driver 200. That is, the pixel circuit PC charges the capacitor Cst with the difference voltage Vdata-Vref between the data voltage Vdata and the reference voltage Vref during the data charging period, The driving transistor Tdr is turned on in accordance with the voltage stored in the organic light emitting element Cst to turn on the data current Ioled determined by the difference voltage Vdata-Vref between the data voltage Vdata and the reference voltage Vref OLED).

In the above-described embodiment, the pixel circuit PC is composed of three transistors and one capacitor. However, the number of transistors and capacitors constituting the pixel circuit PC may be variously modified.

The gate driver 200 is formed on one side and / or both non-display areas of the display panel 100 and is connected to the gate lines GL. At this time, the gate driver 200 may be formed directly on the substrate of the display panel 100 together with the transistor forming process of each pixel P, and may be connected to one or both sides of each of the gate lines GL.

The gate driver 200 generates the first and second gate signals GSa and GSb of the gate-on voltage level for each horizontal period under the control of the timing controller 500 and sequentially outputs the first and second gate signals GSa and GSb to the gate line group GLi Supply. At this time, each of the first and second gate signals GSa and GSb has a gate-on voltage level during a data charging period of each pixel P, and has a gate-off voltage level during a light-emitting period of each pixel P.

In addition, the gate driver 200 controls each pixel P of the selected horizontal line during the sensing period, which is set during a certain horizontal period of one frame period, under the control of the timing controller 500, Generates first and second gate signals (GSa, GSb) for driving in the sensing period, and supplies the generated first and second gate signals (GSa, GSb) to the corresponding gate line group (GLi). At this time, the first gate signal GSa has a gate-on voltage level only during the initialization period and the voltage charging period, and the second gate signal GSb has a gate-on voltage level during a sensing period.

The gate driver 200 may be formed in the form of an integrated circuit (IC) and mounted on one side and / or both non-display areas of the display panel 110 or may be formed in the form of an integrated circuit (IC) (Not shown). At this time, the gate flexible circuit film is attached to the display panel 300 by a film attaching process.

Each of the plurality of data driving ICs 300 is connected to each of the data lines DL and the sensing lines SL. Each of the plurality of data driving ICs 300 supplies a data voltage and a reference voltage to each pixel P under the control of the timing controller 500 and supplies the data voltage and the reference voltage to the selected horizontal line Senses threshold voltage and mobility characteristic changes of the driving transistor Tdr included in each pixel to generate threshold voltage sensing data and mobility sensing data of the driving transistor Tdr and provides them to the timing controller 500. [ As described above, each of the plurality of data driving ICs 300 is mounted on the data flexible circuit film 310. One side of the plurality of data flexible circuit films 310 is attached to a data pad portion formed on a display panel 300 by a film adhering process and the other side of the plurality of data flexible circuit films 310 is adhered to a data pad portion And is attached to the printed circuit board 600.

Each of the plurality of data driving ICs 300 includes a data driver 310 and a sensing unit 320.

The data driver 310 receives the pixel data DATA of each pixel P from the timing controller 500 for each horizontal period and converts the received pixel data into a data voltage Vdata and supplies the data voltage to the data line DLi. The data driver 310 converts the sensing data DATA supplied from the timing controller 500 into a sensing data voltage Vdata during the sensing period and supplies the sensing data voltage to the data line DLi. As a result, the data driver 310 supplies the data voltage Vdata to the data line DLi during the data charging period of each horizontal period, and during the initialization period or the initialization period of the sensing period, And supplies the data voltage Vdata to the data line DLi. The data driver 310 includes a shift register for generating a sampling signal based on a data start signal and a data shift signal supplied from the timing controller 500, a latch for latching the pixel data DATA according to a sampling signal, A digital-to-analog converter (ADC) for selecting and outputting a gradation voltage corresponding to data latched in a plurality of gradation voltages as a data voltage (Vdata), a gradation voltage generation unit And an output unit for outputting the data voltage Vdata to the data line DLi according to a data output signal.

Although the data driver 310 is shown as being connected to one data line DLi in FIG. 5, the data driver 310 is connected to a data line corresponding to the set number of channels.

The sensing unit 320 is connected to each sensing line SLi of each pixel P and includes a switching unit 322 and an analog-to-digital converter 324.

The switching unit 322 includes a reference voltage supply line RVL to which the reference voltage Vref is supplied, a precharging voltage supply line PVL to which the precharging voltage Vpre is supplied, and an analog-to-digital converter 324 And is selectively connected to the sensing line SLi under the control of the timing controller 128. [ That is, the switching unit 322 connects the reference voltage supply line RVL to the sensing line SLi during the respective horizontal periods. Meanwhile, the switching unit 322 connects the precharging voltage supply line PVL to the sensing line SLi during the initialization period of the sensing period, and the sensing line SLi during the data charging period of the sensing period, And connects the sensing line SLi to the analog-to-digital converter 324 during a voltage sensing period of the sensing period.

The reference voltage Vref may be any one of the gradation voltages output from the gradation voltage generator of the data driver 310. In this case, the reference voltage supply line RVL is connected to the gradation voltage generator. Here, the reference voltage Vref may have a voltage level of 0 (Zero) or a voltage level lower than the conduction voltage of the organic light emitting diode OLED.

In addition, the precharging voltage Vpre may be any one of the gradation voltages output from the gradation voltage generator. In this case, the precharging voltage supply line PVL is connected to the gradation voltage generator.

When the analog-to-digital converter 324 is connected to the sensing line SLi by switching of the switching unit 322, the analog-to-digital converter 324 senses a voltage charged in the sensing line SLi, digitally converts the sensed voltage, Generates data (Sdata), and supplies the generated sensing data (Sdata) to the timing control unit (500). The sensing data Sdata is supplied to a timing control unit 500 mounted on the control board 700 through a sensing data transmission line 610 formed on a printed circuit board 600 and a signal transmission member 800.

The memory 400 stores a gain error and an offset error for each analog-to-digital converter 324 included in the sensing unit 324 mounted on the control board 700. The gain error and the offset error of each analog-to-digital converter 324 are measured by the analog-to-digital converter 324 by the ADC deviation correction mode performed in the last inspection process before shipment of the organic light- And is stored in the memory 400. In the present embodiment, as shown in FIG. At this time, the correction calculation process individually calculates the gain error and the offset error of each of the analog-to-digital converters 324 incorporated in each of the plurality of data driving ICs 310, It is possible to calculate the gain error and offset error of each of the analog-to-digital converters 324, or to calculate the same gain error and offset error in all of the analog-to-digital converters 324. [ The ADC deviation correction mode and the correction calculation process will be described later.

Meanwhile, the memory 400 may be embedded in the timing controller 500.

The timing controller 500 is mounted on the control board 700 and supplies a timing synchronization signal and image data input from an external system body (not shown) or a graphic card (not shown) via the user connector 710 Receive.

First, the timing controller 500 drives each of the gate driver 200 and the plurality of data driver ICs 300 based on a timing synchronization signal such as a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a clock signal, Timing.

The timing controller 500 controls the driving timing of the gate driver 200 so that each pixel P connected to each gate line group GLi is driven in a data charging period and a light emitting period in units of one horizontal period, The driving timing of the plurality of data driving integrated circuits 300 is controlled so that the data voltage Vdata is supplied to the data line DLi and the reference voltage Vref is supplied to the sensing line SLi during the data charging period.

The timing controller 500 controls the driving of the gate driver 200 so that each pixel P of the selected horizontal line is driven during the initialization period, the voltage charging period, and the voltage sensing period during the sensing period, And controls the driving of each of the plurality of data driving integrated circuits 300 so that the data voltage Vdata for sensing is supplied to the data line DLi during the period and the voltage charging period. The method of sensing the threshold voltage and the mobility characteristic change of the driving transistor Tdr included in each pixel P of the selected horizontal line during the sensing period is described in detail in the prior patent documents 1 to 3 A description thereof will be omitted.

The timing controller 500 controls the driving transistor Tdr of each pixel P supplied from the sensing unit 324 of the plurality of data driving integrated circuits 300 based on the gain error and the offset error stored in the memory 400. [ (Sdata) corresponding to the threshold voltage and the mobility characteristic change of the pixel P, and outputs the corrected sensing data of the calculated pixel P to a separate memory unit (not shown) . At this time, the timing controller 500 may correct the sensing data (Sdata) according to the gain error and the offset error as shown in the following Equation (1).

In Equation 1, y denotes corrected sensing data, x denotes sensing data (Sdata), a denotes a gain error of the analog-to-digital converter, and b denotes an offset error of the analog- do. The corrected sensed data (y) has a compensated value of the error of the measured data with respect to the input voltage of the analog-to-digital converter 324.

When the input data is inputted from the outside, the timing controller 500 modulates the input data of the pixel P according to the corrected sensing data of the corresponding pixel stored in the memory unit, and supplies the modulated data to the plurality of data driving integrated circuits 300 . Accordingly, the timing controller 500 generates the modulation data by reflecting the change in the threshold voltage and the mobility characteristic of the driving transistor Tdr on the input data based on the corrected sensing data.

The timing controller 500 operates the gate driver 200 and the plurality of data driver ICs 300 in the ADC deviation correction mode according to a measurement synchronization signal supplied from the outside.

Specifically, in the ADC deviation correction mode, the timing controller 500 controls the driving of the gate driver 200 so that the gate signal GS of the gate off voltage level is supplied to all the gate line groups GLi. Then, the timing controller 500 drives the sensing unit 320, which is incorporated in each of the plurality of data driving ICs 300, as a precharging period and a sensing period. Then, the timing controller 500 outputs the measurement data output from the analog-to-digital converter 324 of the sensing unit 320 to the external error correction device by the sensing period, The gain and offset errors of each of the analog-to-digital converters 324, the gain error and offset error of the data drive integrated circuit 300, the same gain and offset error of all the analog-to-digital converters 324, .

In the ADC deviation correction mode, the sensing unit 320 supplies the test voltage Vtest to the sensing lines SLi during the precharging interval, and outputs the test voltage Vtest to the analog- And supplies the measurement data to the timing control unit 500. [ At this time, the timing controller 500 may increase the test voltage (Vtest) supplied to the sensing lines (DLi) during the precharging interval by a plurality of intervals.

The OLED display according to the exemplary embodiment of the present invention may be applied to the pixels of the selected horizontal line based on the gain error and the offset error of the analog-to-digital converter 324 of the sensing unit 320 stored in the memory 400 By correcting the sensing data corresponding to the threshold voltage and mobility characteristic of the included driving transistor Tdr and modulating the input data according to the corrected sensing data, distortion of the sensing data due to the output deviation between the analog- Can be minimized, and the characteristic change of the driving transistor included in each pixel can be more accurately compensated.

FIG. 6 is a view for explaining an error correcting apparatus of an analog-digital converter according to an embodiment of the present invention, and FIG. 7 is a diagram for explaining a configuration of the error correcting apparatus shown in FIG.

6 and 7, the error correcting apparatus 900 according to the present invention includes the timing controller 500 and the timing controller 500 through the user connector 710 mounted on the control board 800 of the organic light emitting display And performs the above-described ADC deviation correction mode while communicating. The error correction apparatus 900 according to the present invention includes a measurement synchronization signal generator 910, a test voltage setting unit 920, and an error calculator 930.

The measurement synchronization signal generator 910 generates a measurement synchronization signal Msync for generating an ADC deviation correction mode and supplies the measurement synchronization signal Msync to the timing controller 500. [ The timing control unit 500 sets the driving mode of the display panel 100 to the ADC deviation correction mode in accordance with the measurement synchronization signal Msync and controls the gate driving unit 200 and the plurality of data driving integrated circuits 300 ) Operate in ADC deviation correction mode.

The test voltage setting unit 920 generates a voltage setting signal TVS for setting the voltage value of the test voltage Vtest to be supplied to the sensing line SLi based on the measurement synchronization signal Msync, (500). Accordingly, the timing controller 500 controls the voltage supplier or controls the output voltage of the reference gamma voltage generator to supply the test voltage Vtest corresponding to the voltage setting signal TVS to the sensing line SLi .

The error calculator 930 analyzes the measurement data Msensing supplied from the timing controller 500 in units of the data integration circuit 300 to calculate a gain error a and an offset error b ). At this time, the error calculator 930 may calculate the gain error a and the offset error b using the least squares method based on the measurement data Msensing.

The error calculator 930 supplies the calculated gain error a and the offset error b to the timing controller 500. [ Accordingly, the timing controller 500 stores the gain error (a) and the offset error (b) supplied from the error calculator 930 in the memory 400.

8 is a diagram for explaining a process of calculating a circuit operation, a gain error, and an offset error in the ADC deviation correction mode using the error correction apparatus according to the present invention.

First, the timing controller 500 controls driving of the gate driver 200 according to a precharging interval of the measurement synchronization signal Msync to apply a gate-off voltage (Vs) to all the gate line groups GLi of the display panel 100 Level gate signals GSa and GSb. At the same time, the timing controller 500 causes the test voltage Vtest corresponding to the voltage setting signal TVS to be supplied to the precharging voltage supply line PVL, and at the same time, The sensing unit SLi is charged with the test voltage Vtest by controlling the switching unit 322 of the sensing unit 320 and connecting the sensing line SLi to the precharging voltage supply line PVL.

The timing controller 500 controls the switching unit 322 of the sensing unit 320 to connect the sensing line SLi to the analog-to-digital converter 324 according to the sensing period of the measurement synchronization signal Msync . Each of the analog-to-digital converters 324 connected to each sensing line SLi converts the voltage of the corresponding sensing line SLi to a digital value to generate measurement data Msensing and outputs the generated measurement data Msensing to the timing And supplies the measurement data Msensing to the error calculator 930. The error calculator 930 calculates the error rate of the measured data Msensing.

Then, the timing controller 500 repeatedly performs the above-described steps for each section according to the voltage level while stepping up the voltage level of the test voltage Vtest according to the voltage setting signal TVS, As shown in the figure, the measurement data Msensing according to the voltage level of the test voltage Vtest is supplied to the error calculator 930.

Next, the error calculator 930 calculates X and Y according to the scattering of the measurement data Msensing using a least squares method based on the measurement data Msensing according to the voltage level of the test voltage Vtest The gain error (a) and the offset error (b) are calculated on the sample regression line (y = ax + b).

Specifically, if the sample regression line according to the measurement data Msensing according to the voltage level of the test voltage Vtest is "y = ax + b ", the sum of the squares of the errors is expressed by Equation 2 below.

)의 a, b에 대한 편미분값이 0인 a, b를 구함으로써 상기 게인 오차(a) 및 오프셋 오차(b)를 산출한다.The error calculator 930 calculates the error of the function (2) in Equation (2)

(A) and the offset error (b) are calculated by obtaining a and b with partial differential values of a and b of 0, respectively.

At this time, the error calculator 930 averages measurement data Msensing measured repeatedly according to the voltage level of the test voltage (Vtest) and substitutes the measured data (Msensing) for the dependent variable yi of the function of Equation (2) The error value of the measurement data Msensing generated intermittently according to the voltage level of the voltage Vtest is corrected. That is, the error calculator 930 compares the added measurement data Msensing with the previous measurement data Msensing, adds the average measurement data Msensing to the measured data Msensing, , And adds the measurement data (Msensing) to be added and the previous measurement data (Msensing) when it is in the normal range.

Due to the linearity problem due to the gain error and the offset error of the analog-to-digital converter 342 itself, the correction values of the single gain error a and the offset error b may be set to values of the measurement data Msensing to be ideally corrected Distortion can be given. In order to prevent such distortion, the error calculator 930 divides the measurement data (Msensing) according to the voltage level of the test voltage (Vtest) And calculates and corrects the gain error (a) and the offset error (b) for each section. When the gain error (a) and the offset error (b) are calculated and corrected according to the intervals, the corrected measurement data Msensing is compared with the D graph As shown in the graph, the error is reduced and approximated to the ideal A graph.

The error calculator 930 corrects the gain error a and the offset error b between the data driving ICs 300 and outputs the same gain error a and offset error b to all the analog- In this case, the timing controller 500 applies the same gain error a and offset error (Sdata) to the sensing data Sdata supplied from each of the plurality of analog-to-digital converters 324 during the sensing period of the horizontal line b to generate corrected sensing data.

The error calculator 930 calculates the gain error a and the offset error b for each analog-to-digital converter 342 calculated through the regression analysis using the least squares method, . Accordingly, the timing controller 500 stores the gain error a and the offset error b provided by the error calculator 930 in the memory 400, and ends the ADC deviation correction mode described above . Here, the gain error (a) and offset error (b) for each analog-to-digital converter 342 can be generated in a look-up table and stored in the memory 400.

12A and 12B are graphs comparing sensing data before and after application of a gain error and an offset error according to the present invention for each data driving integrated circuit. FIG. 12A is a graph showing the corrected data obtained by applying a gain error and an offset error to the sensing data And FIG. 12 (b) shows sensing data to which the gain error and the offset error are not applied to the sensing data.

As can be seen from FIG. 12 (a), in the case of the sensed data corrected by applying the gain error and the offset error, it can be seen that the deviation of the interval of the data driving integrated circuit is reduced.

13 is a diagram for explaining a deviation between sensing data of a plurality of data driving integrated circuits.

13, in the case of the sensing data (Sdata) output from each of the plurality of data driving ICs, due to the gain error and the offset error of the analog-to-digital converter 324, the data driving IC In the case of the sensing data Sdata 'corrected by the gain error a and the offset error b calculated by the above-described ADC deviation correction mode, the data driving IC D -IC # 1 to # 8).

In the organic light emitting diode display according to the embodiment of the present invention, the structure of each pixel P formed on the display panel 100 may have the pixel structure disclosed in the prior art documents 1 to 3. In this case, as described above, the organic light emitting display device according to the embodiment of the present invention corrects the sensing data on the characteristic change of the driving transistor included in each pixel sensed by the sensing method disclosed in the prior arts 1 to 3 Thereby solving the problem caused by the output deviation of the analog-to-digital converter.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

100: display panel 200: gate driver
300: Data driving integrated circuit 310: Data driving part
320: sensing part 322: switching part
324: Analog-to-digital converter 400: Memory
500: timing control unit 600: printed circuit board
700: Control board 900: Error correction device
910: Measurement synchronization signal generation unit 920: Test voltage setting unit
930: error calculating section

Claims (10)

A display panel including a plurality of pixels formed at intersections of the gate lines, the data lines, and the sensing lines;
A gate driver for supplying a gate signal to the gate lines;
A data driver for supplying data voltages to the data lines, and a sensing unit having a plurality of analog-to-digital converters for sensing the characteristic change information of the driving transistors included in the plurality of pixels through the sensing lines to generate sensing data, A plurality of data driving integrated circuits comprising:
A memory in which a gain error and an offset error of each of the plurality of analog-to-digital converters are stored; And
And a timing controller for correcting the sensing data based on the gain error and the offset error, modulating the input data based on the corrected sensing data, and supplying the modulated input data to the plurality of data driving integrated circuits To the organic light emitting display device. The method according to claim 1,
Wherein the timing control unit subtracts the offset error from the sensing data and divides the result of the subtraction operation by the gain error to calculate the corrected sensing data. The method according to claim 1,
The timing control unit divides the sensing unit into a precharging period and a sensing period during the ADC deviation correction mode,
Wherein the sensing unit supplies a test voltage to each of the sensing lines during the precharging interval and supplies measurement data output from the analog-digital converter to the timing control unit during the sensing period. The method of claim 3,
Wherein the timing control unit gradually increases a voltage level of the test voltage, acquires measurement data according to a voltage level output from the analog-to-digital converter, and supplies the measurement data to an external error correcting apparatus, And stores the gain error and the offset error in the memory. The method according to claim 1,
Wherein the sensing unit senses the characteristic change information of the driving transistor included in the pixels of the selected horizontal line through the sensing lines and supplies the sensing data to the timing control unit,
Wherein the timing control unit corrects the sensing data based on the gain error and the offset error and modulates the input data to be supplied to the pixels of the horizontal line based on the corrected sensing data. . A display panel having a plurality of pixels formed at intersections of the gate lines, the data lines, and the sensing lines; And a plurality of data driving ICs including a sensing unit having a plurality of analog-to-digital converters selectively connected to the sensing lines, the driving method comprising:
(A) calculating a gain error and an offset error of each of the plurality of analog-to-digital converters based on output data of each of the plurality of analog-to-digital converters according to a test voltage supplied to each of the sensing lines;
A step (B) of sensing the characteristic change information of the driving transistor included in each of the plurality of pixels through each of the plurality of analog-to-digital converters to generate sensing data of each pixel;
(C) correcting the sensing data based on the gain error and the offset error; And
(D) modulating the input data based on the corrected sensing data and supplying the modulated input data to the plurality of data driving integrated circuits. The method according to claim 6,
Wherein the step (C) calculates the corrected sensing data by subtracting the offset error from the sensing data and dividing the result of the subtraction by the gain error. Way. The method according to claim 6,
The step (A)
Supplying a gate signal of a gate off voltage level to the gate lines;
(A2) supplying a test voltage to the sensing lines and sensing a voltage of each of the sensing lines supplied with the test voltage using each of the plurality of analog-to-digital converters;
(A3) acquiring measurement data corresponding to the data voltage output from each of the plurality of analog-to-digital converters; And
(A4) of calculating a gain error and an offset error of each of the plurality of analog-to-digital converters using the least squares method based on the measurement data and storing the calculated gain error and offset error in a memory . 9. The method of claim 8,
The step (A2) includes the step of increasing the voltage level of the test voltage, sensing the voltage of each of the sensing lines supplied with the test voltage gradually increased by using each of the plurality of analog-digital converters,
Wherein the step (A4) calculates the gain error and the offset error for every predetermined period of the test voltage. 9. The method of claim 8,
The step (A4) calculates the same gain error and offset error for each of the plurality of analog-to-digital converters,
Wherein the step (C) applies the same gain error and offset error to the sensing data of each of the plurality of analog-to-digital converters.

Images