KR20180013356A - Organic light emitting display device - Google Patents

Abstract

The present invention relates to an organic light emitting display device capable of compensating for a difference between sensing data of analogue-digital converters according to a characteristic change of an analogue-digital converter. According to an embodiment of the present invention, the organic light emitting display device comprises: a display panel including pixels connected to data lines and reference voltage lines; source drive ICs each including a data voltage supply unit which converts digital compensation data into data voltages to supply the same to the data lines and an analogue-digital converter which senses predetermined voltages of the pixels through the reference voltage lines to output the same to sensing data that is digital data; and a timing controller for converting digital video data input from the outside into digital compensation data based on the sensing data to supply the same to the data voltage supply unit. Analogue-digital converters of at least two source drive ICs among the source drive ICs receive the same sensing voltage from the same line.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an organic light-

The present invention relates to an organic light emitting display.

As the information society develops, the demand for display devices for displaying images is increasing in various forms. In recent years, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used. Of these, the organic light emitting display device can be driven at a low voltage, is thin, has excellent viewing angle, and has a high response speed.

The organic light emitting display includes a display panel having data lines, scan lines, a plurality of sub-pixels formed at intersections of data lines and scan lines, a scan driver for supplying scan signals to the scan lines, And a data driver for supplying data voltages to the data driver. Each of the sub-pixels includes an organic light emitting diode, a driving transistor for controlling the amount of current supplied to the organic light emitting diode according to the voltage of the gate electrode, And supplying the data voltage to the gate electrode of the driving transistor.

The threshold voltage and the electron mobility of the driving transistor may vary from pixel to pixel due to a process variation during manufacturing of the organic light emitting display device or deterioration of the driving transistor due to long-term driving. That is, when the same data voltage is applied to the pixels, the current supplied to the organic light emitting diode must be the same. However, even if the same data voltage is applied to the pixels due to the difference between the threshold voltage and the electron mobility of the driving transistor between the pixels, the current supplied to the organic light emitting diode may vary from pixel to pixel. Accordingly, even if the same data voltage is applied to the pixels, the luminance at which the organic light emitting diode emits light may vary from pixel to pixel. To solve this problem, a compensation method for compensating the threshold voltage and the electron mobility of the driving transistor has been proposed.

The threshold voltage and electron mobility of the driving transistor can be compensated by the following external compensation method. The external compensation method supplies a predetermined data voltage to the pixel, senses the source voltage of the driving transistor or the driving current of the driving transistor through a predetermined sensing line according to a preset data voltage, and outputs an analog digital converter And converts the sensed voltage into digital data sensing data to compensate digital video data to be supplied to the pixel P in accordance with the sensing data.

The analog-to-digital converter can be embedded in each of the source drive ICs (SIC1 to SIC8) for supplying the data voltages to the data lines as shown in Fig. The blocks BL1 to BL8 of the display panel DIS can be divided according to the source drive IC. That is, since the analog digital converter of the i-th (i is an integer of 2 or more) source drive IC is connected to the sensing lines of the i-th block of the display panel DIS, a predetermined voltage is sensed through the sensing lines of the i-th block .

On the other hand, the characteristics of the analog-to-digital converter can be affected by factors such as temperature, humidity, and pressure after shipment. In this case, even if each of the analog-to-digital converters senses the same voltage through the sensing line, a difference may occur in the sensing data between the analog-digital converters according to the characteristic change of the analog-digital converter. Accordingly, even if the threshold voltage and the electron mobility of the driving transistor are compensated by the external compensation method, due to the difference in the sensing data depending on the characteristics of the analog-to-digital converter, A block dim where a difference in brightness occurs in the blocks BL1 to BL8 of the panel DIS can be visually recognized by the user.

The present invention provides an organic light emitting display capable of compensating for a difference between sensing data of analogue digital converters according to characteristics of an analogue digital converter.

The organic light emitting display according to an embodiment of the present invention includes a display panel including pixels connected to data lines and reference voltage lines, a data voltage supply unit for converting the digital compensation data into data voltages, Source drive ICs each including an analog digital converter for sensing predetermined voltages of pixels through reference voltage lines and outputting them as digital data sensing data, digital video data inputted from the outside, And supplies the data voltage to the data voltage supply unit. Analog digital converters of at least two of the source drive ICs receive the same sensing voltage from the same line.

The embodiment of the present invention receives the same sensing voltage from the same line by analogue digital converters of at least two of the source drive ICs. As a result, the embodiment of the present invention can compensate for the occurrence of a difference between the sensing data of the analog-digital converters according to the characteristic change of the analog-digital converter. Therefore, the embodiment of the present invention can prevent the block dim from being viewed to the user.

1 is an exemplary view showing blocks of a display panel divided according to a source drive IC.
2 is an exemplary view showing a block dim of the display panel of FIG.
3 is a block diagram illustrating an OLED display according to an exemplary embodiment of the present invention.
FIG. 4 is an exemplary view showing a lower substrate, source drive ICs, a timing control section, a data compensation section, flexible films, a source circuit board, a flexible cable, and a control circuit board of the display panel of FIG.
5 is a detailed block diagram of the source drive IC of FIG.
6 is a circuit diagram showing the pixel of FIG. 5 in detail.
7 is a waveform diagram showing a scan signal and a sensing signal supplied to the pixel in the display mode, a switch control signal supplied to the switch, and a gate voltage and a source voltage of the driving transistor.
8 is a waveform diagram showing a scan signal and a sensing signal supplied to a pixel in the first sensing mode, a switch control signal supplied to the switch, and a gate voltage and a source voltage of the driving transistor.
9 is a waveform diagram showing a scan signal and a sensing signal supplied to the pixel in the second sensing mode, a switch control signal supplied to the switch, and a gate voltage and a source voltage of the driving transistor.
10 is an exemplary view showing sensing lines connected to adjacent source drive ICs according to an embodiment of the present invention.
11 is an exemplary view showing source drive ICs and a source circuit board according to another embodiment of the present invention.
12 is an exemplary view showing source drive ICs and a source circuit board according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating an OLED display according to an exemplary embodiment of the present invention. FIG. 4 is an exemplary view showing a lower substrate, source drive ICs, a timing control section, a data compensation section, flexible films, a source circuit board, a flexible cable, and a control circuit board of the display panel of FIG. 5 is a detailed block diagram of the source drive IC of FIG.

3 to 5, an organic light emitting display according to an exemplary embodiment of the present invention includes a display panel 10, a data driver 20, a flexible film 22, a scan driver 40, a source circuit board 50, a timing control unit 60, a data compensation unit 70, a reference voltage supply unit 50, a flexible cable 91, and a control circuit board 90.

The display panel 10 includes a display area AA and a non-display area NDA provided around the display area AA. The display area AA is an area where pixels P are formed to display an image. In the display panel 10, data lines (D1 to Dm, m is a positive integer of 2 or more), reference voltage lines (R1 to Rp, p are positive integers of 2 or more), scan lines (S1 to Sn, n Is a positive integer of 2 or more), and the sensing signal lines SE1 to SEn are provided. The data lines D1 to Dm and the reference voltage lines R1 to Rp may intersect the scan lines S1 to Sn and the sensing signal lines SE1 to SEn. The data lines D1 to Dm and the reference voltage lines R1 to Rp may be parallel to each other. The scan lines S1 to Sn and the sensing signal lines SE1 to SEn may be parallel to each other.

Each of the pixels P includes one of the data lines D1 to Dm, one of the reference voltage lines R1 to Rp, one of the scan lines S1 to Sn, and one of the sensing signal lines SE1 to SEn, respectively. Each of the pixels P of the display panel 10 may include an organic light emitting diode (OLED) as shown in FIG. 6 and a plurality of transistors for supplying current to the organic light emitting diode OLED. A detailed description of each of the pixels P in the display area will be described later with reference to FIG.

The data driver 20 may include a plurality of source drive ICs 21 as shown in FIG. Each of the source drive ICs 21 may be mounted on each of the flexible films 22. Each of the flexible films 22 may be a tape carrier package or a chip on film. Each of the flexible films 22 may be bent or bent. Each of the flexible films 22 may be attached to the lower substrate 11 and the source circuit board 50. Each of the flexible films 22 may be attached on the lower substrate 11 by a tape automated bonding (TAB) method using an anisotropic conductive flim, D1 to Dm. The source circuit board 50 may be connected to the control circuit board 90 by a flexible cable 91. The source circuit board 50 may be a printed circuit board.

Each of the source drive ICs 21 may include a data voltage supply unit 110, an analog digital converter (ADC) 140, and a switch SW as shown in FIG. In FIG. 3, for convenience of description, one source drive IC 21 is formed by w (w is a positive integer satisfying 1? W? M) data lines D1 to Dw and z p < = p) positive reference voltage lines R1 to Rz.

The data voltage supply unit 110 is connected to the data lines D1 to Dw to supply data voltages. The data voltage supplier 110 receives compensation data CDATA or sensing data PDATA and a data timing control signal DCS from the timing controller 60.

The data voltage supplier 110 converts the compensation data CDATA into the light emission data voltages according to the data timing control signal DCS in the display mode and supplies the data to the data lines D1 to Dw. The emission data voltage is a voltage for emitting the organic light emitting diode OLED of the pixel P with a predetermined luminance.

The data voltage supplier 110 converts sensing data PDATA to sensing data voltages in accordance with a data timing control signal DCS in a sensing mode and supplies the sensed data voltages to the data lines D1 to Dw. The sensing data voltage is a voltage for sensing the current of the driving transistor of the pixel P. [

The ADC 140 converts the voltage of each of the reference voltage lines R1 to Rz into digital data sensing data SD1, SD2, and SD3. Alternatively, the ADC 140 converts a current flowing in each of the reference voltage lines R1 to Rz into a voltage, and converts the converted voltage into digital data sensing data SD1, SD2, and SD3. The ADC 140 converts the voltage or current of each of the reference voltage lines R1 to Rz into sensing data SD1, SD2 and SD3 in the sensing mode and outputs the sensing data SD1, SD2 and SD3 to the data compensator 70.

The switch SW is connected between the reference voltage lines R1 to Rz and the voltage supply unit 80 to switch the connection between the reference voltage lines R1 to Rz and the voltage supply unit 80. [ The switch SW can be turned on and off by the switch control signal SCS input from the timing controller 60. [ The reference voltage lines R1 to Rz are connected to the voltage supply unit 80 when the switch SW is turned on by the switch control signal SCS so that the reference voltage of the voltage supply unit 80 is applied to the reference voltage lines (R1 to Rz).

The scan driver 40 includes a scan signal output unit 41 and a sensing signal output unit 42. The scan signal output unit 41 is connected to the scan lines S1 to Sn to supply scan signals. The scan signal output unit 41 supplies scan signals to the scan lines S1 to Sn in accordance with a scan timing control signal SCS input from the timing controller 60. [

The sensing signal output unit 42 is connected to the sensing signal lines SE1 to SEn to supply sensing signals. The sensing signal output unit 42 supplies sensing signals to the sensing signal lines SE1 to SEn according to a sensing timing control signal SENCS input from the timing controller 60. [

The scan signal output unit 41 and the sensing signal output unit 42 may include a plurality of transistors and may be formed directly in the non-display area NDA of the display panel 10 in a gate driver in panel (GIP) manner. Alternatively, the scan signal output unit 41 and the sensing signal output unit 42 may be mounted on a flexible film (not shown) formed in the form of a driving chip and connected to the display panel 10.

The timing controller 60 receives compensation data CDATA or sensing data PDATA and timing signals from the data compensator 70. The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

The timing controller 60 generates timing control signals for controlling the operation timings of the data driver 20, the scan signal output unit 41, and the sensing signal output unit 42. The timing control signals include a data timing control signal DCS for controlling the operation timing of the data driver 20, a scan timing control signal SCS for controlling the operation timing of the scan signal output unit 41, And a sensing timing control signal (SENCS) for controlling the operation timing of the unit (42).

The timing controller 60 outputs the compensation data CDATA or the sensing data PDATA and the data timing control signal DCS to the data driver 20. The timing control unit 60 outputs the scan timing control signal SCS to the scan signal output unit 41 and the sensing timing control signal SENCS to the sensing signal output unit 42. [ The timing control unit 60 may output a switch control signal SCS for controlling the switch SW of the data driver 20. [

The timing controller 60 can control the display mode and the sensing mode. The display mode is a mode in which the pixels P emit light by supplying emission data voltages corresponding to the compensation data CDATA to the pixels P. [ The sensing mode is a mode of supplying data voltages for sensing to the pixels P and sensing predetermined voltages of the pixels P through the reference voltage lines R1 to Rp.

The sensing mode may be divided into first to third sensing modes. The first sensing mode is a mode for sensing the source voltage of the driving transistor (or the driving current of the driving transistor) to compensate the threshold voltage of the driving transistor. The source voltage of the driving transistor sensed in the first sensing mode may be converted into the first sensing data SD1 by the ADC 140 and stored in the memory of the data compensating unit 70. [ The first sensing data SD1 is data reflecting the threshold voltage of the driving transistor. The first sensing mode may be performed before the power of the OLED display is turned off.

The second sensing mode is a mode for sensing the source voltage of the driving transistor (or the driving current of the driving transistor) to compensate the electron mobility of the driving transistor. The source voltage of the driving transistor sensed in the second sensing mode may be converted into the first sensing data SD1 by the ADC 140 and stored in the memory of the data compensating unit 70. [ The second sensing data SD2 is data reflecting the electron mobility of the driving transistor. The second sensing mode may be performed as soon as the power of the organic light emitting display device is turned on, or may be performed in a predetermined cycle with the power of the organic light emitting display device turned on.

The third sensing mode is a mode for supplying the same sensing voltage supplied from the same line to at least two ADCs 140 to compensate for the characteristic change of the ADC 140. [ In the third sensing mode, the same sensing voltage may be converted into third sensing data SD3 by the ADC 140 and stored in the memory of the data compensating unit 70. [ The third sensing data SD3 is data reflecting changes in the characteristics of the ADC 140. [ The third sensing mode may be performed in a predetermined period in a state in which the power of the organic light emitting display device is turned on.

The data compensator 70 generates correction data for correcting the digital video data DATA using the first through third sensing data SD1, SD2, and SD3. The data compensator 70 applies correction data to the digital video data DATA from outside to generate compensation data CDATA. The data compensator 70 outputs the compensation data CDATA to the timing controller 60. [

The data compensating unit 70 may include a memory for storing the first through third sensing data SD1, SD2, and SD3. In addition, the data compensating section 70 may include a memory for storing correction data. The memory of the data compensating unit 70 may be a nonvolatile memory such as an EEPROM (electrically erasable programmable read-only memory). The data compensator 70 may be incorporated in the timing controller 60. [

The voltage supply unit 80 generates a reference voltage and supplies the reference voltage to the source drive ICs 21 of the data driver 20. In addition to the reference voltage, the voltage supply unit 80 may generate driving voltages necessary for driving the organic light emitting display and supply the driving voltages to the necessary configuration.

The timing control unit 60, the data compensation unit 70, and the voltage supply unit 80 may be mounted on the control circuit board. The control circuit board 90 may be connected to the source circuit board 50 by a flexible cable 91. The control circuit board 90 may be a printed circuit board.

As described above, the OLED display according to the exemplary embodiment of the present invention generates correction data using the first through third sensing data SD1, SD2, and SD3 sensed in the first through third sensing modes. , And applies correction data to the digital video data (DATA) to generate compensation data (CDATA). As a result, the embodiment of the present invention can compensate for the threshold voltage and electron mobility of the driving transistor of each of the pixels, and the characteristic change of the ADC 140 of each of the source drive ICs 21. Hereinafter, the operation of the pixel P in the display mode and the first to second sensing modes according to the embodiment of the present invention will be described with reference to FIGS. 6 to 9. FIG.

6 is a circuit diagram showing the pixel of FIG. 5 in detail. In FIG. 6, for convenience of explanation, a data line Dj (j is a positive integer satisfying 1? J? M) data line Dj, a u (u is a positive integer satisfying 1? A scan line Sk and a kth sensing signal line SEk, a voltage supply unit 80, a data supply unit 80, Only the switch SW connected between the voltage supply unit 110, the ADC 140 and the u-th reference voltage line Ru and the voltage supply unit 80 is shown.

6, a pixel P of the display panel 10 includes an organic light emitting diode OLED, a driving transistor DT, first and second switching transistors ST1 and ST2, and a storage capacitor Cst. . ≪ / RTI >

The organic light emitting diode OLED emits light according to the current supplied through the driving transistor DT. The organic light emitting diode OLED may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In the organic light emitting diode (OLED), when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively. The anode electrode of the organic light emitting diode OLED may be connected to the source electrode of the driving transistor DT and the cathode electrode may be connected to a second power supply line VSL to which a second power supply lower than the first power supply is supplied.

The driving transistor DT adjusts the current flowing from the first power supply line EVL to the organic light emitting diode OLED in accordance with the voltage difference between the gate electrode and the source electrode. The gate electrode of the driving transistor DT is connected to the first electrode of the first switching transistor ST1. The source electrode of the driving transistor DT is connected to the anode electrode of the organic light emitting diode OLED. The drain electrode of the driving transistor DT is connected to the first power line EVL. Lt; / RTI >

The first switching transistor ST1 is turned on by the kth scan signal of the kth scan line Sk to connect the jth data line Dj to the gate electrode of the driving transistor DT. The first electrode of the first switching transistor T1 is connected to the kth scan line Sk and the first electrode of the first switching transistor T1 is connected to the gate electrode of the first driving transistor DT1. .

The second switching transistor ST2 is turned on by the kth sensing signal of the kth sensing signal line SEk to connect the u th reference voltage line Ru to the source electrode of the driving transistor DT. The gate electrode of the second switching transistor ST3 is connected to the kth sensing signal line SEk and the first electrode thereof is connected to the u th reference voltage line Ru and the second electrode is connected to the source of the driving transistor DT Can be connected to the electrode.

It should be noted that the first electrode of each of the first and second switching transistors ST1 and ST2 may be a source electrode and the second electrode may be a drain electrode. That is, the first electrode of each of the first and second switching transistors ST1 and ST2 may be a drain electrode, and the second electrode may be a source electrode.

The storage capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The storage capacitor Cst stores the difference voltage between the gate voltage of the driving transistor DT and the source voltage.

The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed of a thin film transistor. Although the driving transistor DT and the first and second switching transistors ST1 and ST2 are formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in FIG. 6, shall. The driving transistor DT and the first and second switching transistors ST1 and ST2 may be formed of a P-type MOSFET. In this case, the timing charts of FIGS. 7 to 9 can be appropriately modified in accordance with the characteristics of the P-type MOSFET.

7 is a waveform diagram showing a scan signal and a sensing signal supplied to the pixel in the display mode, a switch control signal supplied to the switch, and a gate voltage and a source voltage of the driving transistor.

Referring to Fig. 7, during the first and second periods t1, t2 of the display mode, the switch SW is turned on by the switch control signal SCS of the first logic level voltage V1. The reference voltage VREF is supplied from the voltage supply unit 80 to the u th reference voltage line Ru during the first and second periods t1 and t2 of the display mode.

During the first period t1, the first switching transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk. During the first period t1, the second switching transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the first period t1, the switch SW is turned on by the switching control signal SCS of the first logic level voltage V1.

The emission data voltage EVdata of the jth data line Dj is supplied to the gate electrode of the driving transistor DT due to the turn-on of the first switching transistor ST1 during the first period t1. Due to the turn-on of the second switching transistor ST2 during the first period t1, the reference voltage VREF of the u-th reference voltage line Ru is supplied to the source electrode of the driving transistor DT.

During the second period t2, the first switching transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk. During the second period t2, the second switching transistor ST2 is turned off by the kth sensing signal SENSk of the gate-off voltage Voff supplied to the kth sensing signal line SEk.

The current Ids corresponding to the voltage difference between the gate voltage Vg and the source voltage Vs of the driving transistor DT flows to the organic light emitting diode OLED during the second period t2. As a result, the organic light emitting diode OLED emits light. Hereinafter, for the sake of convenience of explanation, it is defined as "current flowing through the driving transistor DT according to the voltage difference between the gate voltage Vg of the driving transistor DT and the source voltage Vs & do.

As described above, the embodiment of the present invention supplies the emission data voltage (EVdata) to the pixel P in the display mode. The emission data voltage EVdata senses the threshold voltage and the electron mobility of the driving transistor DT according to the first and second sensing modes and then outputs the compensation data CDATA compensated for the digital video data DATA And is the data voltage generated accordingly. As a result, in the embodiment of the present invention, the organic light emitting diode OLED of the pixel P emits light according to the threshold voltage of the driving transistor DT and the current Ids of the driving transistor DT, can do. Therefore, the embodiment of the present invention can increase the luminance uniformity of the pixels P.

8 is a waveform diagram showing a scan signal and a sensing signal supplied to a pixel in the first sensing mode, a switch control signal supplied to the switch, and a gate voltage and a source voltage of the driving transistor.

During the first period t1 ', the first switching transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk, The transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the first period t1 ', the switch SW is turned on by the switch control signal SCS of the first logic level voltage V1.

The reference voltage VREF is supplied from the voltage supply unit 80 to the u th reference voltage line Ru due to the turn-on of the switch SW during the first period t1 '. Due to the turn-on of the second switching transistor ST2 during the first period t1 ', the reference voltage VREF of the u th reference voltage line Ru is supplied to the source electrode of the driving transistor DT. That is, the source electrode of the driving transistor DT is initialized to the reference voltage VREF.

During the second period t2 ', the first switching transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk, The transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the second period t2 ', the switch SW is turned off by the switch control signal SCS of the second logic level voltage V2.

The reference voltage VREF is not supplied to the u th reference voltage line Ru due to the turn-off of the switch SW during the second period t2 ', and the u th reference voltage line Ru is supplied to the ADC 140, Respectively. Due to the turn-on of the first switching transistor ST1 during the second period t2 ', the sensing data voltage SVdata is supplied to the gate electrode of the driving transistor DT. Due to the turn-on of the second switching transistor ST2 during the second period t2 ', the reference voltage VREF of the u th reference voltage line Ru is supplied to the source electrode of the driving transistor DT.

Since the voltage difference (Vgs = SVdata-VREF) between the gate electrode and the source electrode of the driving transistor DT is greater than the threshold voltage Vth during the second period t2 ' And the voltage difference (Vgs) between the source electrode and the source electrode reaches the threshold voltage (Vth). As a result, the source voltage of the driving transistor DT rises to "SVdata-Vth" as shown in Fig. Therefore, the threshold voltage of the driving transistor DT is sensed to the source electrode of the driving transistor DT during the second period t2 '.

During the third period t3 ', the first switching transistor ST1 is turned on by the kth scan signal SCANk of the gate-on voltage Von supplied to the kth scan line Sk, The transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the third period t3 ', the switch SW is turned off by the switch control signal SCS of the second logic level voltage V2.

The reference voltage VREF is not supplied to the u th reference voltage line Ru due to the turn-off of the switch SW during the third period t3 ', and the u th reference voltage line Ru is supplied to the ADC 140, Respectively. Due to the turn-on of the second switching transistor ST2 during the third period t3 ', the source electrode of the driving transistor DT is connected to the ADC 140 via the u th reference voltage line Ru. Therefore, the ADC 140 can sense the source voltage of the driving transistor DT, i.e., "SVdata-Vth ".

As described above, the embodiment of the present invention can sense the source voltage "SVdata-Vth" of the driving transistor in which the threshold voltage of the driving transistor DT is reflected in the first sensing mode.

9 is a waveform diagram showing a scan signal supplied to a pixel in the second sensing mode, a sensing signal and a switch control signal supplied to the switch, and a gate voltage and a source voltage of the driving transistor.

During the first period t1 ", the first switching transistor ST1 is turned off by the k-th scan signal SCANk of the gate-off voltage Voff supplied to the k-th scan line Sk, The transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the first period t1 ", the switch SW And is turned on by the switch control signal SCS of the first logic level voltage V1.

The reference voltage VREF is supplied from the voltage supply unit 80 to the u th reference voltage line Ru due to the turn-on of the switch SW during the first period t1 ". During the first period t1 " Due to the turn-on of the second switching transistor ST2, the reference voltage VREF of the u th reference voltage line Ru is supplied to the source electrode of the driving transistor DT. That is, the source electrode of the driving transistor DT is initialized to the reference voltage VREF.

During the second period t2 ", the first switching transistor ST1 is turned on by the k-th scan signal SCANk of the gate-on voltage Von supplied to the k-th scan line Sk, The transistor ST2 is turned on by the kth sensing signal SENSk of the gate-on voltage Von supplied to the kth sensing signal line SEk. During the second period t2 ", the switch SW And is turned off by the switch control signal SCS of the second logic level voltage V2.

The reference voltage VREF is not supplied to the u th reference voltage line Ru due to the turn-off of the switch SW during the second period t2 ", and the u th reference voltage line Ru is supplied to the ADC 140, The sensing data voltage SVdata is supplied to the gate electrode of the driving transistor DT due to the turn-on of the first switching transistor ST1 during the second period t2 ". The reference voltage VREF of the u th reference voltage line Ru is supplied to the source electrode of the driving transistor DT due to the turn-on of the second switching transistor ST2 during the second period t2 ".

Since the voltage difference (Vgs = SVdata-VREF) between the gate electrode and the source electrode of the driving transistor DT is greater than the threshold voltage (Vth) during the second period t2 " Current flows until the voltage difference Vgs between the source electrode and the source electrode reaches the threshold voltage Vth. However, the second period t2 "in Fig. 9 corresponds to the second period t2 ' And the second period t2 "ends before the source voltage Vs of the driving transistor DT reaches" Vdata-Vth ".

At this time, the current of the driving transistor DT can be defined as shown in Equation (1).

&Quot; W "is the channel width of the driving transistor DT," L "is the capacitance of the driving transistor DT, Quot; means the channel length of the driving transistor DT.

The current of the driving transistor DT is proportional to the electron mobility K of the driving transistor DT as shown in Equation 1 and therefore the amount of rise of the source voltage Vs of the driving transistor DT during the second period t2 & The electron mobility K of the driving transistor DT is proportional to the electron mobility K of the driving transistor DT during the second period t2 " The lift amount becomes larger.

As a result, the amount of rise of the source voltage Vs varies depending on the electron mobility K of the driving transistor DT during the second period t2 ", and in Fig. 9, the source voltage Vs The source voltage of the driving transistor DT rises to "SVdata + alpha" as shown in Fig. 9 in accordance with the electron mobility K. Therefore, during the second period t2 " The voltage reflecting the electron mobility K of the driving transistor DT is sensed to the source electrode of the transistor DT.

As described above, the embodiment of the present invention can sense the source voltage "SVdata + alpha" of the driving transistor in which the electron mobility K of the driving transistor DT is reflected in the second sensing mode.

10 is an exemplary view showing reference voltage lines connected to adjacent source drive ICs according to an embodiment of the present invention.

FIG. 10 shows an embodiment of the present invention for driving the third sensing mode. The third sensing mode is a mode for supplying the same sensing voltage supplied from the same line to at least two ADCs 140 to compensate for the characteristic change of the ADC 140. [ In FIG. 10, only the first and second source drive ICs 21a and 21b are illustrated for convenience of explanation.

10, the first source drive IC 21a is mounted on the first flexible film 22a, and the second source drive IC 21b is mounted on the second flexible film 22b. Each of the first and second flexible films 22a and 22b may be attached to the lower substrate 11 of the display panel using an anisotropic conductive film. Thus, each of the first and second source drive ICs 21a and 21b can be connected to the data lines of the lower substrate 11 and the reference voltage lines.

Each of the first and second source drive ICs 21a and 21b may be connected to z reference voltage lines as shown in FIG. In the display mode, the first and second sensing modes, the first source driver IC 21a may be connected to the first to z-th reference voltage lines R1 to Rz, and the second source driver IC 21b may be connected to the And may be connected to the z + 1 th to the 2z reference voltage lines Rz + 1 to R2z. That is, in the display mode, the first and second sensing modes, the first source driver IC 21a senses predetermined voltages of the pixels P from the first to z-th reference voltage lines R1 to Rz, The second source driver IC 21b may sense the predetermined voltages of the pixels P from the z + 1 to the 2z reference voltage lines Rz + 1 to R2z.

In the third sensing mode, the second source driver IC 21b may be connected to any one of the reference voltage lines connected to the first source driver IC 21a. For example, in the third sensing mode, the second source driver IC 21b may be connected to the z-th reference voltage line connected to the first source driver IC 21a. In this case, the second source drive IC 21b may be disconnected from any one of the z + 1 to the 2z reference voltage lines Rz + 1 to R2z. For example, the second source drive IC 21b may be disconnected from the z + 1 reference voltage lines Rz + 1.

10, in the third sensing mode, the second source driver IC 21b is connected to any one of the reference voltage lines connected to the first source driver IC 21a, and the z + The connection to any one of the second reference voltage lines Rz + 1 to R2z is disconnected. However, the present invention is not limited to this. That is, in the third sensing mode, the first source driver IC 21a is connected to any one of the reference voltage lines connected to the second source driver IC 21a, and the first to z- The connection with any one of the reference voltage lines R1 to Rz may be disconnected.

A first transistor T1 is connected between the second source driver IC 21b and the z-th reference voltage line Rz to control the connection between the second source driver IC 21b and the z-th reference voltage line Rz . The first transistor T1 is turned on by the first control signal of the first control line CL1 to connect the second source driver IC 21b with the zth reference voltage line Rz. The gate electrode of the first transistor T1 is connected to the first control line CL1 and the first electrode is connected to the second source drive IC 21b and the second electrode is connected to the zth reference voltage line Rz Can be connected.

The second source driver IC 21b and the (z + 1) th reference voltage line Rz + 1 are controlled to control the connection between the second source drive IC 21b and the z + 1 reference voltage line Rz + The second transistor T2 may be arranged between the first transistor T2 and the second transistor T2. The second transistor T2 is turned on by the inverted signal of the first control signal to connect the second source driver IC 21b and the z + 1 reference voltage line Rz + 1. The gate electrode of the second transistor T2 is connected to the inverter INV connected to the first control line CL1, the first electrode of the second transistor T2 is connected to the second source driver IC 21b, And may be connected to the reference voltage line Rz. The inverter INV may be connected between the first control line CL1 and the gate electrode of the second transistor T2. The inverter INV2 supplies an inverted signal obtained by inverting the first control signal of the first control line CL1 to the gate electrode of the second transistor T2.

It should be noted that the first electrode of each of the first and second transistors T1 and T2 may be a source electrode and the second electrode may be a drain electrode. That is, the first electrode of each of the first and second transistors T1 and T2 may be a drain electrode, and the second electrode may be a source electrode.

The first and second transistors T1 and T2 may be formed of a thin film transistor. In FIG. 10, the first and second transistors T1 and T2 are formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor). However, the present invention is not limited thereto. The first and second transistors T1 and T2 may be formed of a P-type MOSFET. In this case, the first control signal of the first control line CL1 may also be appropriately modified to match the characteristics of the P-type MOSFET.

As a result, in the display mode, in the first and second sensing modes, the first transistor T1 is turned off by the first control signal having the first logic level voltage of the first control line CL1, (T2) may be turned on by the inverted signal of the first control signal having the second logic level voltage. Accordingly, in the display mode, the first and second sensing modes, the first source driver IC 21a can be connected to the first to z-th reference voltage lines R1 to Rz, and the second source driver IC 21b may be connected to the z + 1 th to the 2z reference voltage lines Rz + 1 to R2z. That is, in the display mode, the first and second sensing modes, the first source driver IC 21a senses predetermined voltages of the pixels P from the first to z-th reference voltage lines R1 to Rz, The second source driver IC 21b may sense the predetermined voltages of the pixels P from the z + 1 to the 2z reference voltage lines Rz + 1 to R2z.

Also, in the third sensing mode, the first transistor (T1) is turned on by a first control signal having a second logic level voltage of the first control line (CL1), and the second transistor (T2) Can be turned off by the inverted signal of the first control signal having the level voltage. Accordingly, the ADCs 140 of the first and second source driver ICs 21a and 21b can receive the same sensing voltage from the same z-th reference voltage line Rz in the third sensing mode.

As described above, the ADCs 140 of the first and second source driver ICs 21a and 21b can receive the same sensing voltage from the same z-th reference voltage line Rz in the third sensing mode. For example, the ADCs 140 of the first and second source driver ICs 21a and 21b are connected in parallel in the third sensing mode to the pixel P through the z reference voltage line Rz in the first sensing mode. The source voltage of the driving transistor can be sensed. Alternatively, the ADCs 140 of the first and second source driver ICs 21a and 21b are driven in the third sensing mode in the second sensing mode through the z-th reference voltage line Rz, It is possible to sense the source voltage.

On the other hand, if the same sensing voltage is input to the ADC 140, the same sensing data should be output. However, characteristics of the ADC 140 may be influenced by factors such as temperature, humidity, and pressure after shipment. In this case, even if each of the ADCs 140 senses the same voltage through the sensing line, a difference may occur in the sensing data between the ADCs 140 according to the characteristic change of the ADC 140. [

One embodiment of the present invention allows the ADCs 140 of the first and second source drive ICs 21a and 21b to receive the same sensing voltage from the same z reference voltage line Rz, Analyze the output sensing data. For example, in the third sensing mode, the third sensing data SD3 output from the ADC 140 of the first source driver IC 21a indicates 3V and the ADC 140 of the second source driver IC 21a The third sensing data SD3 outputted from the second sensing circuit 12 indicates 3.5V. In this case, the third sensing data SD3 of the ADC 140 of the first source drive IC 21a is at least 0.5V higher than the third sensing data SD3 of the ADC 140 of the second source drive IC 21a Respectively. Accordingly, the data compensating unit 70 adds the first and second sensing data SD1 and SD2 output from the ADC 140 of the first source driver IC 21a by 0.5 V or multiplies the predetermined gain value . As such, embodiments of the present invention can compensate for differences between the sensing data of the ADCs 140 due to changes in the characteristics of the ADCs 140. Therefore, the embodiment of the present invention can prevent the block dim from being viewed to the user.

11 is an exemplary view showing source drive ICs and a source circuit board according to another embodiment of the present invention.

FIG. 11 shows another embodiment of the present invention for driving the third sensing mode. The third sensing mode is a mode for supplying the same sensing voltage supplied from the same line to at least two ADCs 140 to compensate for the characteristic change of the ADC 140. [

Referring to FIG. 11, each of the source drive ICs 21a, 21b, 21c, and 21d is mounted on each of the flexible films 22a, 22b, 22c, and 22d. The flexible films 22a, 22b, 22c, and 22d may be attached to the source circuit board 50 and the lower substrate 11 of the display panel.

The source circuit board 50 includes a sensing voltage line SVL connected to the voltage supply unit 80 and supplied with a sensing voltage from the voltage supply unit 80. The sensing voltage line SVL may be connected to the ADCs 140 of the source drive ICs 21a, 21b, 21c, and 21d.

The source circuit board 50 may further include capacitors C connected to the sensing voltage line SVL. The capacitors C serve to stably maintain the sensing voltage of the sensing voltage line SVL.

The source circuit board 50 is disposed between the sensing voltage line SVL and each of the source drive ICs 21a, 21b, 21c and 21d and connected to the sensing voltage line SVL and the source drive ICs 21a, 21b and 21c TR2, TR3, TR4, TR5, and TR6 that control the connection of each of the transistors TR1, TR1, and TR1. Transistors TR1, TR2, TR3, TR4, TR5 and TR6 connect the sense voltage line SVL to the ADCs 140 of the source drive ICs 21a, 21b, 21c and 21d in the third sensing mode . In the third sensing mode, each of the transistors TR1, TR2, TR3, TR4, TR5 and TR6 is turned on by the second control signal of the second control line CL2 to turn the sensing voltage line SVL into the source To the ADCs 140 of the drive ICs 21a, 21b, 21c, and 21d. The control electrode of each of the transistors TR1, TR2, TR3, TR4, TR5 and TR6 is connected to the second control line CL2, and the first electrode thereof is connected to the source driver ICs 21a, 21b, 21c, (140), and the second electrode may be connected to the sensing voltage line (SVL).

It should be noted that the first electrode of each of the first and second transistors T1 and T2 may be a source electrode and the second electrode may be a drain electrode. That is, the first electrode of each of the first and second transistors T1 and T2 may be a drain electrode, and the second electrode may be a source electrode.

The transistors TR1, TR2, TR3, TR4, TR5, and TR6 may be formed of a field effect transistor or a bipolar junction transistor. Although the transistors TR1, TR2, TR3, TR4, TR5, and TR6 are formed of an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) in FIG. 11, the present invention is not limited thereto. The transistors TR1, TR2, TR3, TR4, TR5, and TR6 may be formed of a P-type MOSFET. In this case, the second control signal of the second control line CL2 may also be appropriately modified to match the characteristics of the P-type MOSFET.

As a result, in the display mode, the first and second sensing modes, the transistors TR1, TR2, TR3, TR4, TR5 and TR6 are connected to the second control signal having the first logic level voltage of the second control line CL2 As shown in FIG. In the third sensing mode, the transistors TR1, TR2, TR3, TR4, TR5 and TR6 can be turned on by the second control signal having the second logic level voltage of the second control line CL2. Accordingly, the ADCs 140 of the first and second source driver ICs 21a and 21b can receive the same sensing voltage from the same sensing voltage line SVL in the third sensing mode.

As described above, the ADCs 140 of the first and second source driver ICs 21a and 21b can receive the same sensing voltage from the same sensing voltage line SVL in the third sensing mode.

11, the source drive ICs 21a, 21b, 21c and 21d are connected to one sensing voltage line SVL through the transistors TR1, TR2, TR3, TR4, TR5 and TR6. It is not limited. That is, as shown in FIG. 12, the first and second source drive ICs 21a and 21b are connected to the first sensing voltage line SVL1 through the first and second transistors TR1 and TR2, The third source drive ICs 21b and 21c are connected to the second sensing voltage line SVL2 through the third and fourth transistors TR3 and TR4 and the third and fourth source drive ICs 21c and 21c are connected to the second sensing voltage line SVL2 through the third and fourth transistors TR3 and TR4, 21d may be connected to the third sensing voltage line SVL3 through the fifth and sixth transistors TR5, TR6.

On the other hand, if the same sensing voltage is input to the ADC 140, the same sensing data should be output. However, characteristics of the ADC 140 may be influenced by factors such as temperature, humidity, and pressure after shipment. In this case, even if each of the ADCs 140 senses the same voltage through the sensing line, a difference may occur in the sensing data between the ADCs 140 according to the characteristic change of the ADC 140. [

The embodiment of the present invention analyzes the sensing data output by the ADCs 140 after the ADCs 140 of the source drive ICs 21a and 21b receive the same sensing voltage from the same sensing voltage line SVL. For example, in the third sensing mode, the third sensing data SD3 output from the ADC 140 of the first source driver IC 21a indicates 3V and the ADC 140 of the second source driver IC 21a The third sensing data SD3 outputted from the second sensing circuit 12 indicates 3.5V. In this case, the third sensing data SD3 of the ADC 140 of the first source drive IC 21a is at least 0.5V higher than the third sensing data SD3 of the ADC 140 of the second source drive IC 21a Respectively. Accordingly, the data compensating unit 70 adds the first and second sensing data SD1 and SD2 output from the ADC 140 of the first source driver IC 21a by 0.5 V or multiplies the predetermined gain value . As such, embodiments of the present invention can compensate for differences between the sensing data of the ADCs 140 due to changes in the characteristics of the ADCs 140. Therefore, the embodiment of the present invention can prevent the block dim from being viewed to the user.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

10: display panel 20: data driver
21: Source drive IC 22: Flexible film
40: scan driver 41: scan signal output unit
42: sensing signal output unit 50: source circuit board
60: timing controller 70: data compensating unit
80: voltage supply unit 90: control circuit board
91: flexible cable 110: data voltage supply unit
140: Analog to Digital Converters

Claims (10)

A display panel including pixels connected to the data lines and the reference voltage lines; And
A data voltage supplier for converting the digital compensation data into data voltages and supplying the data voltages to the data lines, and an analog digital converter for sensing predetermined voltages of the pixels through the reference voltage lines and outputting the sensed data as digital data sensing data Source drive ICs; And
And a timing controller for converting the digital video data input from the outside into the digital compensation data based on the sensing data and supplying the digital compensation data to the data voltage supply unit,
And the analog digital converters of the at least two source drive ICs of the source drive ICs receive the same sensing voltage from the same line. The method according to claim 1,
In a sensing mode of supplying data voltages for sensing to the pixels and sensing predetermined voltages of the pixels through the reference voltage lines,
And the i + 1 (i is a positive integer) source drive IC is connected to one of the reference voltage lines connected to the ith source drive IC. 3. The method of claim 2,
In the sensing mode,
Th source drive IC is connected to first to z-th (where z is an integer of 2 or more) reference voltage lines, and the (i + 1) th source drive IC is connected to any one of the first to z- Line of the organic light emitting display device. The method of claim 3,
In the display mode in which the display data voltages are supplied to the pixels and the pixels emit light,
Th source drive IC is connected to the first to z-th reference voltage lines, and the (i + 1) th source drive IC is connected to z + Display device. 5. The method of claim 4,
A first transistor connected between any one of the reference voltage lines and the (i + 1) th source drive IC; And
And a second transistor connected between any one of the reference voltage lines and the i-th source drive IC. 6. The method of claim 5,
Wherein in the sensing mode the first transistor is turned off by a first switch control signal having a first logic level voltage of a first switch control line and the second transistor is turned off by a first switch control having a second logic level voltage, And turned on by an inverted signal of the signal. The method according to claim 6,
The first transistor is turned on by the first switch control signal having the second logic level voltage and the second transistor is turned on by the inverted signal of the first switch control signal having the first logic level voltage, Off state of the organic light emitting display device. The method according to claim 1,
In a sensing mode of supplying data voltages for sensing to the pixels and sensing predetermined voltages of the pixels through the reference voltage lines,
Further comprising a voltage supply unit for supplying a sensing voltage to the analog digital converters of the source drive ICs. 9. The method of claim 8,
Flexible films on which each of the source drive ICs is mounted; And
Further comprising a source circuit board attached to the flexible films,
The source circuit board includes:
A sensing voltage line to which the sensing voltage is supplied from the power source and is connected to analog digital converters of the source drive ICs; And
And a capacitor connected to the sensing voltage line. 10. The method of claim 9,
Further comprising transistors connected between the sensing voltage line and each of the source drive ICs,
And the transistors are turned on by the second control signal of the second control line in the sensing mode.

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