KR20140083042A - 수직 통합용 스택형 비아들 - Google Patents

수직 통합용 스택형 비아들 Download PDF

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Publication number
KR20140083042A
KR20140083042A KR1020147013565A KR20147013565A KR20140083042A KR 20140083042 A KR20140083042 A KR 20140083042A KR 1020147013565 A KR1020147013565 A KR 1020147013565A KR 20147013565 A KR20147013565 A KR 20147013565A KR 20140083042 A KR20140083042 A KR 20140083042A
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KR
South Korea
Prior art keywords
metal layer
via structure
layer
implementations
central portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020147013565A
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English (en)
Korean (ko)
Inventor
야오링 판
리시아 초우
Original Assignee
퀄컴 엠이엠에스 테크놀로지스, 인크.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 퀄컴 엠이엠에스 테크놀로지스, 인크. filed Critical 퀄컴 엠이엠에스 테크놀로지스, 인크.
Publication of KR20140083042A publication Critical patent/KR20140083042A/ko
Withdrawn legal-status Critical Current

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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0006—Interconnects
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00222—Integrating an electronic processing unit with a micromechanical structure
    • B81C1/00246—Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Light Control Or Optical Switches (AREA)
  • Micromachines (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020147013565A 2011-10-20 2012-10-17 수직 통합용 스택형 비아들 Withdrawn KR20140083042A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/278,080 2011-10-20
US13/278,080 US10131534B2 (en) 2011-10-20 2011-10-20 Stacked vias for vertical integration
PCT/US2012/060648 WO2013059345A1 (en) 2011-10-20 2012-10-17 Stacked vias for vertical integration

Publications (1)

Publication Number Publication Date
KR20140083042A true KR20140083042A (ko) 2014-07-03

Family

ID=47138180

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147013565A Withdrawn KR20140083042A (ko) 2011-10-20 2012-10-17 수직 통합용 스택형 비아들

Country Status (7)

Country Link
US (1) US10131534B2 (enExample)
EP (1) EP2768767A1 (enExample)
JP (1) JP2014534470A (enExample)
KR (1) KR20140083042A (enExample)
CN (2) CN110228785A (enExample)
IN (1) IN2014CN02998A (enExample)
WO (1) WO2013059345A1 (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180123245A1 (en) * 2016-10-28 2018-05-03 Broadcom Corporation Broadband antenna array for wireless communications
CN108231747A (zh) * 2016-12-21 2018-06-29 中芯国际集成电路制造(上海)有限公司 半导体器件及其制作方法、电子装置
US20190169020A1 (en) * 2017-12-05 2019-06-06 Intel Corporation Package substrate integrated devices
EP3598235A1 (en) 2018-07-18 2020-01-22 ASML Netherlands B.V. Metrology apparatus and method for determining a characteristic relating to one or more structures on a substrate

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US5798283A (en) 1995-09-06 1998-08-25 Sandia Corporation Method for integrating microelectromechanical devices with electronic circuitry
US5917645A (en) * 1997-03-28 1999-06-29 Daewoo Electronics Co., Ltd. Thin film actuated mirror array in an optical projection system and method for manufacturing the same
US6320244B1 (en) * 1999-01-12 2001-11-20 Agere Systems Guardian Corp. Integrated circuit device having dual damascene capacitor
US6562656B1 (en) 2001-06-25 2003-05-13 Thin Film Module, Inc. Cavity down flip chip BGA
US20030234415A1 (en) * 2002-06-24 2003-12-25 Hwey-Ching Chien Scalable three-dimensional fringe capacitor with stacked via
JP4289005B2 (ja) 2003-04-30 2009-07-01 日本ビクター株式会社 多層プリント配線板
US20050041405A1 (en) 2003-08-22 2005-02-24 Intel Corporation Stacked via structure that includes a skip via
US7081647B2 (en) 2003-09-29 2006-07-25 Matsushita Electric Industrial Co., Ltd. Microelectromechanical system and method for fabricating the same
JP4776197B2 (ja) 2004-09-21 2011-09-21 日本特殊陶業株式会社 配線基板の検査装置
JP4608294B2 (ja) 2004-11-30 2011-01-12 日亜化学工業株式会社 樹脂成形体及び表面実装型発光装置並びにそれらの製造方法
JP4724488B2 (ja) * 2005-02-25 2011-07-13 日立オートモティブシステムズ株式会社 集積化マイクロエレクトロメカニカルシステム
KR100881303B1 (ko) * 2005-11-02 2009-02-03 이비덴 가부시키가이샤 반도체 장치용 다층 프린트 배선판 및 그 제조 방법
TWI298608B (en) 2006-05-19 2008-07-01 Foxconn Advanced Tech Inc Method for manufacturing stack via of hdi printed circuit board
US7777715B2 (en) 2006-06-29 2010-08-17 Qualcomm Mems Technologies, Inc. Passive circuits for de-multiplexing display inputs
US20080029898A1 (en) 2006-08-01 2008-02-07 Farooq Mukta G Via stack structures
US7733552B2 (en) * 2007-03-21 2010-06-08 Qualcomm Mems Technologies, Inc MEMS cavity-coating layers and methods
US7570415B2 (en) 2007-08-07 2009-08-04 Qualcomm Mems Technologies, Inc. MEMS device and interconnects for same
US8022896B2 (en) * 2007-08-08 2011-09-20 Qualcomm Mems Technologies, Inc. ESD protection for MEMS display panels
JP5016449B2 (ja) * 2007-11-13 2012-09-05 ローム株式会社 半導体装置
JP5125531B2 (ja) 2008-01-16 2013-01-23 富士通セミコンダクター株式会社 配線基板及び半導体装置
US8242593B2 (en) 2008-01-27 2012-08-14 International Business Machines Corporation Clustered stacked vias for reliable electronic substrates
US20090194861A1 (en) 2008-02-04 2009-08-06 Mathias Bonse Hermetically-packaged devices, and methods for hermetically packaging at least one device at the wafer level
JP5102726B2 (ja) * 2008-09-08 2012-12-19 ラピスセミコンダクタ株式会社 半導体装置の製造方法
CN101728355A (zh) 2008-11-03 2010-06-09 巨擘科技股份有限公司 多层基板的导孔结构及其制造方法
CN102379037B (zh) * 2009-03-30 2015-08-19 高通股份有限公司 使用顶部后钝化技术和底部结构技术的集成电路芯片
JP2010283189A (ja) 2009-06-05 2010-12-16 Shinko Electric Ind Co Ltd 配線基板及びその製造方法
TW201102340A (en) * 2009-07-10 2011-01-16 Nat Univ Tsing Hua A method for fabricating a multilayer microstructure with balancing residual stress capability
CN102001613B (zh) 2009-09-02 2014-10-22 原相科技股份有限公司 微电子装置及制造方法、微机电封装结构及封装方法
JP5134027B2 (ja) * 2010-02-18 2013-01-30 北陸電気工業株式会社 圧電型三軸加速度センサ

Also Published As

Publication number Publication date
CN110228785A (zh) 2019-09-13
EP2768767A1 (en) 2014-08-27
CN103974896A (zh) 2014-08-06
US10131534B2 (en) 2018-11-20
JP2014534470A (ja) 2014-12-18
US20130100143A1 (en) 2013-04-25
WO2013059345A1 (en) 2013-04-25
IN2014CN02998A (enExample) 2015-07-03

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Legal Events

Date Code Title Description
PA0105 International application

Patent event date: 20140520

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid