KR20130125303A - 제어 장치, 기억 장치, 데이터 기입 방법 - Google Patents

제어 장치, 기억 장치, 데이터 기입 방법 Download PDF

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Publication number
KR20130125303A
KR20130125303A KR1020130046708A KR20130046708A KR20130125303A KR 20130125303 A KR20130125303 A KR 20130125303A KR 1020130046708 A KR1020130046708 A KR 1020130046708A KR 20130046708 A KR20130046708 A KR 20130046708A KR 20130125303 A KR20130125303 A KR 20130125303A
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South Korea
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physical
page
data
logical
writing
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KR1020130046708A
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English (en)
Korean (ko)
Inventor
유야 이시카와
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소니 주식회사
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Application filed by 소니 주식회사 filed Critical 소니 주식회사
Publication of KR20130125303A publication Critical patent/KR20130125303A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7202—Allocation control and policies
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7207—Details relating to flash memory management management of metadata or control data

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Read Only Memory (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
KR1020130046708A 2012-05-08 2013-04-26 제어 장치, 기억 장치, 데이터 기입 방법 Withdrawn KR20130125303A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JPJP-P-2012-106830 2012-05-08
JP2012106830A JP5929485B2 (ja) 2012-05-08 2012-05-08 制御装置、記憶装置、データ書込方法

Publications (1)

Publication Number Publication Date
KR20130125303A true KR20130125303A (ko) 2013-11-18

Family

ID=49534164

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020130046708A Withdrawn KR20130125303A (ko) 2012-05-08 2013-04-26 제어 장치, 기억 장치, 데이터 기입 방법

Country Status (5)

Country Link
US (1) US9454475B2 (https=)
JP (1) JP5929485B2 (https=)
KR (1) KR20130125303A (https=)
CN (1) CN103389881A (https=)
TW (1) TW201401048A (https=)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103729303B (zh) * 2014-01-20 2017-03-29 飞天诚信科技股份有限公司 一种Flash的数据写入和读取方法
TWI545571B (zh) * 2014-02-18 2016-08-11 慧榮科技股份有限公司 存取快閃記憶體的方法及相關的控制器與記憶裝置
US9529668B2 (en) 2014-09-26 2016-12-27 Intel Corporation Method and system for using NAND page buffers to improve the transfer buffer utilization of a solid state drive
US10489241B2 (en) * 2015-12-30 2019-11-26 Arteris, Inc. Control and address redundancy in storage buffer
CN107092560B (zh) * 2016-02-17 2020-06-16 建兴储存科技(广州)有限公司 固态储存装置及运用于其中的快闪转换层对应表重建方法
CN109086006B (zh) * 2018-07-24 2021-10-15 浪潮电子信息产业股份有限公司 一种数据读取的方法以及相关装置
CN109189348B (zh) * 2018-10-08 2020-07-24 华中科技大学 基于电荷捕获型3d tlc闪存的存储系统的读性能优化方法
CN110471863A (zh) * 2019-08-13 2019-11-19 深圳忆联信息系统有限公司 基于固态硬盘的数据写入读取方法、装置和计算机设备

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5162846B2 (ja) 2005-07-29 2013-03-13 ソニー株式会社 記憶装置、コンピュータシステム、および記憶システム
JP2007094921A (ja) 2005-09-30 2007-04-12 Toshiba Corp メモリカードとその制御方法
JP5076411B2 (ja) 2005-11-30 2012-11-21 ソニー株式会社 記憶装置、コンピュータシステム
JP2008112285A (ja) * 2006-10-30 2008-05-15 Toshiba Corp 不揮発性メモリシステム
JP4537420B2 (ja) 2007-04-02 2010-09-01 株式会社リコー Ｓｉｍｄ型マイクロプロセッサ
JP4356782B2 (ja) 2007-09-12 2009-11-04 ソニー株式会社 メモリ装置、メモリ制御方法、およびプログラム
JP4649503B2 (ja) * 2008-08-13 2011-03-09 株式会社東芝 半導体装置
JP4666081B2 (ja) * 2009-02-09 2011-04-06 Ｔｄｋ株式会社 メモリコントローラ及びメモリコントローラを備えるフラッシュメモリシステム、並びにフラッシュメモリの制御方法
JP2010198407A (ja) 2009-02-26 2010-09-09 Sony Corp 情報処理装置、およびデータ記録制御方法、並びにプログラム
JP2010282492A (ja) * 2009-06-05 2010-12-16 Toshiba Corp メモリシステム
JP4956593B2 (ja) * 2009-09-08 2012-06-20 株式会社東芝 メモリシステム

Also Published As

Publication number Publication date
US20130304971A1 (en) 2013-11-14
JP5929485B2 (ja) 2016-06-08
CN103389881A (zh) 2013-11-13
US9454475B2 (en) 2016-09-27
JP2013235630A (ja) 2013-11-21
TW201401048A (zh) 2014-01-01

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PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20130426

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid