KR20130122347A - Method for manufacturing solar cell - Google Patents

Abstract

A method for manufacturing a solar cell according to an embodiment comprises: a step of preparing a semiconductor substrate having a first surface, a second surface arranged at an opposite position of the first surface, and side surfaces intersecting the first surface and the second surface; a first doping step of ion-injecting first conductive impurities to the first surface on the first surface; a first activating heat treatment step of activating the first conductive impurities; an isolation step of eliminating the first conductive impurities remaining at the side surfaces of the semiconductor substrate by engraving corresponding portions; a second doping step of ion-injecting second conductive impurities to the second surface on the semiconductor substrate; and a second activating heat treatment step of activating the second conductive impurities. [Reference numerals] (ST10) Step for preparing a semiconductor substrate;(ST20) Step for first doping;(ST30) Step for first activating heat treatment;(ST40) Step for isolation;(ST50) Step for second doping;(ST60) Step for second activating heat treatment;(ST70) Step for forming a reflection preventing film and a passivation film;(ST80) Step for forming electrodes

Description

[0001] METHOD FOR MANUFACTURING SOLAR CELL [0002]

The present invention relates to a method for manufacturing a solar cell, and more particularly to a method for manufacturing a solar cell with improved process.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such a solar cell, an impurity layer is formed to cause photoelectric conversion to form a pn junction, and the like, and an electrode connected to the impurity layer is formed. When an impurity layer is formed, an unpredictable process error or the like may cause an unwanted electrical short. Then, the reverse current (reverse current) of the solar cell is increased, the efficiency may be lowered. Various methods have been proposed to prevent this, but these methods have a problem of damaging solar cells or complicating manufacturing processes.

The present invention is to provide a method for manufacturing a solar cell that can produce a high efficiency solar cell by a simple manufacturing process.

A method of manufacturing a solar cell according to an embodiment includes preparing a semiconductor substrate having a first surface and a second surface opposite to each other, and a side surface intersecting the first surface and the second surface; First doping to ion implant a first conductivity type impurity into the first surface of the semiconductor substrate; A first activation heat treatment step of activating the first conductivity type impurity; Etching the side surface of the semiconductor substrate to remove the first conductivity type impurities remaining in the corresponding portion; A second doping for ion implanting a second conductivity type impurity into the second surface of the semiconductor substrate; And a second activation heat treatment step of activating the second conductivity type impurity.

According to the present exemplary embodiment, an unnecessary electrical short-circuit that may occur when cross-sectional doping is performed on both surfaces of the semiconductor substrate by etching side surfaces of the semiconductor substrate between the first and second doping steps may be performed. As a result, the reverse current and the saturation current can be reduced, thereby improving the current density and the open voltage. In addition, it is possible to minimize hot spots and heat generation that may occur at the end of the solar cell. That is, the efficiency of the solar cell can be improved and the life can be extended.

In addition, the activation heat treatment for the first conductivity type impurity and the activation heat treatment for the second conductivity type impurity may be performed in separate steps, and activation may be performed under optimized conditions according to the characteristics of each conductivity type impurity.

In addition, the first conductive heat treatment step may be performed to isolate the emitter layer by activating the first conductivity type impurity. Accordingly, the first conductivity type impurities implanted into the semiconductor substrate in the isolating step may not be lost, thereby improving stability in the manufacturing process.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.
2 is a flowchart illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
3A to 3H are cross-sectional views illustrating a method of manufacturing a solar cell according to an embodiment of the present invention.
4 is a cross-sectional view showing the step of isolating a method of manufacturing a solar cell according to an embodiment of the present invention.
5 is a cross-sectional view of a solar cell according to another embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a method of manufacturing a solar cell according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. First, after explaining the structure of the solar cell manufactured by the method for manufacturing a solar cell according to an embodiment of the present invention, a method for manufacturing a solar cell according to an embodiment of the present invention will be described.

1 is a cross-sectional view of a solar cell according to an embodiment of the present invention.

Referring to FIG. 1, the solar cell 100 according to the present exemplary embodiment is positioned on the semiconductor substrate 10 and the first surface (hereinafter, “front surface”) of the semiconductor substrate 10 and includes a first conductivity type impurity. The reflector formed on the front surface of the semiconductor substrate 10 and the emitter layer 20, the back surface field layer 30 positioned on the second side (hereinafter referred to as “back side”) of the semiconductor substrate 10 and including the second conductivity type impurities. The barrier layer 22 and the first electrode 24, the passivation layer 32 and the second electrode 34 positioned on the rear surface of the semiconductor substrate 10 may be included. This will be described in more detail as follows.

The semiconductor substrate 10 may comprise various semiconductor materials, for example silicon containing a second conductivity type impurity. As the silicon, single crystal silicon or polycrystalline silicon may be used, and the second conductivity type impurity may be n-type, for example. That is, the semiconductor substrate 10 may be formed of single crystal or polycrystalline silicon doped with a Group 5 element such as phosphorus (P), arsenic (As), bismuth (Bi), and antimony (Sb)

When the semiconductor substrate 10 having the n-type impurity is used, the emitter layer 20 having the p-type impurity is formed on the entire surface of the semiconductor substrate 10 to form a pn junction. When the pn junction is irradiated with light, electrons generated by the photoelectric effect move toward the rear surface of the semiconductor substrate 10, are collected by the second electrode 34, and the holes move toward the front surface of the semiconductor substrate 10 1 electrode 24, respectively. Thereby, electric energy is generated.

In this case, holes having a slower moving speed than electrons may move to the front surface of the semiconductor substrate 10 instead of the rear surface, thereby improving conversion efficiency.

The front surface of the semiconductor substrate 10 may be textured to have irregularities in the form of a pyramid or the like. If unevenness is formed on the front surface of the semiconductor substrate 10 by such texturing and the surface roughness is increased, the reflectance of light incident through the front surface of the semiconductor substrate 10 may be lowered. Therefore, the amount of light reaching the pn junction formed at the interface between the semiconductor substrate 10 and the emitter layer 20 can be increased, thereby minimizing the optical loss. In addition, the back surface of the semiconductor substrate 10 may not be textured and may have a surface roughness smaller than that of the front surface. This is because the back surface of the semiconductor substrate 10 is etched after texturing the semiconductor substrate 10. This will be explained in more detail in the manufacturing method.

An emitter layer 20 having a first conductivity type impurity may be formed on the front surface of the semiconductor substrate 10. [ In the present embodiment, the emitter layer 20 is a first conductivity type impurity, and a p-type impurity such as boron (B), aluminum (Al), gallium (Ga), or indium (In) as a Group III element can be used.

The anti-reflection film 22 and the first electrode 24 are formed on the emitter layer 20 in front of the semiconductor substrate 10.

The antireflection film 22 may be formed substantially entirely on the entire surface of the semiconductor substrate 10 except for the portion where the first electrode 24 is formed. The antireflection film 22 reduces the reflectivity of light incident on the front surface of the semiconductor substrate 10 and immobilizes defects existing in the surface or bulk of the emitter layer 20. [

The amount of light reaching the pn junction formed at the interface between the semiconductor substrate 10 and the emitter layer 20 can be increased by lowering the reflectance of the light incident through the front surface of the semiconductor substrate 10. Accordingly, the short circuit current Isc of the solar cell 100 can be increased. In addition, it is possible to increase the open-circuit voltage (Voc) of the solar cell 100 by immobilizing defects present in the emitter layer 20 and removing recombination sites of minority carriers. The efficiency of the solar cell 100 can be improved by increasing the open-circuit voltage and the short-circuit current of the solar cell 100 with the anti-reflection film 22.

The anti-radiation film 22 may be formed of various materials. For example, the antireflection film 22 may be a single film selected from the group consisting of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, MgF ₂ , ZnS, TiO ₂ and CeO ₂ , Layer structure having a combination of at least two layers. However, the present invention is not limited thereto, and it goes without saying that the anti-reflection film 22 may include various materials.

The first electrode 24 may include various metals having excellent electrical conductivity. For example, the first electrode 24 may include silver (Ag) having excellent electrical conductivity. However, the present invention is not limited thereto, and may be formed of a single layer including a transparent conductive material, or may have a form in which a metal material layer (called a "bus bar" or a "finger electrode") is stacked on the transparent conductive material layer. .

In addition, a back surface field layer 30 including a second conductivity type impurity is formed on the back side of the semiconductor substrate 10 at a higher doping concentration than the semiconductor substrate 10. The rear electric field layer 30 may contribute to improving efficiency of the solar cell by minimizing rear recombination of electrons and holes. The back surface layer 30 may include phosphorus (P), arsenic (As), bismuth (Bi), antimony (Sb), and the like.

In addition, a passivation film 32 and a second electrode 34 may be formed on the rear surface of the semiconductor substrate 10.

The passivation film 32 may be formed substantially on the entire rear surface of the semiconductor substrate 10 except for the portion where the second electrode 34 is formed. This passivation film 32 can pass the defects present on the back surface of the semiconductor substrate 10 to remove recombination sites of minority carriers. As a result, the open voltage Voc of the solar cell 100 may be increased.

The passivation film 32 may be made of a transparent insulating material so that light can be transmitted. Therefore, light can be incident also on the rear surface of the semiconductor substrate 10 through the passivation film 32, thereby improving the efficiency of the solar cell 100. For example, the passivation film 32 may be formed of a silicon nitride film, a silicon nitride film including hydrogen, a silicon oxide film, a silicon oxynitride film, any single film selected from the group consisting of MgF ₂ , ZnS, TiO _2, and CeO ₂ or two or more films. It can have a combined multilayer structure. However, the present invention is not limited thereto, and it goes without saying that the passivation film 32 may include various materials.

The second electrode 34 may include various metals having excellent electrical conductivity. For example, the second electrode 34 may include silver (Ag) having excellent electrical conductivity and high reflectance. When silver having a high reflectance is used as the second electrode 34, light exiting to the rear surface of the semiconductor substrate 10 may be reflected and directed back into the semiconductor substrate 10, thereby increasing the amount of light used.

The second electrode 34 may be formed to have a larger width than the first electrode 24.

In the above description, the semiconductor substrate 10 has an n-type and the emitter layer 20 has a p-type, but the present invention is not limited thereto. Accordingly, the semiconductor substrate 10 may have a p-type, and the emitter layer 20 may have a n-type.

A method of manufacturing the solar cell 100 according to the present embodiment will be described in detail with reference to FIGS. 2, 3A to 3G, and FIG. 4. The above-described parts will not be described in detail, and will not be described in detail.

2 is a flowchart illustrating a method of manufacturing a solar cell according to an exemplary embodiment of the present invention, and FIGS. 3A to 3H are cross-sectional views illustrating a method of manufacturing a solar cell according to an exemplary embodiment of the present invention. 4 is a cross-sectional view showing the step of isolating a method of manufacturing a solar cell according to an embodiment of the present invention.

Referring to FIG. 2, the method of manufacturing a solar cell according to the present embodiment includes preparing a semiconductor substrate (ST10), a first doping step (ST20), a first activation heat treatment step (ST30), and isolating ( ST40), a second doping step (ST50), a second activation heat treatment step (ST60), forming an antireflection film and a passivation film (ST70), and forming an electrode (ST80).

First, as shown in FIG. 3A, in the preparing of the semiconductor substrate (ST10), the semiconductor substrate 10 having the second conductivity type impurities is prepared. In this case, the front and rear surfaces of the semiconductor substrate 10 may have irregularities by texturing. As texturing, wet or dry texturing can be used. The wet texturing can be performed by immersing the semiconductor substrate 10 in the texturing solution, and has a short process time. In dry texturing, the surface of the semiconductor substrate 10 is cut by using a diamond grill or a laser, so that irregularities can be formed uniformly, but the processing time is long and damage to the semiconductor substrate 10 may occur. As described above, the semiconductor substrate 10 can be textured in various ways in the present invention.

Subsequently, as shown in FIG. 3B, in the first doping step (ST20), the first layer 200 is formed by ion implanting first conductive impurities into the entire surface of the semiconductor substrate 10.

Even when the semiconductor substrate 10 is doped only by the cross-sectional doping, unwanted doping may occur on the side surface of the semiconductor substrate 10 to form the side doped portion 202. In the drawings and description, the side doped portion 202 is formed continuously on one side of the semiconductor substrate 10, but the present invention is not limited thereto. That is, the side doped portions 202 may be partially formed to be spaced apart from each other on the side surface of the semiconductor substrate 10.

Subsequently, as shown in FIG. 3C, in the first activation heat treatment step ST30, the first conductive dopant implanted in the first doping step ST20 is annealed by annealing the semiconductor substrate 10. When the first conductive impurity is implanted into the semiconductor substrate 10, the first conductive impurity implanted is not activated at a position other than the lattice position. Annealing the semiconductor substrate 10 in this state causes the first conductivity type impurities to be moved to the lattice position to be activated. By such activation, the emitter layer 20 is formed from the first layer 200 formed on the entire surface of the semiconductor substrate 10.

As described above, when the p-type impurity (for example, boron) is used as the first conductivity type impurity, the first activation heat treatment step ST30 may have a heat treatment temperature of 1000 to 1100 ° C. and a heat treatment time of 15 to 30 minutes. have. If the heat treatment temperature exceeds 1100 ° C., the semiconductor substrate 10 may be damaged and the cost may increase due to the high process temperature. If the heat treatment temperature is less than 1000 ° C., the p-type impurity is hardly activated sufficiently. If the heat treatment time exceeds 30 minutes, the process time may be long, and if the heat treatment time is less than 15 minutes, the p-type impurity may not be sufficiently activated.

Subsequently, as shown in FIG. 3D, in the step of isolating (ST40), the side surface of the semiconductor substrate 10 is etched to remove side doped portions formed at the semiconductor substrate 10 (reference numeral 202 of FIG. 3C). do. That is, the first conductivity type impurities remaining on the side surface of the semiconductor substrate 10 are unnecessarily removed.

In this case, etching for isolation may be performed by wet etching. Such wet etching can shorten the process time and improve productivity. More specifically, in the present embodiment, the step ST40 for isolating may be performed by an inline process. This can simplify the process further.

That is, referring to FIG. 4, the auto transport member 310 may be positioned on the frame 320, and the etching solution 330 may be accommodated between the auto transport members 310. The etching solution 330 may be positioned in the frame 320 such that only a part of the automatic transfer member 310 is locked.

In the present embodiment, the automatic transfer member 310 may have a variety of ways and structures, for example, it may be composed of a plurality of cylindrical rolls. As such, when the automatic transfer member 310 includes a cylindrical roll, the semiconductor substrate 10 is positioned on the automatic transfer member 310 in a state where the etching solution 330 is located in the space between the rolls.

That is, the semiconductor substrate 10 on which the first activation heat treatment step ST30 has been performed is transferred by the automatic transfer member 310 in a state in which the rear surface of the semiconductor substrate 10 is laid so as to be positioned on the automatic transfer member 310 side. do. Then, the rear surface and the side surface of the semiconductor substrate 10 are brought into contact with the etching solution 330 by the rotating automatic transfer member 310, and the rear surface of the semiconductor substrate 10 while being transferred by the automatic transfer member 310. This can be etched. In this case, since the etching solution 330 contacts the side surface of the semiconductor substrate 10 due to the surface tension, the side surface of the semiconductor substrate 10 may be etched together.

As described above, in the present exemplary embodiment, the rear surface of the semiconductor substrate 10 is etched along with the side surface of the semiconductor substrate 10 on which the side doped portion 202 is formed. Then, the unevenness (unevenness formed by texturing) on the rear side of the semiconductor substrate 10 can be removed, thereby reducing the area of the rear surface of the semiconductor substrate 10. Thereby, the back passivation characteristic of the semiconductor substrate 10 can be improved.

In this case, the etching thickness T1 of the rear surface of the semiconductor substrate 10 may be larger than the etching thickness T2 of the side surface or may be similar to the etching thickness T2 of the side surface. For example, an etching thickness T1 of the rear surface of the semiconductor substrate 10 and an etching thickness T2 of the side surface may be 2 μm to 3 μm. In the case of exceeding the above-described range, a process time for sufficiently etching the semiconductor substrate 10 may be increased, and the efficiency of the solar cell 100 may be reduced by reducing the area where photoelectric conversion occurs. If less than the above-described range it may be difficult to remove the unnecessary side doped portion 202 sufficiently.

The etching thicknesses T1 and T2 of the semiconductor substrate 10 may be adjusted by adjusting the speed of transferring the semiconductor substrate 10 on the automatic transfer member 310 to adjust the time immersed in the etching solution 330. have.

Subsequently, as shown in FIG. 3E, in the second doping step ST50, the second layer 300 is formed by ion implanting a second conductivity type impurity into the back surface of the semiconductor substrate 10.

Subsequently, as illustrated in FIG. 3F, in the second activation heat treatment step ST60, the second conductivity type impurity implanted in the second doping step ST50 may be activated by annealing the semiconductor substrate 10. When the second conductive impurity is ion-implanted into the semiconductor substrate 10, the implanted second conductive impurity is located at a position other than the lattice position and is not activated. Annealing the semiconductor substrate 10 in this state causes the second conductivity type impurities to be moved to the lattice position to be activated. By such activation, the back surface electric field layer 30 is formed from the second layer (reference numeral 300 of FIG. 3E) formed on the back surface of the semiconductor substrate 10.

As described above, when the n-type impurity (for example, phosphorus) is used as the first conductivity type impurity, the heat treatment temperature of the second activation heat treatment step ST60 may be 900 to 1000 ° C. and the heat treatment time may be 30 to 70 minutes. have. When the heat treatment temperature exceeds 1000 ° C., the semiconductor substrate 10 may be damaged and the cost may increase due to the high process temperature. If the heat treatment temperature is less than 900 ° C., the temperature is too high and n-type impurities are difficult to be sufficiently activated. If the heat treatment time exceeds 70 minutes, the process time may be long. If the heat treatment time is less than 30 minutes, the n-type impurity may not be sufficiently activated.

Subsequently, as shown in FIG. 3G, in the forming of the anti-reflection film and the passivation film (ST70), the anti-reflection film 22 is formed on the front surface of the semiconductor substrate 10, and the passivation film ( 32).

The antireflection film 22 and the passivation film 32 may be formed by various methods such as vacuum deposition, chemical vapor deposition, spin coating, screen printing, or spray coating.

Subsequently, as shown in FIG. 3H, in forming the electrode (ST80), the first electrode 24 and the rear electric field layer 30 (or the semiconductor substrate 10) are electrically connected to the second portion 20a. The second electrode 34 is electrically connected to the ()).

In the openings formed in the first passivation film 21 and the anti-reflection film 22, the first electrode 24 may be formed by various methods such as a plating method and a deposition method. An opening may be formed in the rear electric field layer 30, and the second electrode 34 may be formed in the opening by various methods such as a plating method and a deposition method.

Alternatively, the first and second electrode forming pastes are applied to the anti-reflection film 22 and the passivation film 32 by screen printing or the like, and then fire through or laser firing contact or the like is applied. It is also possible to form the first and second electrodes 32, 34 of the above-described shape. In this case, it is not necessary to carry out the step of forming the opening separately.

In the above description and drawings, the first and second electrodes 24 and 34 are formed after the anti-reflection film 22 and the passivation film 32 are formed. However, the present invention is not limited thereto. Accordingly, the antireflection film 22 may be formed and then the first electrode 24 may be formed, and then the passivation film 32 may be formed and then the second electrode 34 may be formed. Alternatively, the passivation film 32 may be formed, and then the second electrode 34 may be formed, and then the antireflection film 22 may be formed, followed by the first electrode 24. That is, the formation order of the antireflection film 22, the passivation film 32, the first electrode 24, and the second electrode 34 can be variously modified.

As described above, in the method of manufacturing a solar cell according to the present embodiment, side doping formed by etching side surfaces of the semiconductor substrate 10 between the first doping step ST20 and the second doping step ST50 is unnecessary. The portion 202 can be removed. As a result, an increase in reverse current that may occur when cross-sectional doping is performed on both surfaces of the semiconductor substrate 10 may be prevented. This will be described in more detail as follows.

In the related art, when single-sided doping is performed on both surfaces of a semiconductor substrate, it is considered that a problem such as an electrical short through the side of the semiconductor substrate does not occur. In practice, however, if the reverse current of a solar cell manufactured by doping each side on both sides is measured, the value is very high. This is expected to be due to some doping on the side of the semiconductor substrate even in the case of single-sided doping. In this case, when the reverse current is high, the saturation current of the solar cell is increased to reduce the current density and the open voltage. In addition, hot spots and heat generation may occur at the ends of the solar cell, which may greatly affect the lifetime and power.

On the other hand, in the present embodiment, the side surface of the semiconductor substrate 10 is etched unnecessarily between the first doping step ST20 by ion implantation, which is the cross-sectional doping, and the second doping step ST50 by ion implantation, which is the cross-sectional doping. The formed side doped portion 202 may be removed. Therefore, unnecessary electric short circuit can be prevented, so that reverse current and saturation current can be reduced, thereby improving current density and open voltage. In addition, hot spots and heat generation that may occur at the end of the solar cell 100 can be minimized. That is, the efficiency of the solar cell 100 can be improved and its life can be extended.

In the present exemplary embodiment, the back side of the semiconductor substrate 10 may also be etched together in the step ST40 of etching and isolating the side surface of the semiconductor substrate 10, thereby improving passivation characteristics. That is, the characteristics of the solar cell 100 can be improved while simplifying the process.

In addition, in the related art, an isolation portion is formed by using a laser on the side or the back side of the semiconductor substrate 10 for isolation, and thus, the light receiving surface of the semiconductor substrate 10 may be damaged or the light receiving area may be reduced, thereby reducing efficiency. In the present exemplary embodiment, problems such as damage to the semiconductor substrate 10 and reduction in the light receiving area can be prevented by etching the side surfaces.

In addition, in the present exemplary embodiment, the first activation heat treatment step ST30 is performed after the first doping step ST20, and the second activation heat treatment step ST60 is performed after the second doping step ST50. That is, the activation heat treatment for the first conductivity type impurity and the activation heat treatment for the second conductivity type impurity are performed in separate steps. According to the type of impurities, various process conditions such as temperature and time may be different in the activation step. In this embodiment, the activation heat treatment for the first and second conductivity type impurities is performed separately, thereby the characteristics of each conductivity type impurity. The activation can be carried out at an optimized stage according to.

More specifically, the heat treatment time in the first activation heat treatment step ST30 for activating the first conductivity type impurity that is the p-type impurity is the second activation heat treatment step for activating the second conductivity type impurity that is the n-type impurity (ST60). The heat treatment time can be longer than. Further, the heat treatment temperature in the first activation heat treatment step ST30 for activating the first conductivity type impurity that is the p-type impurity is the heat treatment in the second activation heat treatment step ST60 for activating the second conductivity type impurity that is the n-type impurity It can be made larger than temperature. As a result, the characteristics of the emitter layer 20 and the rear electric field layer 30 may be further improved, thereby improving efficiency of the solar cell 100.

In addition, in the state in which the emitter layer 20 is formed by activating the first conductivity type impurity by the first activation heat treatment step ST30, the step ST20 is performed. As a result, problems such as loss of the first conductivity type impurity ion-implanted into the semiconductor substrate 10 in the isolation step ST20 can be prevented, thereby improving stability in the manufacturing process.

In the above description, the emitter layer 20 and the back surface field layer 30 have a uniform doping concentration. However, the present invention is not limited thereto, and at least one of the emitter layer 20 and the rear electric field layer 30 may have a selective structure.

That is, as shown in FIG. 5, the emitter layer 20 may be formed adjacent to the anti-reflection film 22 between the first electrodes 24, the first electrode 20, and the first electrode 24. It may include a second portion 20b formed in contact and doped at a higher doping concentration than the first portion 20a and having a lower resistance than the first portion 20a.

Then, the efficiency of the solar cell 100 may be improved by implementing a shallow emitter in the first portion 20a corresponding to the first electrode 24 to which light is incident. In addition, the contact resistance with the first electrode 24 can be reduced in the second portion 20b in contact with the first electrode 24. That is, the emitter layer 20 of the present embodiment may have a selective emitter structure to maximize the efficiency of the solar cell.

In addition, the rear electric field layer 30 is formed in contact with the first portion 30a formed between the second electrodes 34 and the second electrode 34 and has a higher doping concentration than the first portion 30a. It may include a second portion 30b that is doped and has a lower resistance than the first portion 30a.

Then, while effectively preventing the recombination of electrons and holes in the first portion 30a of the rear electric field layer 30, the second portion 30b has a relatively small resistance to provide contact resistance with the second electrode 34. Can be reduced. Therefore, the loss due to the recombination of electrons and holes is reduced, and at the same time, the ability to transfer the electrons or holes generated by the photoelectric effect to the second electrode 34 is further improved, thereby further improving the efficiency of the solar cell. .

The emitter layer 20 and the rear electric field layer 30 of this optional structure may be formed by various methods. For example, when the impurities are doped, impurities are doped at a relatively high doping concentration with respect to the portions corresponding to the second portions 20b and 30b by using a comb-shaped mask or the like, and the portions corresponding to the first portions 20a and 30a. Impurities can be doped with a relatively small doping concentration. Alternatively, an impurity doping process may be additionally performed only on the second portions 20b and 30b to form an emitter layer 20 or a backside electric field layer 30 having a selective structure.

Hereinafter, the present invention will be described in more detail with reference to examples of the present invention. However, the following experimental examples are merely illustrative of the present invention and the present invention is not limited to the following experimental examples.

Experimental Example

an n-type semiconductor substrate was prepared. The first doping step was performed by doping boron B on the entire surface of the semiconductor substrate by ion implantation. And annealing at 1000 ℃ 20 minutes to activate the boron to form an emitter layer. In an inline wet etching process, an isolation step of etching the side and rear surfaces of the semiconductor substrate by 2.2 μm was performed. Thereafter, a second doping step was performed by doping phosphorus (P) on the rear surface of the semiconductor substrate by an ion implantation method. Annealing at 900 ° C. for 50 minutes to activate phosphorus to form a backside field layer.

An antireflection film was formed on the entire surface of the semiconductor substrate, and a passivation film was formed on the rear surface of the semiconductor substrate. The solar cell was completed by forming a first electrode electrically connected to the emitter layer and a second electrode electrically connected to the rear field layer. Three solar cells were prepared in the same manner.

Comparative Example

A solar cell was manufactured in the same manner as in Experimental Example, except that the step of isolating was not performed.

The open circuit voltage (Voc), the current density (Jsc), the charge density (FF), the efficiency, the reverse current (Irev2) of the solar cells manufactured according to the experimental and comparative examples were measured and the results are shown in Table 1.

Open-circuit voltage
[mV] Current density
[mA / cm2] Density
[%] efficiency
[%] Reverse current
[A] Experimental Example 0.6370 38.39 76.07 18.60 2.10 0.6353 38.36 77.20 18.82 2.81 0.6397 38.45 76.79 18.88 2.56 Comparative Example 0.644 37.62 76.78 18.61 12.26

 Referring to Table 1, it can be seen that the reverse current value of the experimental example is significantly lower than the reverse current value of the comparative example, whereby it can be seen that the experimental example has a higher efficiency than the comparative example.

That is, in the experimental example, the first doping step, the first activation heat treatment step, the isolation step, the second doping step, and the second activation heat treatment step may be performed in order to prevent unnecessary electric short circuits, thereby reducing reverse current and improving efficiency. It can be seen that it can be improved.

Features, structures, effects and the like according to the above-described embodiments are included in at least one embodiment of the present invention, and the present invention is not limited to only one embodiment. Further, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified in other embodiments by those skilled in the art to which the embodiments belong. Therefore, it should be understood that the present invention is not limited to these combinations and modifications.

100: Solar cell
10: semiconductor substrate
20: Emitter layer
30: rear front layer
310: automatic transfer member
320: frame
330: etching solution

Claims (13)

Preparing a semiconductor substrate having a first surface and a second surface opposite to each other, and side surfaces intersecting the first surface and the second surface;
First doping to ion implant a first conductivity type impurity into the first surface of the semiconductor substrate;
A first activation heat treatment step of activating the first conductivity type impurity;
Etching the side surface of the semiconductor substrate to remove the first conductivity type impurities remaining in the corresponding portion;
A second doping for ion implanting a second conductivity type impurity into the second surface of the semiconductor substrate; And
A second activation heat treatment step of activating the second conductivity type impurity
Wherein the method comprises the steps of: The method of claim 1,
The first activation heat treatment step and the second activation heat treatment step is a manufacturing method of a solar cell having different process conditions. 3. The method of claim 2,
The first activation heat treatment step and the second activation heat treatment step is a method of manufacturing a solar cell different from each other at least one of the heat treatment temperature and the heat treatment time. The method of claim 1,
The first conductivity type impurity includes a p type impurity,
The second conductivity type impurity includes n type impurity,
The manufacturing method of the solar cell in which the said semiconductor substrate contains n type impurity. 5. The method of claim 4,
And a heat treatment temperature of the first activation heat treatment step is higher than a temperature of the second activation heat treatment step. 5. The method of claim 4,
And a heat treatment time of the first activation heat treatment step is longer than a heat treatment time of the second activation heat treatment step. 5. The method of claim 4,
In the first activation heat treatment step, the heat treatment temperature is 1000 ~ 1100 ℃ and the heat treatment time is 15 ~ 30 minutes,
The second activation heat treatment step is a solar cell manufacturing method of the heat treatment temperature is 900 ~ 1000 ℃ and heat treatment time 30 ~ 70 minutes. The method of claim 1,
And in the isolating step, etching the second surface together with the side surface of the semiconductor substrate. 9. The method of claim 8,
A method of manufacturing a solar cell having an etching thickness of 2 to 3㎛ in the isolation step. 9. The method of claim 8,
The isolating step is a method of manufacturing a solar cell is performed by a wet etching method. The method of claim 10,
The isolating step is a solar cell manufacturing method performed by an inline (inline) process. The method of claim 1,
The isolating step is performed while moving on the automatic transfer member with the rear surface of the semiconductor substrate located on the automatic transfer member side. The method of claim 12,
The automatic transfer member includes a plurality of rolls manufacturing method of a solar cell.

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