KR20130108053A - Integrated circuit device - Google Patents

Abstract

PURPOSE: An integrated circuit device is provided to reduce the number of test pads and the size of test circuits. CONSTITUTION: An integrated circuit device (100) includes internal circuits (3-5), a test pad for control (11) and a test mode identification circuit (12). The test pad for control inputs a test control signal indicating a test mode which is a test type performed in the internal circuits. The mode identification circuit identifies a test mode based on the test control signal. The test mode identification circuit performs different operations in the internal circuits according to each test mode. While the internal circuits are being tested, a plurality of test signals which are produced in the internal circuits are sequentially outputted to a test pad for monitoring by test signal output selection circuit (13). [Reference numerals] (1) Input pad; (11) Test pad for control; (12) Test mode identification circuit; (13) Test signal output selection circuit; (14) Test pad for monitoring; (2) Input circuit; (3) Signal delivery circuit (internal circuit); (4) Logic circuit (internal circuit); (5) Function circuit (internal circuit); (6) Output circuit; (7) Output pad

Description

[0001] INTEGRATED CIRCUIT DEVICE [0002]

The present invention relates to an integrated circuit device mounted with a test circuit.

Generally, in the manufacturing process of an integrated circuit device, a test is performed to determine its internal logic and its characteristics. Therefore, many integrated circuit devices are provided with a pad (test pad) for measuring internal logic and device characteristics, and a test circuit that is useful for the test.

In a conventional integrated circuit device, a test pad and a test circuit are provided for each measurement target in the integrated circuit device. However, in that case, the number of test pads and the scale of the test circuit increase in proportion to the number of measurement points for testing. As a result, the circuit scale mounted on the integrated circuit device becomes large, the consumption current increases, and the cost of the product increases.

For example, the following Patent Document 1 discloses a technique in which a static current flowing between a power supply terminal and a ground terminal (a current flowing in a state in which no signal is applied to an input terminal) is measured via two test pads, A method of judging whether or not there is a problem is proposed. According to this method, the number of test pads and the size of the test circuit can be reduced, and the circuit can be judged in a short time.

Japanese Patent Application Laid-Open No. 61-82456

In the technique of Patent Document 1, only the static current is measured, and a function test for checking the internal logic or device characteristics of the integrated circuit is not performed. Therefore, it is not possible to specify the cause of the specific defect or the defective portion of the integrated circuit device. There is also a case where a defect in the integrated circuit device does not affect the quiescent current, and there is a possibility that the both parts are judged to be erroneous.

An object of the present invention is to provide an integrated circuit device capable of measuring internal logic and device characteristics of an integrated circuit and suppressing an increase in the number of test pads and the scale of a test circuit required The purpose is to provide.

The integrated circuit device according to the present invention includes an internal circuit and an operation circuit for identifying the test mode based on a test control signal indicating a test mode which is a type of test performed in the internal circuit, And a test mode identification circuit for performing the test mode identification circuit.

According to the present invention, the test mode identification circuit identifies the test mode, and the internal circuit performs the operation in accordance with the test mode. It is possible to reduce the scale of the test circuit because various tests can be performed by changing the operation of the internal circuit according to the test mode instead of installing the test circuit for each test mode.

1 is a block diagram showing a configuration of an integrated circuit device according to the first embodiment.
2 is a diagram showing a first configuration example of a test mode identification circuit included in the integrated circuit device according to the first embodiment.
3 is a diagram showing a second configuration example of a test mode identification circuit included in the integrated circuit device according to the first embodiment.
4 is a diagram showing a third configuration example of a test mode identification circuit included in the integrated circuit device according to the first embodiment.
5 is a diagram showing an example of the circuit configuration of the T flip-flop.
6 is a diagram showing an operation sequence of a T flip-flop.
7 is a diagram showing a first configuration example of a test signal output selection circuit included in the integrated circuit device according to the first embodiment.
8 is a diagram showing a second configuration example of a test signal output selection circuit included in the integrated circuit device according to the first embodiment.
9 is a diagram showing an operation sequence of the test signal output selection circuit.
10 is a block diagram showing a first modification example of the integrated circuit device according to the first embodiment.
11 is a block diagram showing a second modification example of the integrated circuit device according to the first embodiment.
12 is a block diagram showing a configuration of an integrated circuit device according to the second embodiment.
13 is a block diagram showing the configuration of the integrated circuit device according to the third embodiment.
14 is a diagram showing a configuration example of a test mode identification circuit included in the integrated circuit device according to the third embodiment.
15 is a diagram for explaining the operation of the test mode identification circuit according to the third embodiment.
16 is a diagram showing a configuration of a level shift circuit capable of performing a static characteristic test by controlling a test mode signal.
17 is a diagram showing the configuration of the test signal output selector circuit according to the third embodiment.
18 is a timing chart showing a sequence of a static characteristic test according to the third embodiment.
19 is a diagram for explaining a method of obtaining the input / output characteristics of the inverter by the positive characteristic test.
20 is a diagram showing a configuration of a level shift circuit capable of performing a dynamic characteristic test by control of a test mode signal.
21 is a timing chart showing a sequence of the dynamic characteristic test in the third embodiment.
22 is a diagram showing an example of an internal power supply circuit capable of performing a stress test of an internal circuit by control of a test mode signal.
23 is a diagram showing an example of an internal power supply circuit (simple regulator) in which a stress test of an internal circuit can be performed by controlling a test mode signal.
24 is a diagram showing an example of an internal power supply circuit (simple regulator) in which a stress test of an internal circuit can be performed by controlling a test mode signal.
25 is a diagram showing an example of a low-current circuit.
26 is a timing chart showing an operation sequence of the internal power supply circuit when transitioning from the normal operation mode to the third test mode (stress test).
27 is a timing chart showing a sequence of a normal operation mode in the third embodiment.
28 is a diagram showing an example of a test flow of the integrated circuit device according to the third embodiment.

≪ Embodiment 1 >

1 is a block diagram showing the configuration of an integrated circuit device 100 according to Embodiment 1 of the present invention. The integrated circuit device 100 has an input pad 1 to which an input signal is applied and an input circuit 2 for supplying an input signal applied to the input pad 1 to an internal circuit. 1, a signal transfer circuit 3, a logic circuit 4, and a functional circuit 5 (protection circuit, etc.) are shown as an example of an internal circuit included in the integrated circuit device 100. FIG. The integrated circuit device 100 is also configured such that the output signal of the logic circuit 4 is output from the output pad 7 through the output circuit 6. [ Hereinafter, the signal transfer circuit 3, the logic circuit 4, and the functional circuit 5 may be collectively referred to as " internal circuits 3 to 5 ".

The integrated circuit device 100 according to the present embodiment is a circuit (test circuit) for testing the internal circuits 3 to 5 and includes a control test pad 11, a test mode identification circuit 12, An output selection circuit 13, and a test pad 14 for a monitor.

In the control test pad 11, a test control signal indicating a test mode, which is a type of test performed on the internal circuits 3 to 5, is inputted. The test mode identification circuit 12 is connected between the internal circuits 3 to 5 and the control test pad 11 and identifies the test mode based on the test control signal input to the control test pad 11. [ Then, the control test pad 11 outputs a control signal for causing the internal circuits 3 to 5 to perform the operation in accordance with the test mode.

The monitor test pad 14 is a pad for observing signals (test signals) appearing at predetermined positions of the internal circuits 3 to 5 at the time of testing. The test signal output selecting circuit 13 is connected between the internal circuits 3 to 5 and the test test pad 14 for monitoring and selects among a plurality of test signals appearing in the internal circuits 3 to 5 The test signal to be output to the test pad 14 is selected. Moreover, the test signal output selection circuit 13 operates to sequentially switch test signals to be output to the monitor test pads 14 with time. Since the data stream including a plurality of test signals can be observed by one test pad 14 by the operation of the test signal output selection circuit 13, the number of monitor test pads 14 is At least.

[Configuration example of test mode identification circuit]

2 is a diagram showing a first configuration example of a test mode identification circuit 12 included in the integrated circuit device 100 according to the first embodiment. The test mode identification circuit 12 of FIG. 2 identifies the test mode based on the magnitude (voltage value) of the test control signal input from the control test pad 11, Is a level trigger circuit consisting of a mode identification logic circuit (124).

The comparators 121, 122 and 123 compare the magnitude (voltage value) of the test control signal input from the control test pad 11 with different reference voltages (threshold voltages) V _ref1 , V _ref2 and V _ref3 V _ref1 < V _ref2 < V _ref3 ). The test mode identification logic circuit 124 determines a test mode based on each output of the comparators 121, 122 and 123 and outputs a control signal for causing the internal circuits 3 to 5 to perform operations in accordance with the test mode. . As described above, the scale of the test circuit can be reduced by changing the operation of the internal circuits 3 to 5 in accordance with the test mode, instead of providing a test circuit for each test mode.

Since the test mode identification circuit 12 identifies the test mode based on the size of the test control signal input from the control test pad 11, even if the test mode is 2 or more, Dogs are enough. Therefore, the number of control test pads 11 can be reduced. In general, as the miniaturization of the process progresses, the size of the protection circuit provided at the next stage of the pad increases, so that suppression of the number of input pads generally leads to reduction in circuit scale.

3 is a diagram showing a second configuration example of the test mode identification circuit 12 included in the integrated circuit device 100 according to the first embodiment. The test mode identification circuit 12 in FIG. 3 is also a level trigger circuit for identifying the test mode based on the magnitude of the test control signal input from the control test pad 11, like the circuit in FIG. 2, 122a and 123a and a test mode identification logic circuit 124. [

By setting the threshold voltages of the inverters 121a, 122a, and 123a to different values V _ref1 , V _ref2 , and V _ref3 , the same operation as in the configuration of FIG. 2 is possible, and the same effect can be obtained. Moreover, since the inverter has a simpler structure than the comparator and does not need to supply the reference voltages V _{ref1 to} V ref3, the circuit scale of the test mode identification circuit 12 can be reduced as _{compared with} the configuration of Fig.

4 is a diagram showing a third configuration example of the test mode identification circuit 12 included in the integrated circuit device 100 according to the first embodiment. The test mode identification circuit 12 of FIG. 4 includes a counter circuit for counting the edges (rising or falling) of a test control signal input from the control test pad 11, and a test mode And an decoder circuit 127 for identifying the edge trigger circuit. When the test mode identification circuit 12 is used as an edge trigger circuit, the test control signal supplied from the control test pad 11 becomes a pulse signal.

The counter circuit included in the test mode identification circuit 12 of FIG. 4 is composed of two stages of T flip-flops 125 and 126 (reset priority type). The decoder circuit 127 determines the test mode based on the output signals of the T flip-flops 125 and 126 and outputs to the internal circuits 3 to 5 a control signal for performing the operation in accordance with the test mode. The decoder circuit 127 may be a logic circuit (test mode identification logic circuit) that operates in the same way.

5 is a diagram showing an example of the circuit configuration of the T flip-flop (TFF). In this example, the T flip-flop is configured by using four AND gates 201 to 204, one inverter 205, and two RS flip-flops 206 and 207. 6 is a timing chart showing the operation sequence of the T flip-flop in Fig. As shown in Fig. 6, the signal level of the output terminal (Q terminal) of the T flip-flop of Fig. 5 changes from the falling (L (Low) level of the trigger signal input to the T terminal of the T flip- H (High) level). The signal level of the Q terminal is reset to the L level in accordance with the rise (change from H level to L level) of the reset signal input to the reset terminal (Rst terminal).

Here, it is assumed that the T flip-flops 125 and 126 of the test mode identification circuit 12 of FIG. 4 operate to invert the level of the Q terminal in accordance with the falling of the level of the T terminal. In this case, the signal level of the Q terminal of the first-stage T flip-flop 125 is inverted every time the test control signal falls, and the signal level of the Q terminal of the second-stage T flip- Flop 125 is inverted every time the signal level of the Q terminal of the flip-flop 125 falls. Therefore, the output signal of the counter circuit formed by the T flip-flops 125 and 126 becomes a signal indicating the count value of 2-bit binary numbers. The decoder circuit 127 determines a test mode from the binary count values output from the T flip-flops 125 and 126 and outputs a control signal to the internal circuits 3 to 5 to perform the operation in accordance with the test mode Output.

As described above, the test mode identification circuit 12 identifies the test mode based on the number of pulses (count value) of the test control signal input from the control test pad 11, so that even when the test mode is two or more, (11) is sufficient. Therefore, the number of the control test pads 11 can be reduced like the level-triggered test mode identification circuit 12 (Figs. 2 and 3).

In addition, the test mode identification circuit 12 of the edge trigger system has an advantage that it is hardly influenced by the difference of signal voltages. Moreover, by increasing the number of bits of the counter circuit, it is also possible to simply increase the number of test modes to be discriminated.

[Configuration example of test signal output selection circuit]

7 is a diagram showing a first configuration example of a test signal output selection circuit 13 provided in the integrated circuit device 100 according to the first embodiment. As described above, the test signal output selection circuit 13 selects test signals to be output to the monitor test pads 14 among a plurality of test signals appearing in the internal circuits 3 to 5 at the time of testing, And sequentially switches test signals to be output to the monitor test pads 14 with time.

7 includes a counter circuit composed of two stages of T flip-flops 131 and 132 (reset priority type), and a plurality of test signals in accordance with an output signal of the counter circuit. And a multiplexer 133 for selectively outputting the selected test signal to the monitor test pad 14.

The counter circuit of the test signal output selection circuit 13 counts the edge (rising or falling) of the trigger signal T_IN input to its input terminal (T terminal of the T flip flop 131 at the initial stage). The trigger signal may be a pulse signal of a predetermined period, a signal directly input from the pad, or a signal generated by using the internal circuits 3 to 5.

Four test signals IN0 to IN4 output from the internal circuits 3 to 5 are input to the multiplexer 133. The test signals IN0 to IN4 are input to the multiplexer 133 in accordance with the output signal (count value of 2-bit binary number) And outputs them to the test pad 14 for monitoring. As a result, a stream of the test signals IN0 to IN4 collected at one time and having a high transfer rate is output to the test pad 14 for monitoring.

As described above, since the stream including the data of the plurality of test signals IN0 to IN4 can be observed with one test test pad 14, the number of test test pads 14 can be reduced. In general, when the process is miniaturized, the size of the protection circuit provided at the front end of the output pad is also increased. Therefore, suppression of the number of pads generally leads to reduction in circuit scale.

8 is a diagram showing a second configuration example of the test signal output selection circuit 13 provided in the integrated circuit device 100 according to the first embodiment. In the example shown in Fig. 7, the means for selecting one of the test signals IN0 to IN4 according to the output signal of the counter circuit and outputting it to the test pad 14 for monitoring is the multiplexer 133 which is a digital element, The means may be constituted by using four analog switches 135 to 138 as shown in Fig. In this case, the analog switches 135 to 138 are controlled by the decoder circuit 134 to which the output signal of the counter circuit is inputted.

9 is a timing chart showing the operation sequence of the test signal output selector circuit 13 of Fig. The output signal Q1 of the T flip flop 131 at the first stage of the counter circuit is inverted every falling of the trigger signal T_IN and the output signal Q2 of the T flip flop 132 at the second stage is inverted at the falling edge of the output signal Q1 The output signals Q1 and Q2 of the counter circuit become count values of 2-bit binary numbers. The output signals Z0 to Z4 of the decoder circuit 134 become H levels in order in accordance with the count value. The output signals Z0 to Z4 of the decoder circuit 134 operate to select signals to be output to the monitor test pad 14, and these signals are hereinafter referred to as &quot; selection signals &quot;.

The analog switches 135 to 138 are turned on when the selection signals Z0 to Z4 output from the decoder circuit 134 are at the H level. Therefore, the test signal IN1 is outputted in the period for which Z0 = H in the monitor test pad 14, the test signal IN1 is outputted in the period of Z1 = H, the test signal IN2 is outputted in the period of Z2 = H, The test signal IN3 is outputted in the period where Z3 = H. That is, every time the trigger signal T_IN falls, the monitor period of the test signal IN0, the monitor period of the test signal IN1, the monitor period of the test signal IN2, the monitor period of the test signal IN2, .

Even when the test signal output selection circuit 13 is configured as shown in Fig. 8, the same effect as that of Fig. 7 can be obtained. 8, since the test signals IN0 to IN4 are directly outputted (as an analog signal) to the test test pad 14 for monitoring, the voltage values and the current values of the test signals IN0 to IN4 are supplied to the monitor test pad 14, There is an advantage that it is possible to measure it by way of.

[Modification example of integrated circuit device]

In the integrated circuit device 100 of Fig. 1, the control test pad 11 to which the test control signal is input is provided independently of the pad other than the test application, but may be used as another pad. If the control test pad 11 is also used as another pad, the circuit scale and circuit area of the integrated circuit device 100 can be further reduced.

For example, Fig. 10 shows an example in which the control test pad 11 is also used as the input pad 1. Fig. In Fig. 10, the input pad 1 is also connected to the test mode identification circuit 12, and it can be used as a control test pad 11 at the time of testing.

11 shows an example in which the control test pad 11 is also used as a signal monitor pad other than the test application. 11, the control test pad 11 is also connected to the internal power supply circuit 8 so that it can be used as a pad for monitoring the output of the internal power supply circuit 8 except at the time of testing.

&Lt; Embodiment 2 >

12 is a block diagram showing the configuration of the integrated circuit device 100 according to the second embodiment. In this integrated circuit device 100, the control test pad 11 is omitted, and the output signal of the functional circuit 5 is inputted to the test mode identification circuit 12. [

In the integrated circuit device 100 (Fig. 1) of the first embodiment, the test control signal is externally input via the control test pad 11. However, the test control signal may not necessarily be externally input, It may be generated by using the functional circuit 5 attached to the internal circuit at the time of testing.

Examples of the function circuit 5 include a power supply voltage drop prevention circuit (UV protection circuit), a power supply start / stop circuit, a short circuit protection circuit, an overheat protection circuit, and the like. For example, the power supply level is intentionally changed to operate the protection function of the functional circuit 5, and various protection signals are input to the test mode identification circuit 12 as a test control signal. In this case, the test mode identification circuit 12 discriminates the test mode based on the combination of the protection signal as the test control signal, and causes the internal circuits 3 to 5 to perform the operation in accordance with the test mode. Further, the test signal output selection circuit 13 selects the test signal to be the measurement target according to the test mode, and sends it to the test pad 14 for monitoring.

According to the present embodiment, since the control test pad 11 can be omitted, the circuit scale and the area of the integrated circuit device 100 can be further reduced.

&Lt; Embodiment 3 >

Embodiment 3 shows a specific example in which the present invention is applied to an integrated circuit device having a level shift circuit as an internal circuit. 13 is a block diagram showing the configuration of the integrated circuit device 100 according to the third embodiment.

The integrated circuit device 100 includes a Schmitt circuit 22 as an input circuit for receiving a signal input to the input pad 1, a pulse generating circuit 23 as a signal transmitting circuit, a pulse generating circuit 23 And a power-on reset circuit (hereinafter referred to as &quot; UV &amp; POR protection circuit &quot;) 25 as a functional circuit .

The output signal of the test mode identification circuit 12 is supplied to the pulse generation circuit 23 and the internal power supply circuit 8. At the time of the test, the test mode identification circuit 12 controls the pulse generation circuit 23 and the internal power supply circuit 8 to perform the operation in accordance with each test mode.

A test signal appearing in the level shift circuit 24 is input to the test signal output selection circuit 13 during the test. The test signal output selection circuit 13 is controlled by a signal generated by the UV / POR protection circuit 25 (details will be described later).

14 is a diagram showing a configuration example of the test mode identification circuit 12 according to the present embodiment. This test mode identification circuit 12 is a level trigger circuit configured by using comparators 121 to 123 as in FIG. The test mode identification logic circuit 124 is composed of AND gates 1241 and 1242 and inverters 1243 to 1246 and outputs test mode signals TM1 to TM3 for indicating test modes. Here, the reference voltages V _{ref1 to} V _ref3 are also _referred to as V _ref1 < V _ref2 < V _ref3 . And the voltage level of the test control signal input from the control test pad 11 is VTP.

15 is a diagram showing the relationship between the voltage level VTP of the test control signal and the levels of the test mode signals TM1 to TM3 output from the test mode identification circuit 12. In Fig. And VTP <V _ref1, when the all of the output is at the L level of the comparator (121, 122, 123), and L = TM1, TM2 = L, TM = L. When V _ref1 <V _TP <V _ref2 and only the output of the comparator 121 is at the H level, TM1 = H, TM2 = L, and TM = L. When _Vref2 <VTP < _Vref3 and the outputs of the comparators 121 and 122 are at H level, TM1 = L, TM2 = H, TM = L. When V _ref3 <VTP and all outputs of the comparators 121, 122, and 123 are at H level, TM1 = L, TM2 = L, and TM = H.

The operation mode of the internal circuit of the integrated circuit device 100 switches according to the test mode signals TM1 to TM3. Specifically, when all of the test mode signals TM1 to TM3 are at the L level, the normal operation mode in which the internal circuit performs normal operation is obtained. When the test mode signal TM1 is at the H level, the first test mode for performing the operation for the positive characteristic test is obtained. When the test mode signal TM2 is at the H level, the second test mode for performing the operation for the dynamic characteristic test is obtained. When the test mode signal TM3 is at the H level, the third test mode for performing the stress test operation is obtained. At this time, the test of the integrated circuit device 100 includes a normal operation test for testing whether or not the normal operation is normally performed, but the normal operation test may be performed in the normal operation mode.

16 is a diagram showing a configuration of a level shift circuit included in the integrated circuit device 100 according to the third embodiment. 16 includes a portion corresponding to the pulse generating circuit 23 and a portion corresponding to the level shift circuit 24, and the entirety including both of them is referred to as a &quot; level shift circuit LS &quot;.

The level shift circuit LS in FIG. 16 is configured to be able to perform the positive characteristic test when the test mode signal TM1 becomes the H level. In the normal operation mode (TM1 = L), the pulse signal is generated at the input terminal IN_A of the input terminal IN of the level shift circuit LS (part of the pulse generator circuit 23). However, in the first test mode (TM1 = H), a signal having the same waveform as the input signal IN_A is generated at the input terminal of the level shift circuit LS. That is, in the first test mode, the signal level of each node of the level shift circuit 24 can be fixed to a value corresponding to the level of the input signal IN_A, and the positive characteristic test of the level shift circuit LS can be performed.

17 is a diagram showing a configuration example of the test signal output selector circuit 13 according to the third embodiment. The test signal output selection circuit 13 shown in Fig. 17 is the same as that of Fig. In this embodiment, as the trigger signal T_IN and the reset signal Rst_IN for specifying the operation of the counter circuit (T flip-flop 131, 132) of the test signal output selection circuit 13, the UV (Power-down) detection circuit 251 and a POR (power-on reset) detection circuit 252 are used. An input signal and an output signal of an internal element (element to be measured) in the level shift circuit LS are input to the analog switches 135 to 138.

At this time, the UV detection circuit 251 monitors the voltage (VBS = VB-VS) between the VB terminal and the VS terminal of the level shift circuit LS. When the voltage VBS is lower than a predetermined value (UV trip voltage) The output signal (UV detection signal) of the detection circuit 251 becomes H level. Further, the output signal (power-on reset signal) of the POR detection circuit 252 is at the H level at the start of the power supply, and then becomes the L level when the power supply voltage reaches the predetermined value or more.

Here, an example in which the elements to be measured are inverters INV1 and INV2 at the output stage of the level shift circuit LS in Fig. 16 is shown. In this case, the output signal VMIN0 of the inverter INV1 is input to the analog switch 135, the output signal VMIN1 of the inverter INV2 is input to the analog switch 136, the input signal VMIN2 of the inverter INV1 is input to the analog switch 137, The input signal VMIN3 of INV2 is input. The test signal output selection circuit 13 sequentially outputs the four measurement target signals VMIN0 to VMIN4 in total to the test pad 14 for monitoring in synchronization with the trigger signal T_IN.

Fig. 18 is a timing chart showing a sequence of the static characteristics test in the present embodiment. When the positive characteristic test is performed, the voltage level VTP of the test control signal is set to V _ref1 <VTP <V _ref1 (time t10). In this case, the test mode signal TM1 becomes H level, and the internal circuit of the integrated circuit device 100 becomes the first operation mode.

As described above, in the level shift circuit LS of FIG. 16, when the test mode signal TM1 is at the H level, a signal having the same waveform as that of the input signal IN_A is generated at its input terminal (part of the pulse generating circuit 23) (See VG_A in Fig. 18).

In the positive characteristic test, the voltage (VBS = VB-VS) between the VB terminal and the VS terminal of the level shift circuit LS is fixed and the voltage (VS voltage) of the VS terminal is continuously changed, Measurement of VMIN4 is performed. As shown in Fig. 18, when the voltage of the VS terminal is gradually increased, the input signals VMIN2 and VMIN3 of the inverters INV1 and INV2 are gradually lowered and the output signals VMIN0 and VMIN1 of the inverters INV1 and INV2 become H Level.

For example, as shown in Fig. 19, when the curve of the dependency of the input signal VMIN2 of the inverter INV1 on the VS voltage and the curve of the dependency of the output signal VMIN0 on the VS voltage are obtained and the both are combined, You can get a curve. The same is true for the inverter INV2. The resistance between the resistors RH1 and RH2 can also be estimated by simultaneously measuring the current between the VS terminal and the VB terminal.

In this embodiment, the UV detection signal output from the UV detection circuit 251 of the UV · POR protection circuit 25 is input to the test signal output selection circuit 13 as the trigger signal T_IN. The UV detection circuit 251 sets the trigger signal T_IN (UV detection signal) to H level when the voltage VBS between the VB terminal and the VS terminal is lower than the UV trip voltage. In the present embodiment, the signal outputted to the monitor test pad 14 is switched using this.

18, since the selection signal Z0 output from the decoder circuit 134 of the test signal output selection circuit 13 (Fig. 17) is at the H level, the monitor test pads 14 ) Is the output signal VMIN0 of the inverter INV1.

After the measurement of VMIN0 is completed, the voltage VBS between the VB terminal and the VS terminal is lower than the UV trip voltage, so that the trigger signal T_IN (UV detection signal) becomes H level. Thereafter, when the voltage VBS is returned to the original state, the trigger signal T_IN returns to the L level (time t11). With the falling of the trigger signal T_IN, the selection signal Z0 becomes the L level and the selection signal Z1 becomes the H level. As a result, after time t11, the signal PAD_M of the monitor test pad 14 becomes the output signal VMIN1 of the inverter INV2.

Likewise, after the measurement of VMIN1 is finished, the voltage VBS is once lower than the UV trip voltage to generate the pulse of the trigger signal T_IN, and the select signal Z2 becomes the H level in accordance with the falling of the trigger signal T_IN. Thereby, after time t12, the signal PAD_M of the monitor test pad 14 becomes the input signal VMIN2 of the inverter INV1.

Further, after the measurement of the VMIN2 is finished, the voltage VBS is once lower than the UV trip voltage, the selection signal Z3 becomes H level at this time. After the time t13, the signal PAD_M of the monitor test pad 14, And becomes the input signal VMIN3 of INV2.

Next, the dynamic characteristic test (second test mode) of the level shift circuit will be described. 20 is a diagram showing a configuration example of a level shift circuit in which a dynamic characteristic test can be performed by control of the test mode signal TM2. In the present embodiment, the dynamic characteristics test of the level shift circuit is performed by combining a plurality of path level shift circuits.

The circuit shown in Fig. 20 is configured to drive the SR flip-flop by two-level level shift circuits LSA and LSB. Each of the level shift circuits LSA and LSB has substantially the same configuration as that of the level shift circuit LS of FIG. 16, but has a configuration in which the S and R terminals of the SR flip- Circuit 16 is provided.

The input terminals of the level shift circuits LSA and LSB are provided with a test circuit 15 for inputting the same signal to the level shift circuits LSA and LSB. The validity / invalidity of the test circuit 15 is controlled by the test mode signal TM2. When the test mode signal TM2 is at the L level, the test circuit 15 is disabled, and the pulse signals corresponding to the respective input signals IN_A and IN_B are input to the level shift circuits LSA and LSB.

On the other hand, when the test mode signal TM2 becomes the H level, the test circuit 15 becomes valid and the same signal is input to the level shift circuits LSA and LSB. In this case, when any one of the input signals IN_A and IN_B rises, a pulse signal is simultaneously inputted to the level shift circuits LSA and LSB. If the two level shift circuits LSA and LSB normally operate, the interlock circuit 16 operates and the output signal OUT of the SR flip-flop at the output stage does not change from the L level.

Therefore, when the output signal OUT of the SR flip-flop at the output stage becomes H level, it can be judged that a malfunction such as delay is occurring in any one of the level shift circuits LSA and LSB. Further, by measuring the dynamic characteristics such as the pulse width and the delay time of the test signal appearing in the level shift circuits LSA and LSB at that time, it is possible to specify the cause of the malfunction or the occurrence position.

21 is a timing chart showing a sequence of the dynamic characteristic test in the present embodiment. Here, an example in which the device to be measured is composed of four inverters INV0 to INV3 provided at the respective output terminals of the level shift circuits LSA and LSB in Fig. 20 is shown. In this case, the output signal VMIN0 of the inverter INV0 is input to the analog switch 135 of the test signal output selection circuit 13 (Fig. 17), the output signal VMIN1 of the inverter INV1 is input to the analog switch 136, The output signal VMIN2 of the inverter INV3 is input to the analog switch 138. [ The test signal output selection circuit 13 sequentially outputs the four measurement target signals VMIN0 to VMIN4 in total to the test pad 14 for monitoring in synchronization with the trigger signal T_IN.

Here, also here, the output signal (UV detection signal) of the UV detection circuit 251 of the UV / POR protection circuit 25 is used as the trigger signal T_IN input to the test signal output selection circuit 13, and as the reset signal Rst_IN , And the output signal (power-on reset signal) of the POR detection circuit 252 is used.

When the dynamic characteristic test is performed, the voltage level VTP of the test control signal is set to V _ref2 <VTP <V _ref3 (time t20). In this case, the test mode signal TM2 becomes H level, and the internal circuit of the integrated circuit device 100 becomes the second operation mode.

Further, since the test mode signal TM2 is at the H level, the test circuit 15 becomes effective. Therefore, in response to the rise of the input signal IN_A (or IN_B), the same pulse signal is input to both of the level shift circuits LSA and LSB. Therefore, by observing whether or not the output signal OUT of the SR flip-flop rises, it is possible to detect an abnormality in the level shift circuits LSA and LSB.

In the case of the dynamic characteristic test, the voltage VBS is once lower than the UV trip voltage every time the measurement target signal (any one of VMIN0 to VMIN4) is measured through the monitor test pad 14 like the positive characteristic test, A pulse of the trigger signal T_IN is outputted from the UV detection circuit 251, and the signal PAD_M of the monitor test pad 14 is switched. 21, the output signal VMIN0 of the inverter INV0 is output between the times t20 and t21, the output signal VMIN1 of the inverter INV1 is output between the times t21 and t22, Between times t22 and t23, the output signal VMIN2 of the inverter INV2 is outputted, and the output signal VMIN3 of the inverter INV3 is outputted between the times t23 and t24.

Next, the stress test (third test mode) of the level shift circuit will be described. 22 is a circuit diagram of the internal power supply circuit 8 in which the stress test of the internal circuit is enabled by the control of the test mode signal TM3. Here, the object of the stress test is described as the level shift circuits LSA and LSB shown in Fig.

The internal power supply circuit 8 supplies power to the level shift circuits LSA and LSB and includes an amplifier 303 for outputting an internal power supply voltage and an analog switch for switching the voltage input to the operational amplifier 303 301, and 302, respectively. A reference voltage for normal operation is applied to the analog switch 301, and a reference voltage for stress testing is applied to the analog switch 302.

When the test mode signal TM3 is at the L level, the analog switch 301 is turned on, the analog switch 302 is turned off, and the reference voltage of the normal operation is inputted to the amplifier 303. Therefore, the internal power supply voltage is usually equal to the reference voltage for operation. On the other hand, when the test mode signal TM3 becomes the H level, the analog switch 301 is turned off, the analog switch 302 is turned on, and the reference voltage for the stress test is inputted to the amplifier 303. [ Therefore, the internal power supply voltage changes to the reference voltage for the stress test.

Regarding the reference voltage for the stress test, for example, the external power supply voltage may be set within the element rating value and used as the reference voltage for the stress test.

The internal power supply circuit 8 may be a simple regulator configured by using transistors. 23 and 24 are structural examples of a simple regulator as an internal power supply circuit 8 capable of performing a stress test.

23 shows whether the base potential VB of the transistor 312 that outputs the internal power supply voltage VREG is a reference voltage VZ or a power supply voltage VCC generated by the zener diode 313, And is switched by the transistor 314.

24 shows whether or not the base potential VB of the transistor 322 for outputting the internal power supply voltage VREG is set to be the reference voltage VZ or the power supply voltage VCC generated by the zener diode 323 by the test mode signal TM3 The NMOS transistor 324 is turned on. As the low-current circuit used in Fig. 24, for example, the configuration of Fig. 25 is considered.

26 is a timing chart showing the operation sequence of the internal power supply circuit 8 when transitioning from the normal operation mode to the third test mode (stress test). In the case where the internal power supply circuit 8 has the configuration shown in Fig. 23 Respectively. The PMOS transistor 314 is turned on and the base potential VB of the transistor 312 becomes equal to the reference voltage VZ generated in the transistor 312 in the normal operation mode in which TM1 = TM2 = TM3 = L. Therefore, the internal power supply voltage VREG becomes VZ-Vbe (Vbe is the voltage drop between the base emitter of the transistor 312). VZ-Vbe corresponds to the normal operation action reference potential in Fig.

On the other hand, in the third test mode in which TM3 = H, the PMOS transistor 314 is turned off and the base potential VB of the transistor 312 becomes equal to the power supply voltage VCC. Therefore, the internal power supply voltage VREG rises to VCC-Vbe. VCC-Vbe corresponds to the reference potential for the stress test in Fig.

At this time, a block and a structure that can withstand an applied voltage at the time of the stress test are adopted as the block to be subjected to the stress test. In the stress test, the operation in the recommended condition (normal operation mode) And the like.

27 is a timing chart showing the operation sequence of the level shift circuits LSA and LSB in the normal operation mode. In the normal operation mode, the normal operation test can be performed by measuring the measurement target signal (any one of VMIN0 to VMIN4) through the test pad 14 for monitoring.

In the stress test, after the test mode signal TM3 is set to the H level (VTP> _Vref2 in FIG. 17), the internal power supply voltage is set as the stress test reference voltage and then the same sequence as in FIG. 27 is applied to the level shift circuits LSA and LSB Is performed.

The measurement object element and the measurement object signal in the stress test are basically the same as those in the normal operation test. Then, the measurement result obtained in the stress test is compared with the measurement result obtained in the normal operation test. In this manner, in the two modes in which the internal power supply voltage is different, the same sequence of operations is performed in the internal circuit, and the same measurement target signal is monitored in each mode, so that the dependence of the power supply voltage such as the pulse width and the delay time of the measurement target signal have. Thus, it is possible to detect the defective electrical characteristics of the device under measurement.

At this time, in the normal operation mode (and the third test mode), as shown in FIG. 27, the input signals IN_A and IN_B complementary to each other are inputted to the level shift circuits LSA and LSB, respectively.

In Fig. 27, the operation at the time of power supply start is displayed. When the power supply is started, the reset signal Rst_IN, which is the output signal of the POR detection circuit 252, goes high and the counter circuit of the test signal output circuit 13 is reset (Q1 = Q2 = L in Fig. 17 ), The selection signal Z0 is set to the H level. Thereafter, when the voltage VBS (= VB-VS (VS is a constant value)) between the VB terminal and the VS terminal reaches a predetermined value, the reset signal Rst_IN attains the L level, and the operation of the test signal output circuit 13 The signal Z0 is started from the state of the H-lane (time t30).

Thereafter, the voltage VBS is once lower than the UV trip voltage every time measurement of the measurement target signal (any one of the measurement target signals VMIN0 to VMIN4) is performed through the monitor test pad 14 as in the other tests, A pulse of the trigger signal T_IN is output from the circuit 251, and the signal PAD_M of the monitor test pad 14 is switched. 27, the output signal VMIN0 of the inverter INV0 is outputted between the times t30 and t31, the output signal VMIN1 of the inverter INV1 is outputted between the times t31 and t32, Between times t32 and t33, the output signal VMIN2 of the inverter INV2 is outputted, and the output signal VMIN3 of the inverter INV3 is outputted between the times t33 and t34.

28 shows an example of a test flow of the integrated circuit device 100 according to the present embodiment. This test flow includes a first normal operation test (S2) performed in the normal operation mode, a static characteristic test (S3) performed in the first test mode, a dynamic characteristic test (S4) performed in the second test mode, And the second normal operation test (S6) performed in the normal operation mode are included in the general tests (S1, S7) of the integrated circuit device which has been performed conventionally.

In this test flow, the first normal operation test, the static characteristic test (S3), the dynamic characteristic test (S4), the stress test (S5), and the second normal operation test (S6) are executed in this order. By performing the second normal operation test after the stress test, the integrated circuit device deteriorated during the execution of various tests can be found out and eliminated.

At this time, the present invention can be combined freely with each embodiment within the scope of the invention, or it is possible to modify and omit each embodiment as appropriate.

1 input pad, 2 input circuit, 3 signal transfer circuit, 4 logic circuit, 5 function circuit, 6 output circuit, 7 output pad, 8 internal power circuit, 11 control test pad, 12 test mode identification circuit, 13 test signal output selection Circuit, 14 monitor test pad, 15 test circuit, 16 interlock circuit, 22 Schmitt circuit, 23 pulse generation circuit, 24 level shift circuit, 25 UV · POR protection circuit, 251 UV detection circuit, 252 POR detection circuit, Circuitry, 121 to 123 comparator, 124 test mode identification logic circuit, 121a to 123a inverter, 125, 126 T flip flop, 127 decoder circuit, 131, 132 T flip flop, 133 multiplexer, 134 decoder circuit, 135-137 analog switch , LS, LSA, LSB level shift circuit.

Claims (13)

An internal circuit,
And a test mode identification circuit for identifying the test mode on the basis of a test control signal indicating a test mode which is a type of a test performed in the internal circuit, and for causing the internal circuit to operate according to each test mode. Integrated circuit device.
The method of claim 1,
A monitor test pad for observing a test signal appearing in the internal circuit at the time of testing the internal circuit,
And a test signal output selection circuit for selecting a test signal to be output to the monitor test pad from among a plurality of test signals appearing in the internal circuit at the time of testing the internal circuit,
And the test signal output selection circuit sequentially switches test signals to be output to the monitor test pads with time.
3. The method according to claim 1 or 2,
Wherein the test mode identification circuit identifies a test mode based on a magnitude of the test control signal.
The method of claim 3, wherein
Wherein the test mode identification circuit includes a level trigger circuit configured by using a comparator to which the test control signal is input.
The method of claim 3, wherein
Wherein the test mode identification circuit includes a level trigger circuit configured by using an inverter to which the test control signal is input.
3. The method according to claim 1 or 2,
Wherein the test mode identification circuit includes a counter circuit to which the test control signal is input and identifies a test mode based on an output signal of the counter circuit.
The method of claim 2,
Wherein the test signal output selection circuit comprises:
A counter circuit to which a pulse signal of a predetermined period is input;
And a multiplexer for sequentially selecting the plurality of test signals in accordance with an output signal of the counter circuit and outputting the selected test signals to the test pads for monitoring.
The method of claim 2,
Wherein the test signal output selection circuit comprises:
A plurality of analog switches connected to the testpads for monitoring and to which the plurality of test signals are input;
A counter circuit to which a pulse signal of a predetermined period is input;
And a decoder circuit for sequentially selecting and turning on the plurality of analog switches in response to an output signal of the counter circuit.
3. The method according to claim 1 or 2,
And a control test pad for inputting the test control signal.
The method of claim 9,
Wherein said control test pad is also used as a pad other than a test application.
The method of claim 10,
And the other pad is a pad for signal input or signal monitor.
3. The method according to claim 1 or 2,
Wherein the test control signal is generated by operating a functional circuit associated with the internal circuit at the time of testing the internal circuit.
13. The method of claim 12,
A plurality of test control signals are output from the functional circuit,
Wherein the test mode identification circuit identifies the test mode based on a combination of the plurality of test control signals.

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