KR20130071038A - Socket for testing semiconductor chip - Google Patents

Abstract

PURPOSE: A test socket for a semiconductor chip is provided to insert a guide pin into a guide hole and insert a test pin into a touch hole, thereby preventing damage of a surface of the test pin and inserting the test pin into the touch hole. CONSTITUTION: A plurality of test pins(130) is inserted into a first pin hole and a second pin hole corresponding to first pin holes of a first probe block(110) and second pin holes of a second probe block(120), respectively. A test chip(160) is mounted on a chip mounting unit(150). A pad of the test chip is touched to an upper part of a test pin. The test pin is inserted into touch holes of the chip mounting unit. A guide pin among guide pins(115) of the first probe block is inserted into guide holes of the chip mounting unit.

Description

Socket for semiconductor chip test {SOCKET FOR TESTING SEMICONDUCTOR CHIP}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a socket for testing semiconductor chips, and more particularly to a socket for testing semiconductor chips that can easily test a semiconductor chip having narrow pitch pads.

In general, a semiconductor package has a form in which one semiconductor chip is mounted (Single Chip Package) or at least two semiconductor chips (Multi Chip Package). In general, after the semiconductor package is manufactured, a test process is finally performed.

When the test is performed using a conventional semiconductor chip test socket, a test device for transmitting a test signal and a semiconductor chip to be tested are electrically connected using a test pin. However, as the semiconductor chip is highly integrated, the pitch between pads of the semiconductor chip decreases and the number of pads increases, which makes it difficult for the test pin to contact the pads of the semiconductor chip to be accurately tested.

SUMMARY OF THE INVENTION An object of the present invention is to provide a socket for testing a semiconductor chip which can accurately contact pads of a semiconductor chip to be tested even when testing a semiconductor chip including narrow pitch pads.

In the semiconductor chip test socket according to an exemplary embodiment of the present invention, a plurality of first pinholes penetrating an upper surface and a lower surface is formed, and a plurality of guide pins protrude from the upper surface. A second probe block formed at a lower portion of the probe block, the first probe block, and having a plurality of second pin holes penetrating the upper and lower surfaces at positions corresponding to the positions of the first pin holes; A plurality of test pins respectively inserted through the corresponding first and second pinholes of the second and second pinholes and to which a test signal is applied, and a lower surface of the first probe block and the second probe. An elastic body providing elasticity and a test chip are seated between the upper surface of the block, and the test pin is inserted to contact the pad of the test chip and the upper end of the test pin. The chip mounting portion may include a plurality of contact holes and a plurality of guide holes in which a corresponding guide pin is inserted among the guide pins.

Upper ends of the guide pins may protrude from upper ends of the test pins.

The test pins may be positioned outside the contact holes before the guide pins are inserted into the guide holes, and may be inserted into the contact holes when the guide pins are inserted into the guide holes.

The upper edges of the guide pins may be inclined or rounded, and the edges of the lower surfaces at which the guide pins are inserted into the guide holes may be inclined or rounded. The surface including the inclined or rounded portions of the lower surfaces of the guide holes may be plated.

Each of the test pins may include: a first body inserted into a corresponding first pin hole among the first pin holes and having an upper end contacting a pad of the seating test chip and a lower end protruding from a lower surface of the first probe block; A second body inserted into a corresponding second pinhole of the second pinholes and electrically connected to or separated from the first body, the second body protruding from the lower surface of the first probe block; Is inserted into the connection groove is electrically connected to the connection groove may be electrically connected to the connection groove is elastic and protrudes on the lower surface of the second probe block may include a contact portion to which the test signal is applied.

The test pins may have elasticity and may be inserted into corresponding second pinholes of the second pinholes of the second probe block to be fixed to the second probe block.

According to another aspect of the present invention, there is provided a socket for a semiconductor chip test, wherein a plurality of first pin holes penetrating through an upper surface and a lower surface is formed, and a plurality of guide pins protrude from the upper surface. A first probe block, a second probe block formed at a lower portion of the first probe block, and having a plurality of second pin holes penetrating through an upper surface and a lower surface at a position corresponding to the position of the first pin holes; A plurality of test pins respectively inserted through the corresponding first pinholes and the second pinholes of the pinholes and the second pinholes, and a test signal is applied through a lower end thereof; a lower surface of the first probe block and the second probe hole; An elastic body providing elasticity between the upper surface of the probe block and a test chip are seated, and the test pin is inserted so that the pad of the test chip and the upper end of the test pin contact each other. A plurality of contact holes and a plurality of first guide holes into which a corresponding guide pin is inserted among the guide pins and a chip seating part and the chip seating part, respectively, a position corresponding to the first guide holes It may have a support portion in which a plurality of second guide holes for inserting the guide pin is formed.

Upper ends of the guide pins may protrude from upper ends of the test pins.

The test pins may be positioned outside the contact holes before the guide pins are inserted into the guide holes, and may be inserted into the contact holes when the guide pins are inserted into the guide holes.

The chip seating part is formed on a first insulating layer having a plurality of first holes having the same central axis as the contact holes, and formed on an upper surface of the first insulating layer, and a corresponding first hole among the first holes. A second layer having a plurality of second holes having the same central axis, and formed on an upper surface of the metal layer, wherein the test chip is seated and having the same central axis as the first and second holes having the same central axis And a second insulating layer having a plurality of three holes, wherein the metal layer is formed along an edge of the metal part surrounding each of the second holes to insulate the metal part surrounding each of the second holes. Insulation holes penetrating the upper and lower surfaces may be formed.

The chip seating part may be formed on a first insulating layer having a plurality of first holes having the same central axis as the contact holes, and formed on an upper surface of the first insulating layer, and having a plurality of positions at positions corresponding to the first holes. A metal layer having second holes formed thereon and an upper surface of the metal layer, wherein the test chip is seated, and a plurality of third holes formed at positions corresponding to the first holes and the second holes. And a second insulating layer, wherein each of the second holes may be larger than a size of the first hole or the third hole formed at a corresponding position.

In the socket for a semiconductor chip test according to an embodiment of the inventive concept, the test pin is first inserted into the guide hole and then the test pin is inserted into the contact hole, thereby preventing damage to the surface of the test pin. Inserted into the contact hole has an advantage that can be in precise contact with the pads of the test chip. In addition, the semiconductor chip test socket according to an embodiment of the present invention has an advantage that the guide pin can be easily inserted into the chip seating part even if the position of the guide pin and the guide hole is not exactly matched.

BRIEF DESCRIPTION OF THE DRAWINGS A brief description of each drawing is provided to more fully understand the drawings recited in the description of the invention.
1 is a cross-sectional view of a socket for a semiconductor chip test according to an exemplary embodiment of the inventive concept.
FIG. 2 is a cross-sectional view of a socket for a semiconductor chip test, in which a guide pin is inserted into a guide hole in the socket for a semiconductor chip test of FIG. 1.
FIG. 3 is a cross-sectional view of a socket for a semiconductor chip test illustrating a state in which a test pad is contacted with a test pin in the socket for a semiconductor chip test socket of FIG. 1.
4 is an enlarged view of the guide hole and the guide pin of FIG. 1.
5 is a cross-sectional view of a socket for a semiconductor chip test according to another exemplary embodiment of the inventive concept.
6 is a cross-sectional view of a socket for a semiconductor chip test according to another exemplary embodiment of the inventive concept.
FIG. 7 is a cross-sectional view of the semiconductor chip test socket illustrating a state in which a test pad is contacted with a test pin in the semiconductor chip test socket of FIG. 6.
8 is a cross-sectional view of a socket for a semiconductor chip test according to another exemplary embodiment of the inventive concept.
FIG. 9 is a cross-sectional view of the socket for a semiconductor chip test illustrating a state in which a guide pin is inserted into a guide hole in the socket for the semiconductor chip test of FIG. 8.
FIG. 10 is a cross-sectional view of the semiconductor chip test socket illustrating a state in which a test pad is contacted with a test pin in the semiconductor chip test socket of FIG. 8.
11 is a cross-sectional view of a socket for a semiconductor chip test according to another exemplary embodiment of the inventive concept.
FIG. 12 is a cross-sectional view of the semiconductor chip test socket illustrating a state in which a test pad is in contact with a test pin in the semiconductor chip test socket of FIG.
FIG. 13 is a cross-sectional view of an embodiment of a portion around contact holes of the chip seating portions of FIGS. 8 to 12.
14 is a cross-sectional view of another embodiment of a portion around the contact holes of the chip seating portion of FIGS. 8 to 12.
FIG. 15 is a cross-sectional view of another embodiment of a portion around the contact holes of the chip seating portion of FIGS. 8 to 12.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1 is a cross-sectional view of a socket for a semiconductor chip test according to an exemplary embodiment of the inventive concept.

Referring to FIG. 1, the semiconductor chip test socket 100 may include a first probe block 110, a second probe block 120, a plurality of test pins 130, an elastic body 140, and a chip seating part 150. It may be provided.

The first probe block 110 has a plurality of first pin holes PH1 penetrating the upper surface and the lower surface, and the plurality of guide pins 115 protrude from the upper surface of the first probe block 110. Can be. A corresponding test pin of the test pins 130 may be inserted into each of the first pin holes PH1, and the upper part of the guide pins 115 may be inserted into the first probe block 110. It may protrude from the upper surface of the block 110. The guide pins 115 may be inserted into the probe block 110 and may be moved slightly left and right without being fixed. Therefore, even if the positions of the guide hole GDH and the guide pin 115 do not exactly match each other and are finely twisted as described below, the guide pin 115 is inserted into the guide hole GDH through fine left and right movement. Can be. The first probe block 110 has first pinholes PH1 formed in a state in which a plurality of wafers are stacked, a plurality of plastic layers are stacked or at least one wafer and at least one plastic layer are stacked. The guide pin 115 may be inserted and formed.

The second probe block 120 is formed under the first probe block 110 and includes a plurality of second pin holes penetrating the upper and lower surfaces at positions corresponding to the positions of the first pin holes PH1. PH2) can be formed. A corresponding test pin of the test pins 130 may be inserted into each of the second pin holes PH2. In the second probe block 120, the second pinholes PH2 may be formed in a state in which a plurality of wafers are stacked, a plurality of plastic layers are stacked or at least one wafer and at least one plastic layer are stacked. Can be.

Each of the test pins 130 may be inserted into a corresponding first pinhole and a second pinhole among the first pinholes PH1 and the second pinholes PH2, respectively. That is, one test pin may be inserted into the first pin hole PH1 and the second pin hole PH2 formed at the corresponding position. Each of the test pins 130 is applied with a test signal through the lower end, and the upper end is inserted into the contact hole CTH of the chip seating part 150 to perform electrical tests with the pads of the test chip 160. Can be contacted. The test pins 130 may be elastic pins such as pogo pins or the like, or may have shapes such as those of FIGS. 6 and 7.

A cover layer (eg, a film) may be formed on the bottom surface of the second probe block 120 to prevent the test pins 130 from being separated from the bottom of the second probe block 120. The cover layer may have through-holes through which a portion of the test pins to which the test signal is applied may protrude. The remaining portion of the cover layer except for the portion of the test pins 130 to which the test signal is applied is formed on the cover layer. Supported by the second probe block 120 may not be separated from the bottom.

 The elastic body 140 may provide elasticity between the lower surface of the first probe block 110 and the upper surface of the second probe block 120. For example, the second probe block 120 is fixed without moving, and when the elastic body 140 provides elasticity, the first probe block 110 may move. That is, when pressure is provided from the first probe block 110 to the second probe block 120 in order to test the test chip 160, the first probe block 110 moves downward in the second direction in FIG. 1. When moving in the direction of the probe block 120, the test is terminated and the pressure is not provided, the first probe block 110 is moved upward by the elasticity (restoration force) provided by the elastic body 140 (chip seating in FIG. 1). In the direction of the unit 150). The elastic body 140 may be inserted into a groove for the elastic body formed on the lower surface of the first probe block 110 and the upper surface of the second probe block 120 to provide elasticity. For example, when the first probe block 110 and the second probe block 120 are formed in a state in which the wafers are stacked, the elastic body 140 is formed in the groove for the elastic body formed in at least one of the stacked wafers. ) Can be inserted.

The chip seating unit 150 may be mounted with the test chip 170, and a plurality of contact holes CTH and a plurality of guide holes GDH penetrating the upper and lower surfaces may be formed. The plurality of contact holes CTH may be through-holes in which the test pin 130 is inserted such that the pad of the test chip 160 seated on the chip seat 150 contacts the upper end of the test pin 130. That is, one portion of the test pin 130 in the upper direction may be inserted into the corresponding contact hole CTH. The pads of the test chip 160 may have a solder ball shape. In this case, the solder ball pads may be inserted into the contact hole CTH. A corresponding guide pin of the guide pins 115 may be inserted into the plurality of guide holes GDH. The chip seating unit 150 may include a wafer in which a plurality of contact holes CTH and a plurality of guide holes GDH are formed.

The guide pin 115 may protrude from the top of the test pin 130. That is, the upper end of the guide pin 115 may be at a position higher than the upper end of the test pin 130. Therefore, according to the exemplary embodiment of the inventive concept, the position of the guide pin 115 and the position of the guide hole GDH do not exactly match each other, and are finely twisted so that a part of the guide pin 115 may be partially misaligned. Even when the bottom surface of the chip seat 150 is in contact, the upper end position of the test pin 130 is lower than the upper end position of the guide pin 115 (the chip 160 for the test) The upper portion of the test pin 130 in contact with the pad of the) does not contact the surface of the chip seat 150 may protect the surface of the test pin 130. After the guide pin 115 is inserted into the guide hole GDH to exactly match the position of the contact holes CTH and the position of the test pin 130, the test pin 130 contacts the contact hole CTH. Since it is inserted in, the test pin 130 and the pads of the test chip 160 may be in precise electrical contact. A method of performing the test will be described in more detail with reference to FIGS. 2 and 3.

The guide pin 115 may be formed to have an inclined edge of the upper surface or rounding, and the guide hole GDH may have an inclined edge of the lower surface at which the guide pin 115 begins to be inserted. It may be formed to have or rounded. As it is formed in such a shape, even if the position of the guide pin 115 and the position of the guide hole (GDH) does not exactly match the inclination or rounding process without damaging the guide pin 115 or the chip mounting portion 150 The guide pin 115 can be accurately inserted into the guide hole GDH by moving along the edge. In addition, a surface including an inclined or rounded portion of the lower surface of the guide hole GDH may be plated. An embodiment of the shape of the guide pin 115 and the shape of the guide hole GDH will be described in more detail with reference to FIG. 4.

FIG. 2 is a cross-sectional view of the semiconductor chip test socket 100 illustrating a state in which the guide pin 115 is inserted into the guide hole GDH in the semiconductor chip test socket 100 of FIG. 1.

1 and 2, when the test chip 160 mounted on the chip seating part 150 is tested, the chip seating part 150 may be inserted into the guide pin 115 to be inserted into the guide hole GDH. The upper surface of the test pin 130 is lower than the upper position of the guide pin 115, when the upper surface of the test pin 130 is in contact with the pad of the test chip 160. The upper portion of the pin 130) may not contact the surface of the chip seat 150 to protect the surface of the test pin 130. Subsequently, when the guide pin 115 begins to be inserted into the guide hole GDH, the position of the test pin 130 and the position of the contact hole CTH coincide with each other so that the test pin 130 also contacts the hole. (CTH) can be inserted. Therefore, even when the position of the guide pin 115 and the position of the guide hole GDH do not exactly match at one time, the upper end of the test pin 130 does not contact the lower surface of the chip seat 150. There is no risk that the top of the test pin 130 is broken.

3 is a view illustrating a state in which a pad of a test chip 160 and a test pin 130 are in contact with each other to perform a test in the semiconductor chip test socket 100 of FIG. 1. It is a cross section.

1 to 3, when the guide pin 115 begins to be inserted into the guide hole GDH as shown in FIG. 2, the position of the test pin 130 and the position of the contact hole CTH are Will match. Therefore, when the chip mounting part 150 continuously moves in the direction of the second probe block 120, the first probe block 110 also moves in the direction of the second probe block 120 by compression of the elastic body 140. do. As the chip seating part 150 and the first probe block 110 move, the test pin 130 is inserted into a corresponding contact hole CTH. In this case, since the guide pin 115 is inserted into the guide hole GDH to match the position of the test pin 130 with the position of the contact hole CTH, the test pin 130 is the contact hole CTH. The pads of the test chip 160, which are inserted and inserted into the test chip 160, may be accurately and electrically contacted. When the test is completed by performing the test as described above, the first probe block 110 and the second probe block 120 are separated by the restoring force of the elastic body 140.

4 is an enlarged view of the guide hole GDH and the guide pin 115 of FIG. 1.

1 to 4, the edge of the top surface of the guide pin 115 may be formed to be inclined or formed in a round shape (not shown), and the guide hole GDH of the guide pin 115 is inserted. The bottom edge may also be formed to be inclined or rounded (not shown). Therefore, even when the central axis of the guide pin 115 does not exactly coincide with the central axis of the guide hole GDH, the guide pin 115 slides along the inclined surface or the rounded shape, and the guide pin 115 is formed in the guide hole GDH. Can be inserted.

In addition, the surface including the inclined or rounded portion of the lower surface of the guide hole GDH may be plated 410. For example, the inclined or rounded portion of the inner wall surface and the lower surface of the guide hole GDH may be plated 410. Since the surface of the guide hole GDH is flattened by the plating treatment as described above, the guide pin 115 may be inserted into the guide hole GDH better, and the guide pin 115 may be inserted into the guide hole. In the process of finding (GDH), it is possible to prevent damage due to contact between the guide pin 115 and the guide hole (GDH).

In FIG. 4, only the guide hole GDH is plated, but the present invention is not limited thereto. Only the guide pin 115 may be plated or the guide pin 115 and the guide hole GDH may be plated. Plating may be performed using various other methods such as plating all.

5 is a cross-sectional view of a socket for a semiconductor chip test according to another exemplary embodiment of the inventive concept.

1 to 5, the semiconductor chip test socket 500 may include the first probe block 110, the second probe block 120, and the plurality of sockets in the same manner as the semiconductor chip test socket 100 of FIG. 1. The test pins 130, the elastic body 140, and the chip seating part 150 may be provided. That is, the components and operations of the semiconductor chip test socket 500 are the same as those described with reference to FIGS. 1 to 4, and thus redundant descriptions thereof will be omitted. The semiconductor chip test socket 500 of FIG. 5 has the test pins 130 fixed to the second pin hole PH2 of the second probe block 120 by the fixing member 510. It is different from the test socket 100. The test pins 130 may be pins having elasticity such as pogo pins as described above.

5, as in the embodiment of FIG. 1, a cover layer (eg, a film, etc.) for preventing the test pins 130 from escaping to the bottom of the second probe block 120 includes a second probe block. It may be formed on the lower surface of the (120). The cover layer may have through-holes through which a portion of the test pins to which the test signal is applied may protrude. The remaining portion of the cover layer except for the portion of the test pins 130 to which the test signal is applied is formed on the cover layer. Supported by the second probe block 120 may not be separated from the bottom.

6 is a cross-sectional view of a semiconductor chip test socket 600 according to another embodiment of the inventive concept, and FIG. 7 is a cross-sectional view of the test chip 160 in the semiconductor chip test socket 600 of FIG. 6. A cross-sectional view of a semiconductor chip test socket 800 showing a state in which a pad and a test pin 130 ′ are in contact with each other to perform a test.

1 to 7, the semiconductor chip test socket 600 may include the first probe block 110, the second probe block 120, and the plurality of sockets in the same manner as the semiconductor chip test socket 100 of FIG. 1. The test pins 130 ′, the elastic body 140, and the chip seating part 150 may be provided. That is, except for the structure of the test pins 130 ′ of the socket for the semiconductor chip test, each component and operation are the same as those described with reference to FIGS. 1 to 4, and thus redundant descriptions thereof will be omitted.

Each of the test pins 130 ′ may include a first body 610 and a second body 620. The first body 610 is inserted into a corresponding first pinhole of the first pinholes PH1, and an upper end of the first body 610 contacts a pad of the test chip 160 seated on the chip seating part 150. 1 may protrude from the lower surface of the probe block 110. The first body 610 may be a straight pin that can be inserted into the connecting groove 623 to move vertically as shown in Figures 6 and 7, the present invention is not limited to this case, the first body 610 ) May have various other shapes as long as it can be electrically connected to or separated from the second body 620.

The second body 620 may be inserted into a corresponding second pinhole among the second pinholes PH2, and may be electrically connected to or separated from the first body 610. The second body 620 may include a connection groove 623 and a contact portion 625. The connection groove 623 may be electrically connected by inserting a portion of the first body 610 protruding from the lower surface of the first probe block 110. For example, the connecting groove 623 may be a groove having a 'Y' shape, but the present invention is not limited to this case and may have a different shape if electrical connection or separation with the first body 610 is possible. It may be. The contact part 625 may be electrically connected to the connection groove 623, may have elasticity, and may protrude from the lower surface of the second probe block 120 to apply the test signal. For example, the contact portion 625 may be disposed between the connection groove 623 and a portion to which the test signal is applied (a portion of the contact portion 625 protruding to the bottom of the second probe block 120), as shown in FIG. 6. It may be a curved pin to electrically connect the.

A cover layer (eg, a film, etc.) is provided at the bottom of the second probe block 120 to prevent the second body 620 of the test pins 130 ′ from being separated from the bottom of the second probe block 120. It can be formed on the side. The cover layer may have through-holes through which a portion of the test pins 130 'may be protruded, and may be formed therein, and a portion of the test pins 130' to which the test signal is applied (the first contact portion 625). The remaining portions except for the second probe block 120 protruding downward may be supported by the cover layer so as not to be separated from the lower portion of the second probe block 120.

8 is a cross-sectional view of a socket for a semiconductor chip test according to another exemplary embodiment of the inventive concept.

Referring to FIG. 8, the semiconductor chip test socket 800 may include a first probe block 810, a second probe block 820, a plurality of test pins 830, an elastomer 840, and a chip seat 850. And a support 870.

The first probe block 810 has a plurality of first pin holes PH1 penetrating the upper surface and the lower surface, and the plurality of guide pins 815 protrude from the upper surface of the first probe block 810. Can be. A corresponding test pin of the test pins 830 may be inserted into each of the first pin holes PH1, and the upper part of the guide pins 815 may be inserted into the first probe block 810. It may protrude from the top surface of block 810. The guide pins 815 may be inserted into the probe block 810 and may be slightly moved left and right without being fixed. Therefore, even if the positions of the guide hole GDH and the guide pin 815 are not exactly matched and finely twisted as described below, the guide pin 815 is inserted into the guide hole GDH through fine left and right movement. Can be. The first probe block 810 has first pinholes PH1 formed in a state in which a plurality of wafers are stacked, a plurality of plastic layers are stacked or at least one wafer and at least one plastic layer are stacked. The guide pin 815 may be inserted into the guide pin 815.

The second probe block 820 is formed under the first probe block 810 and includes a plurality of second pin holes penetrating the upper and lower surfaces at positions corresponding to the positions of the first pin holes PH1. PH2) can be formed. A corresponding test pin of the test pins 830 may be inserted into each of the second pin holes PH2. In the second probe block 820, the second pinholes PH2 may be formed in a state in which a plurality of wafers are stacked, a plurality of plastic layers are stacked or at least one wafer and at least one plastic layer are stacked. Can be.

Each of the test pins 830 may be inserted into a corresponding first pinhole and a second pinhole among the first pinholes PH1 and the second pinholes PH2, respectively. That is, one test pin may be inserted into the first pin hole PH1 and the second pin hole PH2 formed at the corresponding position. Each of the test pins 830 is applied with a test signal through the lower end, and the upper end is inserted into the contact hole CTH of the chip seat 850 to perform electrical tests with the pads of the test chip 160. Can be contacted. The test pins 830 may be elastic pins such as pogo pins or the like, or may have shapes such as those of FIGS. 11 and 12.

A cover layer (eg, a film) may be formed on the bottom surface of the second probe block 820 to prevent the test pins 830 from being separated from the bottom of the second probe block 820. The cover layer may have through-holes through which a portion of the test pins to which the test signal is applied may protrude. The remaining portion of the cover layer except for the portion to which the test signal is applied is applied to the cover layer. Supported by the second probe block 820 may not be separated from the lower portion.

 The elastic body 840 may provide elasticity between the lower surface of the first probe block 810 and the upper surface of the second probe block 820. For example, the second probe block 820 is fixed without moving and the first probe block 810 may move when the elastic body 840 provides elasticity. That is, when pressure is provided from the first probe block 810 to the second probe block 820 to test the test chip 860, the first probe block 810 is directed downward (the second in FIG. 8). When moving to the probe block 820, the test is terminated and the pressure is not provided, the first probe block 810 is moved upward by the elasticity (restoration force) provided by the elastic body 840 (chip mounting in FIG. 8). Direction 850). The elastic body 840 may be inserted into a groove for the elastic body formed in the lower surface of the first probe block 810 and the upper surface of the second probe block 820 to provide elasticity. For example, when the first probe block 810 and the second probe block 820 are formed in a state in which the wafers are stacked, an elastic body 840 is formed in the groove for the elastic body formed in at least one of the stacked wafers. ) Can be inserted.

The test chip 870 may be seated on the chip seat 850, and a plurality of contact holes CTH and a plurality of first guide holes penetrating the upper and lower surfaces may be formed. The plurality of contact holes CTH may be through holes into which the test pin 830 is inserted such that the pad of the test chip 860 seated on the chip seat 850 contacts the upper end of the test pin 830. That is, one portion of the test pin 830 in the upper direction may be inserted into the corresponding contact hole CTH. The pads of the test chip 860 may have a solder ball shape, in which case the solder ball pads may be inserted into the contact hole CTH. A corresponding guide pin of the guide pins 815 may be inserted into the plurality of first guide holes. The chip seat 850 may include a wafer in which a plurality of contact holes CTH and a plurality of first guide holes are formed.

The support part 870 may be coupled to the chip seating part 850, and second guide holes may be formed in which guide pins 815 are inserted at positions corresponding to the first guide holes of the chip seating part 850. have. The guide hole GDH means a hole in which the first guide hole and the second guide hole are combined at corresponding positions.

The embodiment of FIG. 8 may be applied to the case where it is difficult to form the guide hole GDH in the chip seat 850 due to a thin thickness of the chip seat 850. For example, the chip seat 850 may be manufactured to have a thin thickness in the form of a metal layer formed between the insulating layers. Embodiments of the chip seat 850 will be described in more detail with reference to FIGS. 13 to 15.

The guide pin 815 may protrude from the top of the test pin 830. That is, the upper end of the guide pin 815 may be at a higher position than the upper end of the test pin 830. Therefore, according to the exemplary embodiment of the inventive concept, the position of the guide pin 815 and the position of the guide hole GDH do not exactly match each other, and are finely twisted so that a part of the guide pin 815 Even when the bottom surface of the chip seat 850 is in contact, the top position of the test pin 830 is lower than the top position of the guide pin 815 (the chip of the test pin 860 The upper portion of the test pin 830 in contact with the pad) may not be in contact with the surface of the chip seat 850 to protect the surface of the test pin 830. In addition, the guide pin 815 is inserted into the guide hole GDH to exactly match the position of the contact holes CTH and the position of the test pin 830, and then the test pin 830 contacts the contact hole CTH. Since it is inserted in the test pin 830 and the pads of the test chip 860 can be precisely in electrical contact. A method of performing the test will be described in more detail with reference to FIGS. 9 and 10.

The guide pin 815 may be formed to have an inclined edge of the upper surface or may be rounded, and the guide hole GDH may have an inclined edge of the lower surface at which the guide pin 815 begins to be inserted. It may be formed to have or rounded. As it is formed in such a shape, even when the position of the guide pin 815 and the position of the guide hole GDH do not exactly match, the inclination or rounding treatment is performed without damaging the guide pin 815 or the chip seat 850. The guide pin 815 can be accurately inserted into the guide hole GDH by moving along the edge. Embodiments of the shape of the guide pin 815 and the shape of the guide hole GDH are similar to those described with reference to FIG. 4, and thus, the descriptions with reference to FIG. 4 will be replaced.

9 is a cross-sectional view of the semiconductor chip test socket 800 illustrating a state in which the guide pin 815 is inserted into the guide hole GDH in the semiconductor chip test socket 800 of FIG. 8.

8 and 9, when the test chip 860 mounted on the chip seat 850 is tested, the chip seat 850 may be inserted into the guide pin 815 in the guide hole GDH. ), The upper position of the test pin 830 is lower than the upper position of the guide pin 815, so that the surface of the test pin 830 contacts the pad of the test chip 860. The upper portion of the pin 830 does not contact the surface of the chip seat 850 to protect the surface of the test pin 830. Subsequently, when the guide pin 815 begins to be inserted into the guide hole GDH, the position of the test pin 830 and the position of the contact hole CTH coincide with each other so that the test pin 830 also contacts the hole. (CTH) can be inserted. Therefore, even when the position of the guide pin 815 and the position of the guide hole GDH do not coincide exactly at one time, the upper end of the test pin 830 does not contact the lower surface of the chip seat 850. There is no risk that the top of the test pin 830 is broken.

FIG. 10 is a view illustrating a state in which a pad of a test chip 860 and a test pin 830 are in contact with each other to perform a test in the semiconductor chip test socket 800 of FIG. 8. It is a cross section.

8 to 10, when the guide pin 815 starts to be inserted into the guide hole GDH as shown in FIG. 9, the position of the test pin 830 and the position of the contact hole CTH are Will match. Therefore, when the chip seat 850 continuously moves in the direction of the second probe block 820, the first probe block 810 also moves in the direction of the second probe block 820 by compression of the elastic body 840. do. As the chip seat 850 and the first probe block 810 move, the test pin 830 is inserted into a corresponding contact hole CTH. In this case, since the guide pin 815 is inserted into the guide hole GDH to match the position of the test pin 830 with the position of the contact hole CTH, the test pin 830 is the contact hole CTH. The pads of the test chip 860, which are correctly inserted and seated in the pads, may be precisely and electrically contacted. When the test is completed by performing the test as described above, the first probe block 810 and the second probe block 820 are separated by the restoring force of the elastic body 840.

FIG. 11 is a cross-sectional view of a semiconductor chip test socket 1100 according to another exemplary embodiment of the inventive concept, and FIG. 12 is a view illustrating a test chip 860 in the semiconductor chip test socket 1100 of FIG. 11. A cross-sectional view of the semiconductor chip test socket 1100 illustrates a state in which a pad and a test pin 830 'contact each other to perform a test.

8 to 12, the semiconductor chip test socket 1100 may include a first probe block 810, a second probe block 820, and a plurality of sockets in the same manner as the semiconductor chip test socket 800 of FIG. 8. The test pins 830 ′, the elastic body 840, the chip seating part 850, and the support part 870 may be provided. That is, except for the structure of the test pins 830 ′ of the semiconductor chip test socket 1100, each component and operation are the same as those described with reference to FIGS. 8 to 10, and thus redundant descriptions thereof will be omitted.

Each of the test pins 830 ′ may include a first body 1110 and a second body 1120. The first body 1110 is inserted into a corresponding first pinhole among the first pinholes PH1, and an upper end of the first body 1110 contacts the pad of the test chip 860 seated on the chip seat 850. 1 may protrude from the lower surface of the probe block 810. The first body 1110 may be a straight pin that can be inserted into the connecting groove 1123 by vertically moving as shown in FIGS. 11 and 12, but the present invention is not limited thereto, and the first body 1110 is not limited thereto. ) May have various other shapes as long as it can be electrically connected to or separated from the second body 1120.

The second body 1120 may be inserted into a corresponding second pinhole among the second pinholes PH2, and may be electrically connected to or separated from the first body 1110. The second body 1120 may include a connection groove 1123 and a contact part 1125. The connection groove 1123 may be electrically connected by inserting a portion of the first body 1110 protruding from the lower surface of the first probe block 810. For example, the connecting groove 1123 may be a groove having a 'Y' shape, but the present invention is not limited thereto, and may have another shape if the first body 1110 may be electrically connected or separated. It may be. The contact part 1125 may be electrically connected to the connection groove 1123, may have elasticity, may protrude to a lower surface of the second probe block 820, and the test signal may be applied thereto. For example, as shown in FIG. 11, the contact part 1125 is between a connection groove 1123 and a part to which the test signal is applied (a part protruding to the bottom of the second probe block 820 of the contact part 1125). It may be a curved pin to electrically connect the.

A cover layer (eg, a film) is provided on the lower portion of the second probe block 820 to prevent the second body 1120 of the test pins 830 'from escaping to the lower portion of the second probe block 820. It can be formed on the side. The cover layer may have through holes through which a portion of the test pins 830 'protrudes from which the test signal is applied, and a portion of the test pins 830' to which the test signal is applied (first of the contact portions 1125). The remaining portion except for the second probe block 820 may be supported by the cover layer so as not to be separated from the bottom of the second probe block 820.

13 is a cross-sectional view of an embodiment of a portion around the contact holes CTH of the chip seat 850 of FIGS. 8 to 12.

8 to 13, the chip mounting part 850 may include a first insulating layer 1310, a metal layer 1320, and a second insulating layer 1330. The first to third holes having the same central axis formed in each of the first insulating layer 1310, the metal layer 1320, and the second insulating layer 1330 of the chip mounting part 850 are combined to form a contact hole CTH. Can be formed. That is, the contact hole CTH may include the first to third holes.

The first insulating layer 1310 may have a plurality of first holes having the same central axis as the contact holes CTH. The first insulating layer 1310 is formed of an insulating material, and may be, for example, a flexible polymer polymer film having insulating properties. For example, the first insulating layer 1310 may be a flexible film including polyethylene terephthalate (PET), liquid crystal polymer (LCP), or polyimide (PI), or may be formed on the insulating film. The copper foil may be a flexible copper clad laminate (FCCL) film. However, the present invention is not limited to this case and may be formed using an insulating material of various other materials. When the first insulating layer 1310 is the flexible copper foil laminated film, the first insulating layer 1310 has a very thin thickness, and the first insulating layer 1310 uses an insulating material even when the flexible copper foil laminated film is not used. It can be formed thin.

The metal layer 1320 may be formed on an upper surface of the first insulating layer 1310, and a plurality of second holes having the same central axis as the corresponding first hole among the first holes may be formed. By forming the metal layer 1320 on the top surface of the first insulating layer 1310, the chip seat 850 may be formed even after repeatedly testing the test chip 860 seated on the top surface of the chip seat 850. It can prevent deformation such as stretching or tearing, and can firmly support the test chip 860 on which the chip seating portion 850 is seated, thereby preventing a portion of the chip seating portion 850 from sagging downward. can do.

The metal layer 1320 may be formed of a metal material having elasticity. For example, the metal layer 1320 may be formed of a nickel material, a binary nickel alloy material having elasticity such as nickel-cobalt alloy, nickel-iron alloy, or nickel-manganese alloy, or an iron-chromium-nickel alloy. It may be formed of a ternary nickel alloy material such as an iron-nickel-manganese alloy or an iron-nickel-cobalt alloy, a copper alloy material such as a beryllium copper alloy, or a stainless material. However, the metal layer of the present invention is not limited to this case, and the metal layer 1320 may be formed on the upper surface of the first insulating layer 1310 to prevent deformation or sag of the chip seat 850. Other metals may be used. For example, the metal layer 1320 may be formed by plating after forming a sputter on an upper surface of the first insulating layer 1310.

The second insulating layer 1330 may be formed on the upper surface of the metal layer 1320, and a plurality of third holes having the same central axis as the first hole and the second hole having the same central axis may be formed. That is, the first hole, the second hole, and the third hole having the same central axis may be combined to form a contact hole CTH. A test chip 860 may be seated on an upper surface of the second insulating layer 1330, and a pad of the test chip 860 is positioned in the third hole. For example, when the pad of the test chip 860 has a solder ball shape, the pad of the solder ball shape may be inserted into the third hole. The second insulating layer 1330 may be made of an insulating polymer polymer (eg, polyimide), but the present invention is not limited thereto, and the second insulating layer 1330 may be formed of an insulating material of various other materials. An insulating layer 1330 may be formed. In addition, the second insulating layer 1330 may be formed using an insulating film, or may be formed by applying a liquid insulating material to the upper surface of the metal layer 1320 and curing the same.

An insulating hole 1340 may be formed at an edge of the metal part surrounding each of the second holes to insulate the metal part surrounding each of the second holes. The insulating hole 1340 may have a shape penetrating the upper and lower surfaces of the metal layer 1320. That is, the insulating hole 1340 is formed along the edge of the metal part surrounding each of the second holes, thereby insulating the metal part surrounding each second hole from another part of the metal layer 1320. have.

For example, the pad or test pin 830 or 830 ′ of the solder ball-shaped test chip 860 may be electrically contacted with a metal part surrounding the second hole while being inserted into the contact hole CTH. have. In this case, when the contacted metal part is not insulated from the metal part surrounding the other second hole, the pads of the test chip are electrically connected or the test pins are electrically connected and thus cannot be normally tested. Problems will arise. Accordingly, in one embodiment of the present invention, in order to prevent the electrical connection between the pads of the test chip or the electrical connection between the test pins, an insulating hole 1340 surrounding each of the second holes is formed. The insulating hole 1340 may be formed in the metal layer 1320 in a quadrangular shape surrounding the second hole. However, the present invention is not limited to this case, and may have another polygonal shape surrounding the second hole or a curved shape surrounding the second hole.

14 is a cross-sectional view of another embodiment of a portion around the contact holes CTH of the chip seating portion 850 of FIGS. 8 to 12, and FIG. 15 is a portion of the chip seating portion 850 of FIGS. 8 to 12. A cross-sectional view of another embodiment of a portion around the contact holes CTH.

8 to 12, 14, and 15, the chip seat 850 may include a first insulating layer 1410, a metal layer 1420, and a second insulating layer 1430 or 1530. The first to third holes formed in each of the first insulating layer 1410, the metal layer 1420, and the second insulating layer 1430 or 1530 of the chip seat 850 may be combined to form a contact hole CTH. Can be. That is, the contact hole CTH may include the first to third holes.

In the first insulating layer 1410, a plurality of first holes may be formed at positions corresponding to the contact holes CTH. The first insulating layer 1410 is formed of an insulating material, and may be, for example, a flexible polymer polymer film having insulating properties. For example, the first insulating layer 1410 may be a flexible film including polyethylene terephthalate (PET), liquid crystal polymer (LCP), or polyimide (PI), or may be formed on the insulating film. The copper foil may be a flexible copper clad laminate (FCCL) film. However, the present invention is not limited to this case and may be formed using an insulating material of various other materials. When the first insulating layer 1410 is the flexible copper foil laminated film, the first insulating layer 1410 has a very thin thickness, and the first insulating layer 1410 uses an insulating material even if the flexible copper foil laminated film is not used. It can be formed thin.

The metal layer 1420 may be formed on an upper surface of the first insulating layer 1410, and a plurality of second holes may be formed at positions corresponding to the first holes. By forming the metal layer 1420 on the upper surface of the first insulating layer 1410, even if the test chip seated on the upper surface of the chip seat 850 is repeatedly tested, the chip seat 850 is stretched or torn. It is possible to prevent deformation such as losing, and when the test chip is seated on the upper surface of the chip seat 850, the chip seat 850 may firmly support the test chip 860, thereby providing a chip seat ( A portion of the 850 may be prevented from sagging down.

The metal layer 1420 may be formed of a metal material having elasticity. For example, the metal layer 1320 may be formed of a nickel material, a binary nickel alloy material having elasticity such as nickel-cobalt alloy, nickel-iron alloy, or nickel-manganese alloy, or an iron-chromium-nickel alloy. It may be formed of a ternary nickel alloy material such as an iron-nickel-manganese alloy or an iron-nickel-cobalt alloy, a copper alloy material such as a beryllium copper alloy, or a stainless material. However, the metal layer of the present invention is not limited to this case, and the metal layer 1420 may be formed on the upper surface of the first insulating layer 1410 to prevent deformation or sag of the chip seat 850. Other metals may be used. For example, the metal layer 1420 may be formed by plating after forming a sputter on the top surface of the first insulating layer 1410.

The second insulating layer 1430 or 1530 may be formed on an upper surface of the metal layer 1420, and a plurality of third holes may be formed at positions corresponding to the first holes and the second holes. That is, the first hole, the second hole, and the third hole formed at the corresponding position may be combined to form a contact hole CTH. The test chip may be seated on an upper surface of the second insulating layer 1430 or 1530, and a pad of the test chip is positioned in the third hole. As described with reference to FIG. 8, for example, when the pad of the test chip has a solder ball shape, the pad of the solder ball shape may be inserted into the third hole. The second insulating layer 1430 or 1530 may be made of an insulating polymer polymer (eg, polyimide), but the present invention is not limited thereto. The second insulating layer 1430 or 1530 may be formed. In addition, the second insulating layer 1430 or 1530 may be formed using an insulating film, or may be formed by applying a liquid insulating material to the upper surface of the metal layer 1420 and curing the same. For example, as shown in FIG. 15, the liquid insulating material is applied to cover the upper surface of the metal layer 1420 and the outer circumferential surface of the second hole of the metal layer, and then cured to form a second insulating layer having the shape as shown in FIG. 15. 1530 may be formed. In the embodiment of FIG. 15, the first hole and the third hole may be combined to form a contact hole CTH.

The size of each of the second holes formed in the metal layer 1420 may be larger than the size of the first hole or the third hole formed in the corresponding position. For example, when the pad or test pin 830 or 830 'of the test chip 860 having a solder ball shape is inserted into the contact hole CTH, the second hole is the first hole or the third hole. Since the pad or test pins 830 or 830 'of the test chip 860 are larger than the metal layer 1420, the pads or the test pins 860' are not in contact with each other. If the size of the second hole is less than or equal to the size of the first hole and the third hole, pads or test pins 830 or 830 'of the test chip 860 inserted into the contact hole CTH. There is a problem that the electrical connection between the two can not be tested normally.

Therefore, in another embodiment of the present invention, in order to prevent the electrical connection between the pads of the test chip or the electrical connection between the test pins, the size of the second hole is larger than the size of the first hole or the third hole of the corresponding position. Formed. The first hole, the second hole, and the third hole of the corresponding position described above may have the same central axis. That is, when the first to third holes have the same central axis, the diameter of the second hole may be larger than the diameter of the first hole or the diameter of the third hole.

As described above, optimal embodiments have been disclosed in the drawings and the specification. Although specific terms have been employed herein, they are used for purposes of illustration only and are not intended to limit the scope of the invention as defined in the claims or the claims. Therefore, those skilled in the art will appreciate that various modifications and equivalent embodiments are possible without departing from the scope of the present invention. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (22)

A first probe block having a plurality of first pin holes penetrating the upper surface and the lower surface, the plurality of guide pins protruding from the upper surface;
A second probe block formed under the first probe block and having a plurality of second pin holes penetrating through an upper surface and a lower surface at positions corresponding to the positions of the first pin holes;
A plurality of test pins respectively inserted through the corresponding first and second pinholes of the first and second pinholes and to which a test signal is applied;
An elastic body providing elasticity between a lower surface of the first probe block and an upper surface of the second probe block; And
A test chip is seated, a plurality of contact holes into which the test pin is inserted so that the pad of the test chip and the upper end of the test pin are in contact, and a plurality of guide holes into which the corresponding guide pin is inserted. The socket for a semiconductor chip test, characterized in that it comprises a chip mounting portion is formed. According to claim 1, wherein the upper end of the guide pin,
The socket for a semiconductor chip test, characterized in that protruding from the top of the test pins. The method of claim 2, wherein the test pins,
And the guide pins are positioned outside the contact holes before being inserted into the guide holes, and are inserted into the contact holes when the guide pins are inserted into the guide holes. The method of claim 1,
The upper edges of the guide pins are inclined or rounded, and the edges of the lower surfaces at which the guide pins are inserted into the guide holes are inclined or rounded. A socket for testing semiconductor chips. The method of claim 5,
And the surface including the inclined or rounded portion of the lower surface of the guide holes is plated. The method of claim 1, wherein the elastic body,
The socket for semiconductor chip test, characterized in that it is inserted into the groove for the elastic body formed on the lower surface of the first probe block and the upper surface of the second probe block. The method of claim 1, wherein the test pins,
It is an elastic pin,
The pad of the test chip,
A socket for semiconductor chip testing, characterized in that the solder ball shape. The method of claim 1, wherein each of the test pins,
A first body inserted into a corresponding first pin hole among the first pin holes and having an upper end contacting a pad of the seated test chip and a lower end protruding from a lower surface of the first probe block; And
A second body inserted into a corresponding second pinhole of the second pinholes and electrically connected to or separated from the first body,
The second body,
A connection groove in which a first body protruding from the lower surface of the first probe block is inserted into and electrically connected to the first probe block; And
And a contact part electrically connected to the connection groove and elastic and protruding from a lower surface of the second probe block to which the test signal is applied. The method of claim 8, wherein the first body,
Is a straight pin that moves vertically and electrically connected to or disconnected from the connecting groove,
The contact portion
And a curved pin electrically connecting the connection groove and a portion to which the test signal is applied. The method of claim 1, wherein the test pins,
The socket for a semiconductor chip test having elasticity and being inserted into a corresponding second pinhole among the second pinholes of the second probe block and fixed to the second probe block. The method of claim 1, wherein the chip mounting portion,
A wafer in which the contact holes and the guide holes are formed;
The first probe block,
The first pinholes are formed and a wafer or plastic layer is formed to be stacked to couple the protruding guide pins.
The second probe block,
The semiconductor chip test socket, characterized in that the wafer or plastic layer is formed so that the second pin holes are formed. A first probe block having a plurality of first pin holes penetrating the upper surface and the lower surface, the plurality of guide pins protruding from the upper surface;
A second probe block formed under the first probe block and having a plurality of second pin holes penetrating through an upper surface and a lower surface at positions corresponding to the positions of the first pin holes;
A plurality of test pins respectively inserted through the corresponding first and second pinholes of the first and second pinholes and to which a test signal is applied;
An elastic body providing elasticity between a lower surface of the first probe block and an upper surface of the second probe block;
A test chip is seated, and a plurality of first guide holes into which a plurality of contact holes into which the test pin is inserted and corresponding guide pins of the guide pins are inserted to contact the pad of the test chip and the upper end of the test pin. Chip seating portion is formed for the holes; And
And a support part coupled to the chip seat and having a plurality of second guide holes into which the guide pin is inserted at positions corresponding to the first guide holes. The method of claim 12, wherein the top of the guide pins,
The socket for a semiconductor chip test, characterized in that protruding from the top of the test pins. The method of claim 13, wherein the test pins,
And the guide pins are positioned outside the contact holes before being inserted into the guide holes, and are inserted into the contact holes when the guide pins are inserted into the guide holes. The method of claim 12, wherein the chip mounting portion,
A first insulating layer having a plurality of first holes having the same central axis as the contact holes;
A metal layer formed on an upper surface of the first insulating layer and having a plurality of second holes having the same central axis as the corresponding first hole among the first holes; And
A second insulating layer formed on an upper surface of the metal layer to seat the test chip, and a plurality of third holes having the same central axis as the first hole and the second hole having the same central axis;
The metal layer may include,
Insulating holes penetrating the upper surface and the lower surface formed along the edge of the metal portion surrounding each of the second holes, in order to insulate the metal portion surrounding each of the second holes Test socket. The method of claim 12, wherein the chip mounting portion,
A first insulating layer having a plurality of first holes having the same central axis as the contact holes;
A metal layer formed on an upper surface of the first insulating layer and having a plurality of second holes formed at positions corresponding to the first holes; And
A second insulating layer formed on an upper surface of the metal layer to seat the test chip, and having a plurality of third holes formed at positions corresponding to the first holes and the second holes,
The size of each of the second holes,
And a socket larger than the size of the first hole or the third hole formed at a corresponding position. The method of claim 12,
The upper edges of the guide pins are inclined or rounded, and the edges of the lower surfaces at which the guide pins are inserted into the guide holes are inclined or rounded. A socket for testing semiconductor chips. The method of claim 12, wherein the elastic body,
The socket for semiconductor chip test, characterized in that it is inserted into the groove for the elastic body formed on the lower surface of the first probe block and the upper surface of the second probe block. The method of claim 12, wherein the test pins,
It is an elastic pin,
The pad of the test chip,
A socket for semiconductor chip testing, characterized in that the solder ball shape. The method of claim 12, wherein each of the test pins,
A first body inserted into a corresponding first pin hole among the first pin holes and having an upper end contacting a pad of the seated test chip and a lower end protruding from a lower surface of the first probe block; And
A second body inserted into a corresponding second pinhole of the second pinholes and electrically connected to or separated from the first body,
The second body,
A connection groove in which a first body protruding from the lower surface of the first probe block is inserted into and electrically connected to the first probe block; And
And a contact part electrically connected to the connection groove and elastic and protruding from a lower surface of the second probe block to which the test signal is applied. The method of claim 20, wherein the first body,
Is a straight pin that moves vertically and electrically connected to or disconnected from the connecting groove,
The contact portion
And a curved pin electrically connecting the connection groove and a portion to which the test signal is applied. The method of claim 12, wherein the first probe block,
The first pinholes are formed and a wafer or plastic layer is formed to be stacked to couple the protruding guide pins.
The second probe block,
The semiconductor chip test socket, characterized in that the wafer or plastic layer is formed so that the second pin holes are formed.

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