KR20130053280A - Chip on glass type flexible organic light emitting diodes - Google Patents

Abstract

PURPOSE: A COG(Chip On Glass) type flexible organic light emitting device is provided to prevent the failure of a switching and driving thin film transistor by preventing pressure from being concentrated on a bump. CONSTITUTION: A switching and driving thin film transistor includes a semiconductor layer, a gate electrode, a source electrode, a drain electrode, a gate insulation layer(105), and a first interlayer dielectric layer. A second interlayer dielectric layer covers the source and drain electrodes. A pad terminal is located on a non-display unit and is electrically connected to the switching and driving thin film transistor. An insulation layer is formed on the upper side of the pad terminal and includes a contact hole to expose the pad terminal. A driving integrated circuit(130) includes a bump which is electrically connected to the pad terminal through the contact hole. The thickness of the insulation layer corresponds to the length of the bump.

Description

CIOGE type flexible organic light emitting diodes {Chip on glass type flexible organic light emitting diodes}

The present invention relates to a flexible OLED, and more particularly, to a COG type flexible OLED that directly mounts a drive integrated circuit on a substrate.

Until recently, CRT (cathode ray tube) was mainly used as a display device. However, a flat panel display device such as a plasma display panel (PDP), a liquid crystal display device (LCD), and an organic light emitting diode (OLED) Have been widely studied and used.

Among the above flat panel display devices, an organic light emitting element (hereinafter referred to as OLED) is a self-light emitting element, and a backlight used in a liquid crystal display device which is a non-light emitting element is not required.

In addition, it has a better viewing angle and contrast ratio than liquid crystal display devices, is advantageous in terms of power consumption, can be driven by DC low voltage, has a fast response speed, is resistant to external impacts due to its solid internal components, It has advantages.

Particularly, since the manufacturing process is simple, it is advantageous in that the production cost can be saved more than the conventional liquid crystal display device.

The OLED includes a driver such as a driver IC for driving the OLED, which includes a printed circuit board (PCB) on which components generating various control signals, data signals, and the like are mounted, and an OLED and a printed circuit board. And a driving integrated circuit (IC) for connecting and applying a signal to the wiring of the OLED.

Here, the driving integrated circuit mounting method is classified into a tab automated bonding (TAB) process and a chip on glass (COG) process. These methods are rapidly developing as the use of OLEDs expands.

The TAB type bonds the electrode of the OLED substrate to the driving integrated circuit through an inner lead bonding (OLB) process and an outer lead bonding (OLB) process in which a process alloy is connected between the metal-bonded film and the electrode of the driving integrated circuit. . The ILB process is a process of connecting the film lead and the electrodes of the driving integrated circuit to the bump, and the OLB process is a process of bonding the lead of the TAB package bonded to the electrode to the OLED via the ILB process.

In addition to the TAB type, there is a COG (Chip On Glass) type that directly mounts a driving integrated circuit on an OLED substrate.

COG type is a method of directly attaching driving integrated circuit to OLED substrate using only bump and anisotropic conductive film (ACF) without using the film used in TAB. It can be an advantage.

However, in the COG method, the organic insulating film is stacked as a protective film to protect driving devices such as OLED thin film transistors, so when bumps are connected to the pad part due to the step difference between the pad part where the metal layer is located below and the rest part. There is a disadvantage that a defect occurs.

In particular, flexible OLEDs, which are manufactured to maintain display performance even when bent like paper using flexible materials such as flexible glass substrates or plastics, are rapidly emerging as next-generation flat panel displays. In the case of more pressing bad will occur.

As shown in FIG. 1, the crimping failure causes cracks in the insulating layer for protecting the thin film transistor, which causes a failure of the driving device, thereby lowering the reliability of the OLED.

The present invention has been made to solve the above problems, and a first object of the present invention is to prevent the occurrence of a compression failure in the COG type driving integrated circuit mounting method of the OLED.

Through this, the second object is to prevent the occurrence of defects in the driving element and to improve the reliability of the OLED.

In order to achieve the above object, the present invention provides a COG type flexible organic light emitting diode including a switching and driving thin film transistor and an organic light emitting diode on a first substrate including a display portion and a non-display portion, the semiconductor layer and And a gate electrode, a source and a drain electrode, a gate insulating layer positioned between the semiconductor layer and the gate electrode, and a first interlayer insulating layer positioned between the gate electrode and the source and drain electrodes. A transistor; A second interlayer insulating film covering the source and drain electrodes; A pad terminal positioned in the non-display portion and electrically connected to the switching and driving thin film transistor; An insulating layer formed on the pad terminal and including a contact hole exposing the pad terminal; A driving integrated circuit includes a bump in electrical contact with the pad terminal through the contact hole, and the thickness of the insulating layer provides a COG type flexible organic light emitting diode having a length corresponding to that of the bump.

In this case, the insulating layer is made of the same material as the second interlayer insulating film, and includes a first layer located on the same layer, and a planarization layer is formed on the second interlayer insulating film, and the insulating layer is the planarization layer. It is made of the same material as and further comprises a second layer located on the same layer.

A bank layer is formed on the planarization layer, and the insulating layer is made of the same material as the bank layer, and further includes a third layer located on the same layer, and a spacer is formed on the bank layer. The insulating layer is made of the same material as the spacer, and further includes a fourth layer located on the same layer.

The insulating layer may further include a fifth layer formed of a separate polymer material on the spacer, and the organic light emitting diode may include a first electrode, an organic light emitting layer, and a second electrode. The bank layer is separated for each pixel area.

In addition, the pad terminal and the bump are electrically contacted through an anisotropic conductive film (ACF), and the semiconductor layer is made of polysilicon (p-si), amorphous silicon (a-si), and oxide (oxide). ) And one selected from organic materials.

As described above, the COG type OLED of the present invention forms a plurality of layers corresponding to the length of the bump on the pad terminal connected to the data driving integrated circuit so as to directly support the data driving integrated circuit, thereby driving the data driving integrated circuit. In the process of compressing the pressure, the pressure applied to the data driving integrated circuit may be distributed to the entire data driving integrated circuit. As a result, it is possible to prevent the pressure from concentrating on the bumps, thereby preventing the occurrence of cracks caused by the pressing of the first interlayer insulating film or the gate insulating film.

Therefore, there is an effect that can prevent the occurrence of a failure of the drive element, there is an effect that can improve the reliability of the OLED.

1 is a photograph showing the appearance of a crack of a conventional insulating layer.
2 is a plan view schematically showing an OLED according to an embodiment of the present invention.
3 is a cross-sectional view taken along the line III-III of FIG. 2.
4 is a cross-sectional view of another embodiment of the present invention taken along cut line III-III of FIG. 2;

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

2 is a plan view schematically illustrating a flexible OLED according to an embodiment of the present invention.

As shown, the flexible OLED 100 includes a driving thin film transistor DTr and an organic light emitting diode E formed on the array substrate 101.

Here, the array substrate 101 is divided into a display area AA for displaying an image and a non-display area NA covering an edge of the display area AA. A gate wiring GL is formed, a data wiring DL defining a pixel region P is formed along with the gate wiring GL extending in a second direction crossing the first direction, and the data wiring is formed. A power supply line PL is formed to be spaced apart from the DL and to apply a power supply voltage.

In each pixel area P, a switching thin film transistor STr connected to the two wirings is formed at a portion where the gate wiring GL and the data wiring DL intersect each other, and the switching thin film transistor STr is a driving thin film. The transistor DTr and the storage capacitor StgC are connected to each other, and the driving thin film transistor DTr is connected between the power supply line PL and the organic light emitting diode E.

In the non-display area NA outside the display area AA, a data driving integrated circuit 130 for applying a data signal voltage to the data wiring DL is mounted on the array substrate 101. A gate driving integrated circuit 120 that applies a gate signal voltage to the gate line GL is formed at one edge perpendicular to the edge where the 130 is formed. The plurality of pixel areas P are divided and scanned.

In addition, a power supply line 140 for supplying power to each electrode of the organic light emitting diode E is formed at the other edge perpendicular to the edge where the data driving integrated circuit 130 of the non-display area NA is formed. The gate and data driving integrated circuits 120 and 130 and the power supply line 140 process signals provided from the outside through the pad unit PA of the non-display area NA.

A pad electrode 135 is formed in the pad part PA to be electrically connected to the FPC 160 in the form of a film. A signal is input from the outside through the FPC 160, and the pad electrode 135 and the power supply line are provided. 140 and the gate and data driver integrated circuits 120 and 130 are connected to the pad electrodes 135 through the power link wiring 150, respectively.

The gate and data driving integrated circuits 120 and 130 are connected to the gates and the data lines GL and DL of the pixel region P through gate and data signal link wirings (not shown), respectively.

When a signal is input from the outside to the power supply line 140 and the gate and data driving integrated circuits 120 and 130 through the pad electrode 135, the gate driving integrated circuit 120 and the data driving integrated circuit 130 are scanned. And the data signal are supplied to the gate wiring GL and the data wiring DL, respectively.

Therefore, when a signal is applied to each pixel area P through the gate line GL, the switching thin film transistor STr is turned on for each pixel area P, and the signal of the data line DL is driven. Since the driving thin film transistor DTr is turned on by being transferred to the gate electrode of the thin film transistor DTr, light is emitted through the organic light emitting diode E.

A passivation layer (not shown) is formed on the driving and switching thin film transistors DTr and STr and the organic light emitting diode E of the flexible OLED 100, and a thin film type protection is formed on the passivation layer (not shown). The film 102 is provided, and the array substrate 101 is encapsulated.

The flexible OLED 100 of the present invention comprises a COG type driving integrated circuit mounting method in which the gate and data driving integrated circuits 120 and 130 are directly mounted on the array substrate 101. Compared with the simple structure, the volume can be reduced.

In particular, the present invention can prevent the occurrence of poor compression in the process of mounting the driving integrated circuit (120, 130). As a result, cracks in the insulating layers 105 and 109a (see FIG. 3) formed to protect the driving and switching thin film transistor DTr may be prevented from occurring.

This distributes the pressure concentrated in the bumps 131a and 131b of the driving integrated circuits 120 and 130 to the entire driving integrated circuits 120 and 130 in the process of mounting the driving integrated circuits 120 and 130. By doing so.

This will be described in more detail with reference to FIG.

3 is a cross-sectional view of a portion of FIG. 2;

Prior to the description, the flexible OLED 100 is divided into a top emission type and a bottom emission type according to the transmission direction of the emitted light, and the bottom emission method has high stability and freedom of processing. On the other hand, the research on the bottom emission method is actively conducted. Hereinafter, the lower light emitting method will be described as an example.

As shown, a semiconductor layer 103 is formed in the pixel region (P of FIG. 2) of the display area AA displaying an image of the array substrate 101, and the semiconductor layer 103 is made of silicon. The central portion includes an active region 103a constituting a channel and source and drain regions 103b and 103c doped with a high concentration of impurities on both sides of the active region 103a.

The gate insulating layer 105 is formed on the semiconductor layer 103.

A gate wiring (GL in FIG. 2) is formed on the gate insulating layer 105 to extend in one direction with the gate electrode 107 in correspondence with the active region 103a of the semiconductor layer 103.

In addition, a first interlayer insulating film 109a is formed on the entire surface of the gate electrode 107 and the gate wiring (GL in FIG. 2), wherein the first interlayer insulating film 109a and the gate insulating film 105 below are active. First and second semiconductor layer contact holes 111a and 111b exposing the source and drain regions 103b and 103c located on both sides of the region 103a, respectively.

Next, an upper portion of the first interlayer insulating layer 109a including the first and second semiconductor layer contact holes 111a and 111b is spaced apart from each other and exposed through the first and second semiconductor layer contact holes 111a and 111b. And source and drain electrodes 113 and 115 in contact with the drain regions 103b and 103c, respectively.

And a second interlayer having a drain contact hole 117 exposing the drain electrode 115 over the first interlayer insulating film 109a exposed between the source and drain electrodes 113 and 115 and the two electrodes 113 and 115. The planarization layer 119 is formed to planarize the level difference between the insulating film 109b and the surface of the array substrate 101.

At this time, the semiconductor layer 103 including the source and drain electrodes 113 and 115 and the source and drain regions 103b and 103c in contact with the electrodes 113 and 115 and the gate electrode formed on the semiconductor layer 103. 107 forms a driving thin film transistor DTr.

Although not shown, the switching thin film transistor (STr of FIG. 2) has the same structure as the driving thin film transistor DTr and is connected to the driving thin film transistor DTr.

Here, the switching thin film transistor (STr of FIG. 2) and the driving thin film transistor (DTr) are shown as an example of a top gate type in which the semiconductor layer 103 is formed of a polysilicon (p-si) semiconductor layer. It may be formed as a bottom gate type.

In addition, the switching thin film transistor (STr of FIG. 2) and the driving thin film transistor (DTr) may be formed of amorphous silicon (a-si) of pure water and impurities, or may be formed of an oxide semiconductor layer, or a pentacin ( It may be formed of an organic semiconductor layer such as pentacene or polythiophene.

The first electrode is connected to the drain electrode 115 of the driving thin film transistor DTr through the drain contact hole 117, and forms an anode in an area that substantially displays an image on the planarization layer 119. A second electrode 211 is formed, and the first electrode 211 is formed of a material having a relatively high work function, for example, and serves as one component constituting the organic light emitting diode (E).

The first electrode 211 is formed for each pixel region (P in FIG. 2), and a bank layer 121 is positioned between the first electrodes 211 formed for each pixel region (P in FIG. 2). .

That is, the first electrode 211 is formed in a structure in which the bank layer 121 serves as a boundary portion for each pixel region (P in FIG. 2) and is separated for each pixel region P. As shown in FIG.

Here, the bank layer 121 may be made of polyacrylates, epoxy resins, phenolic resins, polyamides resins, polyimides resins, and unsaturated polys. Unsaturated polyesters resin, poly (phenylenethers) resin, polyphenylenesulfide resin (poly (phenylenesulfides) resin) and benzocyclobutene (benzocyclobutene (BCB)) It may be formed of a material, or may be made of graphite powder, gravure ink, black spray, black enamel.

The organic light emitting layer 213 is formed on the first electrode 211.

Here, the organic light emitting layer 213 may be composed of a single layer made of a light emitting material, and in order to increase the light emitting efficiency, a hole injection layer, a hole transport layer, and an emitting material layer It may be composed of multiple layers of an electron transport layer and an electron injection layer.

The organic light emitting layer 213 expresses the colors of red (R), green (G), and blue (B). In general, red (R) and green (G) colors are applied to each pixel region (P of FIG. 2). ), A separate organic material emitting blue (B) color is used as a pattern.

A second electrode 215 forming a cathode is formed on the organic light emitting layer 213.

At this time, the second electrode 215 may be made of an opaque conductive material, a metal material having a relatively low work function, for example, aluminum (Al), aluminum alloy (AlNd), silver (Ag), magnesium (Mg) , Gold (Au), aluminum magnesium alloy (AlMg) is preferably formed of one material selected from.

Therefore, the light emitted from the organic light emitting layer 213 is driven by the bottom emission method emitted toward the transparent first electrode 211.

When a predetermined voltage is applied to the first electrode 211 and the second electrode 215 according to the selected color signal, the flexible OLED 100 may inject holes and second electrodes 215 injected from the first electrode 211. Electrons provided from the organic light emitting layer 213 are transported to form an exciton, and when the exciton transitions from the excited state to the ground state, light is generated and emitted in the form of visible light.

In this case, since the emitted light passes through the transparent first electrode 211 to the outside, the flexible OLED 100 implements an arbitrary image.

In addition, a protective film 102 in the form of a thin thin film is formed on the driving thin film transistor DTr and the organic light emitting diode E. The flexible OLED 100 of the present invention has a protective film 102 which is an upper encapsulation layer. ) Is encapsulated.

Thus, the flexible OLED 100 according to the embodiment of the present invention can be encapsulated through the protective film 102, so that the OLED 100 can be formed in a thin thickness compared to the case of encapsulation with glass, OLED The overall thickness of 100 can be reduced.

In addition, the OLED 100 has a flexible characteristic, thereby implementing a flexible OLED that can maintain the display performance as it is, even if bent like paper.

Here, the array substrate 101 is made of a flexible glass substrate or a plastic material having flexible characteristics so that the display performance can be maintained even when the flexible OLED 100 is bent like a paper.

In the non-display area NA outside the display area AA of the array substrate 101, terminals (not shown) of the data driving integrated circuit 130 are driven from an external power source (not shown) by bump bonding. The first and second pad terminals 133 and 135 for applying a signal voltage to the transistor DTr and the organic light emitting diode E are connected to each other.

The second pad terminal 135 is also connected to the FPC 160 for connecting with an external power source (not shown).

Here, the first pad terminal 133 and the second pad terminal 135 are formed in plural, and the first pad terminal 133 and the second pad terminal 135 are the source and the drain of the driving thin film transistor DTr. It is made of the same material in the same layer as the electrodes 113 and 115.

A plurality of insulating layers are stacked on the first pad terminal 133 and the second pad terminal 135, and the first layer is made of the same material as the second interlayer insulating layer 109b of the display area AA. The second layer is made of the same material as the planarization layer 119 of the display area AA.

The third layer is made of the same material as the bank layer 121 of the display area AA.

The first to third contact holes 125a exposing the first pad terminal 133 and the second pad terminal 135 to the second interlayer insulating layer 109b, the planarization layer 119, and the bank layer 121, respectively. 125b, 125c) are formed. The first to third contact holes 125a, 125b, and 125c may include a second interlayer insulating layer 109b and a planarization layer 119 stacked on the first pad terminal 133 and the second pad terminal 135. The bank layer 121 is partially etched, and the first contact hole 125a exposes the first pad terminal 133, and the second contact hole 125b forms one side of the second pad terminal 135. The third contact hole 125c exposes the other side of the second pad terminal 135.

The ACF 170 including the conductive balls 171 is coated on the bank layer 121 including the first to third contact holes 125a, 125b, and 125c to cover the first contact holes 125a. The first bump 131a connected to one terminal (not shown) of the data driving integrated circuit 130 comes into contact with each other, and the data passes through the second contact hole 125b exposing one side of the second pad terminal 135. The second bump 131b connected to the other terminal (not shown) of the driving integrated circuit 130 comes into contact with each other.

In this case, the first bump 131a is an output pad terminal of the data driving integrated circuit 130, the second bump 131b is an input pad terminal of the data driving integrated circuit 130, and the first and second pad terminals ( 133 and 135 and the first and second bumps 131a and 131b are electrically connected to each other by the conductive balls 171 compressed therebetween.

In addition, an auxiliary pad electrode 137 is formed to contact the other side of the second pad terminal 135 through the third contact hole 125c of the pad portion PA exposing the other side of the second pad terminal 135. In addition, the auxiliary pad electrode 137 serves not only to transfer an external voltage (not shown) to the second pad terminal 135, but also to block the second pad terminal 135 from the outside, so that the second pad terminal 135 is closed. To prevent propagation.

In addition, the ACF 170 including the conductive balls 171 is coated on the auxiliary pad electrode 137, so that the auxiliary pad electrodes 137 are electrically connected to each other by the FPC 160 and the conductive balls 171. Will be.

In this case, the thicknesses of the second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 correspond to the lengths of the first and second bumps 131a and 131b of the data driving integrated circuit 130. When the lengths of the first and second bumps 131a and 131b are short, the bank layer 121 may be removed from the first pad terminal 133 and the second pad terminal 135, or the first and second bumps 131a may be removed. If the length of the 131b is long, a separate layer (not shown) made of a polymer may be further included on the bank layer 121.

Therefore, since the data driving integrated circuit 130 is in contact with the bank layer 121, the data driving integrated circuit 130 may drive the pressure concentrated on the first and second bumps 131a and 131b in the process of mounting the data driving integrated circuit 130. Distributed to the integrated circuit 130 as a whole.

As a result, in the process of mounting the data driver integrated circuit 130, it is possible to prevent the occurrence of a compression failure.

In more detail, in the process of mounting the data driving integrated circuit 130 in the COG type on the array substrate 101, the data driving integrated circuit 130 is disposed on the bank layer 121 coated with the ACF 170. The first and second bumps 131a and 131b of the first and second contact holes 125a and 125b are aligned with each other and the data driving integrated circuit 130 is compressed. In this case, the data driving integrated circuit 130 ), The pressure due to the compression concentrates on the first and second bumps 131a and 131b protruding from the data driving integrated circuit 130.

As the first and second bumps 131a and 131b are formed to have a small area, the first and second bump terminals 133 and 135 may be formed by the pressure concentrated on the first and second bumps 131a and 131b. Cracks are generated by being pressed by the first interlayer insulating film 109a or the gate insulating film 105 located below.

As such, when cracks occur in the first interlayer insulating film 109a and the gate insulating film 105, defects in the switching and driving thin film transistors (STr and DTr in FIG. 2) may occur, thereby lowering the reliability of the flexible OLED 100. Let's go.

In an exemplary embodiment of the present invention, the second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 are stacked on the first and second pad terminals 133 and 135, and the second interlayer insulating film 109b is formed. The thicknesses of the planarization layer 119 and the bank layer 121 correspond to the lengths of the first and second bumps 131a and 131b of the data driving integrated circuit 130, thereby allowing the data driving integrated circuit 130 to have a bank layer. In contact with 121, the pressure applied to the data driving integrated circuit 130 in the process of compressing the data driving integrated circuit 130 is distributed to the entire data driving integrated circuit 130.

Therefore, concentration of pressure on the first and second bumps 131a and 131b can be prevented, and cracks caused by being pressed against the first interlayer insulating film 109a or the gate insulating film 105 can be prevented. .

Through this, the failure of the switching and driving thin film transistors (STr and DTr of FIG. 2) may be prevented from occurring, and the reliability of the flexible OLED 100 may be improved.

Here, since the first and second bumps 131a and 131b of the data driving integrated circuit 130 are formed to have a length of about 10 μm, the second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 are formed. ) Is preferably formed to have a total thickness of about 10 μm.

In this case, the thickness of any one of the second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 may be 10 μm, and the second interlayer insulating film 109b may have a thickness of about 2 μm. The planarization layer 119 may be formed to have a thickness of about 3 μm and the bank layer 121 may have a thickness of about 5 μm.

When the second interlayer insulating film 109b is formed to have a thickness similar to that of the first and second pad terminals 133 and 135, the total thickness of the planarization layer 119 and the bank layer 121 is 10 μm. You may.

4 is a cross-sectional view of another embodiment of the present invention taken along cut line III-III of FIG. 2.

In this case, in order to avoid redundant description, the same reference numerals are assigned to the same parts that play the same role as the description of FIGS.

As shown in the drawing, the display area AA displaying an image of the array substrate 101 includes a semiconductor layer 103, a gate electrode 107 formed on the semiconductor layer 103, and a source of the semiconductor layer 103. A driving thin film transistor DTr including source and drain electrodes 113 and 115 in contact with the drain regions 103b and 103c, respectively, is formed.

At this time, the semiconductor layer 103 is composed of an active region 103a corresponding to the gate electrode 107 and source and drain regions 103b and 103c on both sides thereof, and between the semiconductor layer 103 and the gate electrode 107. The gate insulating film 105 is interposed therebetween, and the first interlayer insulating film 109a is interposed between the gate electrode 107 and the source and drain electrodes 113 and 115, and the source and drain electrodes 113 and 115 are firstly interposed therebetween. And the source and drain regions 103b and 103c through the second semiconductor layer contact holes 111a and 111b.

A second interlayer insulating film 109b and a planarization layer 119 having a drain contact hole 117 exposing the drain electrode 115 and a planarization layer 119 are formed on the first interlayer insulating film 109a. The switching thin film transistor (STr of FIG. 2) has the same structure as the driving thin film transistor DTr and is connected to the driving thin film transistor DTr.

The first electrode is connected to the drain electrode 115 of the driving thin film transistor DTr through the drain contact hole 117, and forms an anode in an area that substantially displays an image on the planarization layer 119. 211 is formed.

The first electrode 211 is made of a material having a relatively high work function value, for example.

The first electrode 211 is formed for each pixel region (P in FIG. 2), and the bank layer 121 is positioned between the first electrodes 211 formed for each pixel region (P in FIG. 2). The spacer 127 is positioned on the layer 121.

Here, the bank layer 121 and the spacer 127 may be made of the same material in the same process.

The spacer 127 serves to prevent the organic light emitting layer 213 from being damaged by physical force after the array substrate 101 is encapsulated through the protective film 102, which will be described later, and the bank layer 121. ) May be defined separately from the pixel region (P of FIG. 2). The spacer 127 may be positioned for each pixel region (P of FIG. 2), but may be irregularly positioned for every two pixel regions (P of FIG. 2) or at regular intervals.

The organic light emitting layer 213 is formed on the first electrode 211.

Here, the organic light emitting layer 213 may be composed of a single layer made of a light emitting material, and in order to increase the light emitting efficiency, a hole injection layer, a hole transport layer, and an emitting material layer It may be composed of multiple layers of an electron transport layer and an electron injection layer.

The organic light emitting layer 213 expresses the colors of red (R), green (G), and blue (B). As a general method, red (R), green (G), and blue for each pixel area (P). (B) A pattern of organic substances emitting color is used.

A second electrode 215 forming a cathode is formed on the organic light emitting layer 213.

At this time, the second electrode 215 may be made of an opaque conductive material, for example, aluminum (Al), aluminum alloy (AlNd), silver (Ag), magnesium (Mg) which is a metal material having a relatively low work function value. , Gold (Au), aluminum magnesium alloy (AlMg) is preferably formed of one material selected from.

Therefore, the light emitted from the organic light emitting layer 213 is driven by the bottom emission method emitted toward the transparent first electrode 211.

In addition, a protective film 102 in the form of a thin thin film is formed on the driving thin film transistor DTr and the organic light emitting diode E. The flexible OLED 100 of the present invention has a protective film 102 which is an upper encapsulation layer. ) Is encapsulated.

Here, the array substrate 101 is made of a flexible glass substrate or a plastic material having flexible characteristics so that the display performance can be maintained even when the flexible OLED 100 is bent like a paper.

In the non-display area NA outside the display area AA of the array substrate 101, terminals (not shown) of the data driving integrated circuit 130 are driven from an external power source (not shown) by bump bonding. The first and second pad terminals 133 and 135 for applying a signal voltage to the transistor DTr and the organic light emitting diode E are connected to each other.

The second pad terminal 135 is also connected to the FPC 160 for connecting with an external power source (not shown).

A plurality of insulating layers are stacked on the first pad terminal 133 and the second pad terminal 135, and the first layer is made of the same material as the second interlayer insulating layer 109b of the display area AA. The second layer is made of the same material as the planarization layer 119 of the display area AA.

The third layer is made of the same material as the bank layer 121 of the display area AA.

The first to third contact holes 125a exposing the first pad terminal 133 and the second pad terminal 135 to the second interlayer insulating layer 109b, the planarization layer 119, and the bank layer 121, respectively. 125b, 125c) are formed.

The first to third contact holes 125a, 125b, and 125c may include a second interlayer insulating layer 109b and a planarization layer 119 stacked on the first pad terminal 133 and the second pad terminal 135. The bank layer 121 is partially etched, and the first contact hole 125a exposes the first pad terminal 133, and the second contact hole 125b forms one side of the second pad terminal 135. The third contact hole 125c exposes the other side of the second pad terminal 135.

The ACF 170 including the conductive balls 171 is coated on the bank layer 121 including the first to third contact holes 125a, 125b, and 125c to cover the first contact holes 125a. The first bump 131a connected to one terminal (not shown) of the data driving integrated circuit 130 comes into contact with each other, and the data passes through the second contact hole 125b exposing one side of the second pad terminal 135. The second bump 131b connected to the other terminal (not shown) of the driving integrated circuit 130 comes into contact with each other.

In this case, the first and second pad terminals 133 and 135 and the first and second bumps 131a and 131b are electrically connected to each other by the conductive balls 171 compressed therebetween.

In addition, an auxiliary pad electrode 137 is formed in contact with the other side of the second pad terminal 135 through the third contact hole 125c of the pad portion PA exposing the other side of the second pad terminal 133. Also, the ACF 170 including the conductive balls 171 is coated on the auxiliary pad electrodes 137, so that the auxiliary pad electrodes 137 are electrically connected to each other by the FPC 160 and the conductive balls 171. do.

In this case, a fourth layer including the same material is formed on the bank layer 121 and the same layer as the spacer 127 of the display area. The second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 are formed. The thickness of the spacer 127 corresponds to the lengths of the first and second bumps 131a and 131b of the data driving integrated circuit 130.

Therefore, since the data driver integrated circuit 130 comes into contact with the spacer 127, the data driver integrated pressure is concentrated on the first and second bumps 131a and 131b in the process of mounting the data driver integrated circuit 130. To be distributed throughout the circuit 130.

As a result, in the process of mounting the data driver integrated circuit 130, it is possible to prevent the occurrence of a compression failure.

That is, according to the present invention, the second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 are stacked on the first and second pad terminals 133 and 135, and then on the bank layer 121. The spacers 127 are formed, and the thicknesses of the second interlayer insulating film 109b, the planarization layer 119, the bank layer 121, and the spacer 127 are determined by the first and second bumps of the data driving integrated circuit 130. The pressure applied to the data driving integrated circuit 130 in the process of compressing the data driving integrated circuit 130 by contacting the spacer 127 by contacting the spacers 127 by corresponding to the lengths of the 131a and 131b. The data driving integrated circuit 130 is distributed throughout.

Therefore, concentration of pressure on the first and second bumps 131a and 131b can be prevented, and cracks due to the pressing of the first interlayer insulating film 109a or the gate insulating film 105 can be prevented. .

Through this, the failure of the switching and driving thin film transistors (STr and DTr of FIG. 2) may be prevented from occurring, and the reliability of the flexible OLED 100 may be improved.

Here, since the first and second bumps 131a and 131b of the data driving integrated circuit 130 are formed to have a length of about 10 μm, the second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 are formed. And the total thickness of the spacer 127 is also preferably about 10 μm.

In this case, the second interlayer insulating film 109b may be formed to have a thickness of about 2 μm, the planarization layer 119 may be formed to have a thickness of about 3 μm, and the bank layer 121 may have a thickness of about 2 μm. The thickness of 127 may be formed to have a thickness of about 3 μm.

When the second interlayer insulating film 109b is formed to have a thickness similar to that of the first and second pad terminals 133 and 135, the total thickness of the planarization layer 119, the bank layer 121, and the spacer 127 is It may be formed to have a 10㎛, if the length of the first and second bumps (131a, 131b) is longer, further comprising a separate fifth layer (not shown) made of a polymer on the upper portion of the spacer 127. It may be.

As described above, the flexible OLED 100 of the present invention includes a plurality of layers (ie, corresponding to the lengths of the bumps 131a and 131b on the pad terminals 133 and 135 so as to directly support the data driving integrated circuit 130). By forming the 109b, 119, 121, and 127, the pressure applied to the data driving integrated circuit 130 in the process of compressing the data driving integrated circuit 130 may be distributed to the entire data driving integrated circuit 130. .

As a result, concentration of pressure on the bumps 131a and 131b can be prevented, and cracks due to the pressing of the first interlayer insulating film 109a or the gate insulating film 105 can be prevented, thereby switching and driving. The failure of the thin film transistors (STr and DTr in FIG. 2) may be prevented from occurring, and the reliability of the flexible OLED 100 may be improved.

The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

100: OLED, 101: substrate, 102: protective film
103: semiconductor layer 103a: active region, 103b, 103c: source and drain regions
105: gate insulating film, 107: gate electrode, 109a, 109b: first and second interlayer insulating films
111a and 111b: first and second semiconductor layer contact holes,
113, 115: source and drain electrodes,
117: drain contact hole, 119: planarization layer, 121: bank layer
125a, 125b, 125c: first to third contact holes
130: data driving integrated circuit, 131a, 131b: first and second bumps
133 and 135: first and second terminals
137: auxiliary pad electrode
160: FPC, 170: ACF (171: Challenge Ball)
211: first electrode, 213: organic light emitting layer, 215: second electrode
DTr: driving thin film transistor, E: organic light emitting diode
AA: display area, NA: non-display area

Claims (9)

In the COG type flexible organic light emitting device comprising a switching and driving thin film transistor and an organic light emitting diode on a first substrate including a display portion and a non-display portion,
The switching device including a semiconductor layer, a gate electrode, a source and a drain electrode, a gate insulating film positioned between the semiconductor layer and the gate electrode, and a first interlayer insulating film positioned between the gate electrode and the source and drain electrodes. And a driving thin film transistor;
A second interlayer insulating film covering the source and drain electrodes; A pad terminal positioned in the non-display portion and electrically connected to the switching and driving thin film transistor;
An insulating layer formed on the pad terminal and including a contact hole exposing the pad terminal;
A driving integrated circuit including a bump in electrical contact with the pad terminal through the contact hole
And a thickness of the insulating layer corresponding to the length of the bumps.
The method of claim 1,
The insulating layer is made of the same material as the second interlayer insulating film, COG type flexible organic light emitting device comprising a first layer located on the same layer.
3. The method of claim 2,
A planarization layer is formed on the second interlayer insulating film, and the insulation layer is made of the same material as the planarization layer and further comprises a second layer positioned on the same layer.
The method of claim 3, wherein
A bank layer is formed on the planarization layer, and the insulating layer is made of the same material as the bank layer, and further comprises a third layer disposed on the same layer COG type flexible organic light emitting device.
The method of claim 4, wherein
A spacer is formed on the bank layer, and the insulating layer is made of the same material as the spacer and further comprises a fourth layer located on the same layer COG type flexible organic light emitting device.
The method of claim 5, wherein
The insulating layer is a COG type flexible organic light emitting device further comprising a fifth layer made of a separate polymer material on the spacer.
The method of claim 4, wherein
The organic light emitting diode includes a first electrode, an organic light emitting layer, and a second electrode, and the first electrode is separated by pixel region through the bank layer.
The method of claim 1,
The pad terminal and the bump are in electrical contact via an anisotropic conductive film (ACF) COG type flexible organic light emitting device.
The method of claim 1,
The semiconductor layer is a COG type flexible organic light emitting device comprising one selected from polysilicon (p-si), amorphous silicon (a-si), oxide (oxide), organic (organic).

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