KR101860036B1 - Chip on glass type flexible organic light emitting diodes - Google Patents

Abstract

The present invention relates to a flexible OLED, and more particularly to a COG type flexible OLED that directly mounts a driving integrated circuit on a substrate.
A feature of the present invention resides in that in a COG type flexible OLED, a plurality of layers corresponding to the length of a bump are formed on a pad terminal connected to a data driving integrated circuit so as to directly support the data driving integrated circuit, The pressure applied to the data driving integrated circuit can be dispersed throughout the data driving integrated circuit during the pressing process.
As a result, it is possible to prevent the pressure from concentrating on the bump, thereby preventing the generation of cracks due to the pressing of the first interlayer insulating film or the gate insulating film, preventing defective driving devices, The reliability of the OLED can be improved.

Description

[0001] The present invention relates to a flexible organic light emitting diode (OLED)

The present invention relates to a flexible OLED, and more particularly to a COG type flexible OLED that directly mounts a driving integrated circuit on a substrate.

Until recently, CRT (cathode ray tube) was mainly used as a display device. However, a flat panel display device such as a plasma display panel (PDP), a liquid crystal display device (LCD), and an organic light emitting diode (OLED) Have been widely studied and used.

Among the above flat panel display devices, an organic light emitting element (hereinafter referred to as OLED) is a self-light emitting element, and a backlight used in a liquid crystal display device which is a non-light emitting element is not required.

In addition, it has a better viewing angle and contrast ratio than liquid crystal display devices, is advantageous in terms of power consumption, can be driven by DC low voltage, has a fast response speed, is resistant to external impacts due to its solid internal components, It has advantages.

Particularly, since the manufacturing process is simple, it is advantageous in that the production cost can be saved more than the conventional liquid crystal display device.

The OLED includes a driver such as a driver IC for driving an OLED. The driver includes a printed circuit board (PCB) on which components for generating various control signals, data signals, and the like are mounted, And a driving IC for applying a signal to the wiring of the OLED.

Here, the driving integrated circuit mounting method is classified into a TAB (Tape Automated Bonding) process and a COG (Chip On Glass) process. These schemes are rapidly evolving as OLED applications expand.

In the TAB type, the substrate of the OLED and the electrodes of the driving integrated circuit are adhered to each other through an ILB (Inner Lead Bonding) process and an OLB (Outer Lead Bonding) process in which a process alloy is connected between the metal line- . The ILB process is a process of connecting electrodes of a film lead and a driving integrated circuit with bumps, and the OLB process is a process of bonding a lead of a TAB package bonded to an electrode to an OLED via an ILB process.

In addition to the TAB type, there is a COG (Chip On Glass) type in which a driving integrated circuit is directly mounted on a substrate of an OLED.

The COG type is a method of directly bonding a driving integrated circuit to a substrate of an OLED using only bumps and anisotropic conductive film (ACF) without using a film used in a TAB, and is simpler in structure and less bulky than TAB It is an advantage.

However, in the COG method, since an organic insulating film or the like is laminated as a protective film for protecting a driving element such as a thin film transistor of an OLED, when a bump or the like is connected to a pad portion due to a step between the pad portion where the metal layer is located and the remaining portion, There is a drawback that defects are generated.

In particular, in recent years, flexible OLEDs, which are manufactured by using a flexible material such as a flexible glass substrate or plastic and capable of maintaining the display performance even when bent like paper, are rapidly emerging as a next generation flat panel display device. Resulting in the occurrence of a larger number of defective crimping.

As shown in FIG. 1, this defective bonding causes a crack in the insulating layer for protecting the thin film transistor, which causes defective driving elements, thereby lowering the reliability of the OLED.

SUMMARY OF THE INVENTION It is a first object of the present invention to provide a method of mounting a COG type driving integrated circuit of an OLED in order to prevent a defective bonding.

It is a second object of the present invention to prevent the occurrence of defective driving devices, thereby improving the reliability of the OLED.

In order to achieve the above object, the present invention provides a COG type flexible organic light emitting device including a switching and driving thin film transistor and an organic light emitting diode on a first substrate including a display portion and a non-display portion, A gate electrode, source and drain electrodes, a gate insulating film positioned between the semiconductor layer and the gate electrode, and a first interlayer insulating film located between the gate electrode and the source and drain electrodes, A transistor; A second interlayer insulating film covering the source and drain electrodes; A pad terminal located in the non-display portion and electrically connected to the switching and driving thin film transistor; An insulating layer formed on the pad terminal and including a contact hole exposing the pad terminal; And a driving integrated circuit including bumps electrically contacting the pad terminal through the contact hole, wherein the thickness of the insulating layer corresponds to the length of the bump.

In this case, the insulating layer is formed of the same material as the second interlayer insulating film, and includes a first layer located on the same layer, a planarization layer is formed on the second interlayer insulating film, And a second layer disposed on the same layer.

A bank layer is formed on the planarization layer. The insulation layer is formed of the same material as the bank layer, and further includes a third layer disposed on the same layer. A spacer is formed on the bank layer. The insulating layer is made of the same material as the spacer, and further includes a fourth layer located on the same layer.

The organic light emitting diode may include a first electrode, an organic light emitting layer, and a second electrode. The first electrode may include a first electrode, a second electrode, and a second electrode. Are separated by the pixel region through the bank layer.

The pad terminal and the bump are electrically contacted through an anisotropic conductive film (ACF), and the semiconductor layer is formed of polysilicon (p-si), amorphous silicon (a-si), oxide ), And organic (organic).

As described above, the COG type OLED of the present invention forms a plurality of layers corresponding to the length of the bumps on the pad terminals connected to the data driving integrated circuit so as to directly support the data driving integrated circuit, The pressure applied to the data driving integrated circuit can be dispersed throughout the data driving integrated circuit. Accordingly, it is possible to prevent the pressure from concentrating on the bump, and it is possible to prevent a crack caused by the pressing of the first interlayer insulating film or the gate insulating film.

Therefore, it is possible to prevent the defective driving device from occurring, and it is possible to improve the reliability of the OLED.

1 is a photograph showing a state where a crack of a conventional insulating layer is generated.
2 is a plan view schematically illustrating an OLED according to an embodiment of the present invention.
3 is a cross-sectional view taken along line III-III in FIG. 2;
4 is a cross-sectional view of another embodiment of the present invention cut along the cutting line III-III in Fig. 2;

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

2 is a plan view schematically showing a flexible OLED according to an embodiment of the present invention.

As shown, the flexible OLED 100 includes a driving thin film transistor DTr and an organic light emitting diode E on an array substrate 101.

Here, the array substrate 101 is divided into a display area AA for displaying an image and a non-display area NA for covering an edge of the display area AA. In the display area AA, And a data line DL extending in a second direction intersecting the first direction and defining a pixel region P in addition to the gate line GL is formed in the data line DL, A power supply line PL for applying a power supply voltage is formed.

In each pixel region P, a switching thin film transistor STr connected to the two lines is formed at a portion where the gate line GL and the data line DL intersect each other. The switching thin film transistor STr includes a thin film transistor A transistor DTr and a storage capacitor StgC and the driving thin film transistor DTr is connected between the power supply line PL and the organic electroluminescent diode E. [

A data driving integrated circuit 130 for applying a data signal voltage to the data line DL is mounted on the array substrate 101 in a non-display area NA outside the display area AA, A gate driving integrated circuit 120 for applying a gate signal voltage to the gate line GL is formed on one edge of the pixel region P perpendicular to the edge where the pixel region 130 is formed.

A power supply line 140 for supplying power to each electrode of the organic light emitting diode E is formed on the other edge of the non-display area NA perpendicular to the edge where the data driving integrated circuit 130 is formed, The gate and data driving integrated circuits 120 and 130 and the power supply line 140 process a signal provided from the outside through the pad portion PA of the non-display area NA.

The pad unit PA is formed with a pad electrode 135 to be electrically connected to the FPC 160 in the form of a film. A signal is inputted from the outside through the FPC 160, The data driver IC 140 and the gate and data driver ICs 120 and 130 are connected to the pad electrode 135 through the power supply wiring line 150, respectively.

The gate and data driving integrated circuits 120 and 130 are connected to gates and data lines GL and DL of the pixel region P through gate and data signal link wiring lines (not shown), respectively.

The gate drive integrated circuit 120 and the data drive integrated circuit 130 receive the scan signal when the signals are inputted from the outside to the power supply line 140 and the gate and data drive integrated circuits 120 and 130 through the pad electrode 135. [ And the data signal to the gate wiring GL and the data wiring DL, respectively.

Therefore, in each pixel region P, when a signal is applied through the gate line GL, the switching thin film transistor STr is turned on for each pixel region P, and the signal of the data line DL is driven And is transmitted to the gate electrode of the thin film transistor DTr so that the driving thin film transistor DTr is turned on to emit light through the organic light emitting diode E.

A passivation layer (not shown) is formed on the flexible OLED 100 and on the switching thin film transistors DTr and STr and the organic light emitting diode E. A passivation layer A film 102 is provided, and the array substrate 101 is encapsulated.

The flexible OLED 100 according to the present invention is implemented by a COG type driver integrated circuit mounting method in which gate and data driving integrated circuits 120 and 130 are directly mounted on an array substrate 101. This COG type is a TAB type The structure is simple and the volume is reduced.

Particularly, the present invention can prevent the occurrence of defective pressing in the process of mounting the driving integrated circuits 120 and 130. As a result, it is possible to prevent the occurrence of cracks in the insulating films 105 and 109a (see FIG. 3) formed for protecting the driving and switching thin film transistor DTr.

This is because the pressure concentrated on the bumps 131a and 131b (see FIG. 3) of the drive integrated circuits 120 and 130 during the process of mounting the drive integrated circuits 120 and 130 is distributed to the entire drive integrated circuits 120 and 130 .

This will be described in more detail with reference to FIG.

3 is a cross-sectional view of part of Fig.

Prior to the description, the flexible OLED 100 is divided into a top emission type and a bottom emission type according to the transmission direction of the emitted light. The lower emission type has a high stability and a high degree of freedom in the process. , And studies on the bottom emission type are being actively carried out. Hereinafter, the present invention will be described by way of an example of a bottom emission type.

As shown in the figure, a semiconductor layer 103 is formed in a pixel region (P in FIG. 2) of a display region AA for displaying an image of the array substrate 101. The semiconductor layer 103 is made of silicon, The central portion is composed of an active region 103a constituting a channel and source and drain regions 103b and 103c doped with impurities at high concentration on both sides of the active region 103a.

A gate insulating layer 105 is formed on the semiconductor layer 103.

A gate wiring (GL in FIG. 2) extending in one direction with respect to the active region 103a of the semiconductor layer 103 is formed on the gate insulating film 105.

A first interlayer insulating film 109a is formed on the entire upper surface of the gate electrode 107 and the gate wiring line GL in FIG. 2. At this time, the first interlayer insulating film 109a and the gate insulating film 105 below the first interlayer insulating film 109a are active And first and second semiconductor layer contact holes 111a and 111b that respectively expose the source and drain regions 103b and 103c located on both sides of the region 103a.

Next, upper portions of the first interlayer insulating film 109a including the first and second semiconductor layer contact holes 111a and 111b are separated from each other by a source exposed through the first and second semiconductor layer contact holes 111a and 111b, And source and drain electrodes 113 and 115 which are in contact with the drain regions 103b and 103c, respectively.

And a drain contact hole 117 exposing the drain electrode 115 to the upper portion of the first interlayer insulating film 109a exposed between the source and drain electrodes 113 and 115 and the two electrodes 113 and 115, A planarization layer 119 for planarizing a step between the insulating film 109b and the surface of the array substrate 101 is formed.

At this time, the semiconductor layer 103 including the source and drain electrodes 113 and 115 and the source and drain regions 103b and 103c contacting the electrodes 113 and 115 and the gate electrode 103 formed on the semiconductor layer 103 (107) constitute a driving thin film transistor (DTr).

Though not shown in the drawing, the switching thin film transistor STr in FIG. 2 has the same structure as the driving thin film transistor DTr and is connected to the driving thin film transistor DTr.

Here, the switching thin film transistor (STr in FIG. 2) and the driving thin film transistor DTr are shown as an example of a top gate type in which the semiconductor layer 103 is a polysilicon (p-Si) semiconductor layer , Or a bottom gate type.

The switching thin film transistor (STr in FIG. 2) and the driving thin film transistor DTr may be formed of amorphous silicon (a-si) or an oxide semiconductor layer of pure water and impurity, pentacene or polythiophene may be used as the organic semiconductor layer.

The drain electrode 115 of the driving thin film transistor DTr is connected to the drain electrode 115 through the drain contact hole 117. In a region where the image is substantially displayed on the planarization layer 119, The first electrode 211 is formed of, for example, a material having a relatively high work function value, and functions as a constituent element of the organic light emitting diode E.

The first electrode 211 is formed for each pixel region (P in FIG. 2). A bank layer 121 is located between the first electrodes 211 formed for each pixel region (P in FIG. 2) .

That is, the first electrodes 211 are formed in a structure in which the bank layer 121 is divided into the pixel regions P with the boundary of each pixel region (P in FIG. 2).

Here, the bank layer 121 may be formed of a material selected from the group consisting of polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimides resin, One selected from the group consisting of unsaturated polyesters resin, poly (phenylenethers) resin, poly (phenylenesulfides) resin and benzocyclobutene (BCB) Or it may be made of graphite powder, gravure ink, black spray, black enamel.

An organic light emitting layer 213 is formed on the first electrode 211.

Here, the organic light emitting layer 213 may be a single layer made of a light emitting material. In order to increase the light emitting efficiency, a hole injection layer, a hole transport layer, an emitting material layer, , An electron transport layer (electron transport layer), and an electron injection layer (electron injection layer).

The organic light emitting layer 213 may emit red (R), green (G), and blue (B) colors. In general, each pixel region (P in FIG. 2) ), And blue (B) are patterned and used.

A second electrode 215, which is a cathode, is formed on the organic light emitting layer 213.

The second electrode 215 may be made of an opaque conductive material and may be formed of a metal material having a relatively low work function value such as aluminum (Al), an aluminum alloy (AlNd), silver (Ag), magnesium (Mg) , Gold (Au), and aluminum magnesium alloy (AlMg).

Accordingly, the light emitted from the organic light emitting layer 213 is driven by the lower light emitting method, which is emitted toward the transparent first electrode 211.

When a predetermined voltage is applied to the first electrode 211 and the second electrode 215 in accordance with a selected color signal, the flexible OLED 100 displays the holes injected from the first electrode 211 and the second electrode 215, The excitons are transported to the organic light emitting layer 213 to form excitons. When the excitons transit from the excited state to the ground state, light is emitted and emitted in the form of visible light.

At this time, the emitted light passes through the transparent first electrode 211 and exits to the outside, so that the flexible OLED 100 realizes an arbitrary image.

A protective film 102 in the form of a thin thin film is formed on the driving thin film transistor DTr and the organic light emitting diode E. The flexible OLED 100 of the present invention includes a protective film 102 ). ≪ / RTI >

Therefore, the flexible OLED 100 according to the embodiment of the present invention can encapsulate the protective film 102, so that the OLED 100 can be formed with a smaller thickness than that encapsulated with glass, The overall thickness of the substrate 100 can be reduced.

In addition, the OLED 100 has a flexible characteristic, so that it can realize a flexible OLED capable of maintaining the display performance as it is bent like paper.

Here, the array substrate 101 is made of a flexible glass substrate or plastic material having flexible characteristics so that the display performance can be maintained even if the flexible OLED 100 is bent like a paper.

A terminal (not shown) of the data driving IC 130 is connected to a driving thin film (not shown) from an external power source (not shown) by a bump bonding method in a non-display area NA outside the display area AA of the array substrate 101 And the first and second pad terminals 133 and 135 for applying a signal voltage to the transistor DTr and the organic electroluminescent diode E, respectively.

The second pad terminal 135 is also connected to the FPC 160 for connection to an external power source (not shown).

Here, the first pad terminal 133 and the second pad terminal 135 are formed in a plurality of units. The first pad terminal 133 and the second pad terminal 135 are connected to the source and drain of the driving thin film transistor DTr, And the same material as the electrodes 113 and 115.

A plurality of insulating layers are stacked on the first pad terminal 133 and the second pad terminal 135. The first layer may be formed of the same material as the second interlayer insulating film 109b of the display area AA And the second layer is made of the same material in the same layer as the planarization layer 119 in the display area AA.

The third layer is made of the same material in the same layer as the bank layer 121 of the display area AA.

The first through third contact holes 125a and 125b exposing the first pad terminal 133 and the second pad terminal 135 are formed in the second interlayer insulating film 109b and the planarization layer 119 and the bank layer 121, 125b, and 125c are formed. The first to third contact holes 125a, 125b and 125c are formed by a second interlayer insulating film 109b stacked on the first pad terminal 133 and the second pad terminal 135, a planarization layer 119, The first contact hole 125a exposes the first pad terminal 133 and the second contact hole 125b exposes the one side of the second pad terminal 135 And the third contact hole 125c exposes the other side of the second pad terminal 135. [

The ACF 170 containing the conductive balls 171 is applied onto the bank layer 121 including the first to third contact holes 125a, 125b and 125c to form the first contact holes 125a. The first bump 131a connected to one terminal (not shown) of the data driving integrated circuit 130 is brought into contact with the second contact hole 125b through the second contact hole 125b exposing one side of the second pad terminal 135, The second bump 131b connected to the other terminal (not shown) of the driving integrated circuit 130 comes into contact.

The first bump 131a is an output pad terminal of the data driving integrated circuit 130 and the second bump 131b is an input pad terminal of the data driving integrated circuit 130. The first and second pad terminals 131a, 133 and 135 and the first and second bumps 131a and 131b are electrically connected to each other by the conductive balls 171 pressed therebetween.

The auxiliary pad electrode 137 is formed to contact the other side of the second pad terminal 135 through the third contact hole 125c of the pad portion PA exposing the other side of the second pad terminal 135 The auxiliary pad electrode 137 serves to transmit an external voltage (not shown) to the second pad terminal 135 as well as the second pad terminal 135 by blocking the second pad terminal 135 from the outside, To prevent tampering.

The ACF 170 containing the conductive balls 171 is also applied onto the auxiliary pad electrodes 137 and the auxiliary pad electrodes 137 are electrically connected to each other by the FPC 160 and the conductive balls 171 .

The thicknesses of the second interlayer insulating film 109b, the planarization layer 119 and the bank layer 121 correspond to the lengths of the first and second bumps 131a and 131b of the data driving IC 130, 1 and the second bumps 131a and 131b are short, the bank layer 121 is removed from the upper portion of the first pad terminal 133 and the second pad portion 135, and the first and second bumps 131a and 131b 131b may have a long length, a separate layer (not shown) made of a polymer may be further formed on the bank layer 121.

Therefore, the data driving integrated circuit 130 is brought into contact with the bank layer 121, so that the pressure concentrated on the first and second bumps 131a and 131b in the process of mounting the data driving integrated circuit 130 is data- To be distributed throughout the integrated circuit 130.

As a result, it is possible to prevent the occurrence of compression failure in the process of mounting the data driving integrated circuit 130.

The data driving integrated circuit 130 is mounted on the bank layer 121 to which the ACF 170 is applied in the process of mounting the data driving integrated circuit 130 on the array substrate 101 in the COG type, The first and second bumps 131a and 131b of the data driving integrated circuit 130 are aligned to the first and second contact holes 125a and 125b and the data driving integrated circuit 130 is compressed. The pressure due to the compression is concentrated on the first and second bumps 131a and 131b projecting from the data driving integrated circuit 130. [

The first and second bumps 131a and 131b are formed to have a small area so that the pressure of the first and second bumps 131a and 131b is reduced by the pressure concentrated on the first and second bumps 131a and 131b A crack is generated by the pressing on the first interlayer insulating film 109a or the gate insulating film 105 located underneath.

When cracks are generated in the first interlayer insulating film 109a and the gate insulating film 105 as described above, defects in the switching and driving thin film transistors (STr and DTr in FIG. 2) are caused, thereby lowering the reliability of the flexible OLED 100 .

The second interlayer insulating film 109b and the planarization layer 119 and the bank layer 121 are stacked on the first and second pad terminals 133 and 135 and the second interlayer insulating film 109b, The planarizing layer 119 and the bank layer 121 are made to correspond to the lengths of the first and second bumps 131a and 131b of the data driving integrated circuit 130, The pressure applied to the data driving integrated circuit 130 is distributed to the entire data driving integrated circuit 130 in the process of pressing the data driving integrated circuit 130 in contact with the data driving integrated circuit 130.

Therefore, it is possible to prevent the pressure from concentrating on the first and second bumps 131a and 131b, and to prevent cracks from being generated on the first interlayer insulating film 109a or the gate insulating film 105 .

This makes it possible to prevent the defects of the switching and driving thin film transistors (STr, DTr in FIG. 2) from occurring and improve the reliability of the flexible OLED 100.

Since the first and second bumps 131a and 131b of the data driving IC 130 are formed to have a length of about 10 mu m, the second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 ) Is preferably formed to have a total thickness of about 10 mu m.

At this time, the thickness of any one of the second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 may be 10 占 퐉, and the thickness of the second interlayer insulating film 109b may be about 2 占 퐉 And the planarization layer 119 may be formed to have a thickness of about 3 mu m and the bank layer 121 may have a thickness of about 5 mu m.

When the second interlayer insulating film 109b is formed to have a thickness similar to that of the first and second pad terminals 133 and 135 so that the total thickness of the planarization layer 119 and the bank layer 121 is 10 μm You may.

4 is a cross-sectional view of another embodiment of the present invention cut along the cutting line III-III in FIG.

Here, in order to avoid redundant explanations, the same reference numerals are given to the same parts that have the same functions as those of FIGS. 2 and 3 of the first embodiment described above, and only the characteristic contents described above will be described.

As shown in the figure, a semiconductor layer 103, a gate electrode 107 formed on the semiconductor layer 103, and a source of the semiconductor layer 103 are formed in a display area AA for displaying an image of the array substrate 101, A driving thin film transistor DTr including source and drain electrodes 113 and 115 which respectively contact the drain regions 103b and 103c is formed.

The semiconductor layer 103 is composed of an active region 103a corresponding to the gate electrode 107 and source and drain regions 103b and 103c on both sides of the active region 103a and between the semiconductor layer 103 and the gate electrode 107 A first interlayer insulating film 109a is interposed between the gate electrode 107 and the source and drain electrodes 113 and 115 while the source and drain electrodes 113 and 115 are interposed between the gate electrode 107 and the source and drain electrodes 113 and 115, And the source and drain regions 103b and 103c through the second semiconductor layer contact holes 111a and 111b.

A second interlayer insulating film 109b having a drain contact hole 117 exposing the drain electrode 115 and a planarization layer 119 are formed on the first interlayer insulating film 109a, , The switching thin film transistor STr in FIG. 2 has the same structure as the driving thin film transistor DTr and is connected to the driving thin film transistor DTr.

The drain electrode 115 of the driving thin film transistor DTr is connected to the drain electrode 115 through the drain contact hole 117. In a region where the image is substantially displayed on the planarization layer 119, (211) is formed.

The first electrode 211 is made of, for example, a material having a relatively high work function value.

The first electrode 211 is formed for each pixel region (P in FIG. 2). The bank layer 121 is located between the first electrodes 211 formed for each pixel region (P in FIG. 2) A spacer 127 is located above the layer 121.

Here, the bank layer 121 and the spacer 127 may be made of the same material in the same process.

The spacer 127 serves to prevent the organic light emitting layer 213 from being damaged by physical force after the array substrate 101 is encapsulated through the protective film 102 described later and the bank layer 121 (P in Fig. 2) can be defined separately. The spacers 127 may be located in each pixel region (P in FIG. 2), but may be irregularly arranged at intervals of two pixel regions (P in FIG. 2) or at regular intervals.

An organic light emitting layer 213 is formed on the first electrode 211.

Here, the organic light emitting layer 213 may be a single layer made of a light emitting material. In order to increase the light emitting efficiency, a hole injection layer, a hole transport layer, an emitting material layer, , An electron transport layer (electron transport layer), and an electron injection layer (electron injection layer).

The organic light emitting layer 213 may emit red (R), green (G), and blue (B) colors. In general, (B) An organic material emitting a color is used in a pattern.

A second electrode 215, which is a cathode, is formed on the organic light emitting layer 213.

In this case, the second electrode 215 may be made of an opaque conductive material. For example, the second electrode 215 may be made of a metal material having a relatively low work function value such as aluminum (Al), an aluminum alloy (AlNd), silver (Ag) , Gold (Au), and aluminum magnesium alloy (AlMg).

Accordingly, the light emitted from the organic light emitting layer 213 is driven by the lower light emitting method, which is emitted toward the transparent first electrode 211.

A protective film 102 in the form of a thin thin film is formed on the driving thin film transistor DTr and the organic light emitting diode E. The flexible OLED 100 of the present invention includes a protective film 102 ). ≪ / RTI >

Here, the array substrate 101 is made of a flexible glass substrate or plastic material having flexible characteristics so that the display performance can be maintained even if the flexible OLED 100 is bent like a paper.

A terminal (not shown) of the data driving IC 130 is connected to a driving thin film (not shown) from an external power source (not shown) by a bump bonding method in a non-display area NA outside the display area AA of the array substrate 101 And the first and second pad terminals 133 and 135 for applying a signal voltage to the transistor DTr and the organic electroluminescent diode E, respectively.

The second pad terminal 135 is also connected to the FPC 160 for connection to an external power source (not shown).

A plurality of insulating layers are stacked on the first pad terminal 133 and the second pad terminal 135. The first layer may be formed of the same material as the second interlayer insulating film 109b of the display area AA And the second layer is made of the same material in the same layer as the planarization layer 119 in the display area AA.

The third layer is made of the same material in the same layer as the bank layer 121 of the display area AA.

The first through third contact holes 125a and 125b exposing the first pad terminal 133 and the second pad terminal 135 are formed in the second interlayer insulating film 109b and the planarization layer 119 and the bank layer 121, 125b, and 125c are formed.

The first to third contact holes 125a, 125b and 125c are formed by a second interlayer insulating film 109b stacked on the first pad terminal 133 and the second pad terminal 135, a planarization layer 119, The first contact hole 125a exposes the first pad terminal 133 and the second contact hole 125b exposes the one side of the second pad terminal 135 And the third contact hole 125c exposes the other side of the second pad terminal 135. [

The ACF 170 containing the conductive balls 171 is applied onto the bank layer 121 including the first to third contact holes 125a, 125b and 125c to form the first contact holes 125a. The first bump 131a connected to one terminal (not shown) of the data driving integrated circuit 130 is brought into contact with the second contact hole 125b through the second contact hole 125b exposing one side of the second pad terminal 135, The second bump 131b connected to the other terminal (not shown) of the driving integrated circuit 130 comes into contact.

At this time, the first and second pad terminals 133 and 135 and the first and second bumps 131a and 131b are electrically connected to each other by the conductive balls 171 pressed therebetween.

The auxiliary pad electrode 137 is formed to contact the other side of the second pad terminal 135 through the third contact hole 125c of the pad portion PA exposing the other side of the second pad terminal 133 The ACF 170 containing the conductive balls 171 is applied onto the auxiliary pad electrodes 137 and the auxiliary pad electrodes 137 are electrically connected to each other by the FPC 160 and the conductive balls 171 do.

A fourth layer of the same material as the spacer 127 in the display region is formed on the bank layer 121. The second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 ) And the thickness of the spacer 127 correspond to the lengths of the first and second bumps 131a and 131b of the data driving integrated circuit 130.

Therefore, the data driving integrated circuit 130 is brought into contact with the spacers 127, so that the pressure concentrated on the first and second bumps 131a and 131b in the process of mounting the data driving integrated circuit 130 can be data- So as to be dispersed throughout the circuit 130.

As a result, it is possible to prevent the occurrence of compression failure in the process of mounting the data driving integrated circuit 130.

That is, in the present invention, after the second interlayer insulating film 109b, the planarization layer 119, and the bank layer 121 are stacked on the first and second pad terminals 133 and 135, The spacers 127 are formed and the thickness of the second interlayer insulating film 109b and the planarization layer 119 and the bank layers 121 and the spacers 127 is set to the thicknesses of the first and second bumps The data driving integrated circuit 130 is brought into contact with the spacer 127 so that the pressure applied to the data driving integrated circuit 130 in the process of pressing the data driving integrated circuit 130 To be dispersed throughout the data driving integrated circuit 130.

Therefore, it is possible to prevent the pressure from concentrating on the first and second bumps 131a and 131b, and to prevent cracks due to the pressing of the first interlayer insulating film 109a or the gate insulating film 105 .

This makes it possible to prevent the defects of the switching and driving thin film transistors (STr, DTr in FIG. 2) from occurring and improve the reliability of the flexible OLED 100.

Since the first and second bumps 131a and 131b of the data driving integrated circuit 130 are formed to have a length of about 10 mu m, the second interlayer insulating film 109b, the planarization layer 119, the bank layer 121 ) And the total thickness of the spacer 127 is also about 10 mu m.

At this time, the second interlayer insulating film 109b may be formed to have a thickness of about 2 mu m, the planarization layer 119 may be formed to have a thickness of about 3 mu m, the bank layer 121 may have a thickness of about 2 mu m, The thickness of the second electrode 127 may be formed to have a thickness of about 3 mu m.

When the second interlayer insulating film 109b is formed to have a thickness similar to that of the first and second pad terminals 133 and 135, the total thickness of the planarization layer 119, the bank layer 121, and the spacer 127 is (Not shown) made of a polymer may be further formed on the spacer 127 when the first and second bumps 131a and 131b are longer than the first and second bumps 131a and 131b It is possible.

As described above, the flexible OLED 100 of the present invention includes a plurality of layers (corresponding to the lengths of the bumps 131a and 131b) on the pad terminals 133 and 135 so as to directly support the data driving integrated circuit 130 The pressure applied to the data driving integrated circuit 130 can be dispersed throughout the data driving integrated circuit 130 in the process of pressing the data driving integrated circuit 130 by forming the electrodes 109a, 109b, 119, 121, .

This makes it possible to prevent the pressure from concentrating on the bumps 131a and 131b and to prevent cracks due to the pressing of the first interlayer insulating film 109a or the gate insulating film 105, It is possible to prevent the defects of the thin film transistors (STr and DTr in FIG. 2) from occurring, and the reliability of the flexible OLED 100 can be improved.

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the present invention.

100: OLED, 101: substrate, 102: protective film
103: semiconductor layer 103a (active region, 103b, 103c: source and drain regions)
105: gate insulating film, 107: gate electrode, 109a, 109b: first and second interlayer insulating films
111a, 111b: first and second semiconductor layer contact holes,
113 and 115: source and drain electrodes,
117: drain contact hole, 119: planarization layer, 121: bank layer
125a, 125b, and 125c: first to third contact holes
130: data driving integrated circuit, 131a, 131b: first and second bumps
133, 135: first and second terminals
137: auxiliary pad electrode
160: FPC, 170: ACF (171: conductive ball)
211: first electrode, 213: organic light emitting layer, 215: second electrode
DTr: driving thin film transistor, E: organic light emitting diode
AA: display area, NA: non-display area

Claims (9)

A COG type flexible organic light emitting diode comprising a switching and driving thin film transistor and an organic light emitting diode on a first substrate including a display portion and a non-display portion,
A semiconductor device comprising: a semiconductor layer; a gate electrode; a source and a drain electrode; a gate insulating film positioned between the semiconductor layer and the gate electrode; and a first interlayer insulating film located between the gate electrode and the source and drain electrodes And a driving thin film transistor;
A second interlayer insulating film covering the source and drain electrodes;
A pad terminal located in the non-display portion and electrically connected to the switching and driving thin film transistor;
An insulating layer formed on the pad terminal and including a contact hole exposing the pad terminal;
And a bump that is in electrical contact with the pad terminal through the contact hole.
Wherein a thickness of the insulating layer corresponds to a length of the bump, the driving integrated circuit is held in close contact with the insulating layer,
Wherein the insulating layer comprises the second interlayer insulating film, a planarization layer over the second interlayer insulating film, and a bank layer above the planarization layer.
delete The method according to claim 1,
Wherein the drive integrated circuit includes first and second bumps,
Wherein the first bump is an output pad terminal and the second bump is an input pad terminal.
The method of claim 3,
The first and second bumps are respectively connected to the first and second pad terminals,
The second pad terminal is connected to the FPC via the auxiliary pad electrode,
Wherein the FPC is connected to an external power source.
The method according to claim 1,
Wherein the insulating layer comprises a spacer over the bank layer.
6. The method of claim 5,
Wherein the insulating layer further comprises a fifth layer made of a separate polymer material on the spacer.
The method according to claim 1,
Wherein the organic electroluminescent diode comprises a first electrode, an organic light emitting layer, and a second electrode, and the first electrode is divided into pixel regions through the bank layer.
The method according to claim 1,
Wherein the pad terminal and the bump are in electrical contact with each other through an anisotropic conductive film (ACF).
The method according to claim 1,
Wherein the semiconductor layer comprises one selected from the group consisting of polysilicon (p-Si), amorphous silicon (a-Si), oxide, and organic.

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