KR20130047465A - Data communication method for communication module of digital protective relay - Google Patents

Abstract

PURPOSE: A communication module and data communication method for a digital protective relay are provided to sufficiently perform an inherent function of a digital protective relay. CONSTITUTION: A communication module for a digital protective relay includes a HDLC protocol(100), a shared memory(200), a multiplexer(300), a communication unit(400) and an interrupt(500). The HDLC protocol transceives data by performing half duplex communication with an upper monitoring system. The shared memory transceives data with the HDLC protocol and provides a bidirectional interface. The multiplexer transceives data with the shared memory and transmits the signal by selecting one input signal by a selected control signal in a plurality of circuit input signals. The communication unit transceives data with the multiplexer and transceives data with a desktop and a controller by performing communication. The interrupt transmits a single signal with respect to one communication packet received in the HDLC to the control unit.

Description

Communication module for digital protective relay and data communication method {Data communication method for Communication module of digital Protective Relay}

The present invention relates to a communication module for a digital protection relay and a data communication method thereof, and more particularly, to provide a data communication method that can minimize interrupt cycle occurring in a microprocessor using HDLC communication. The present invention relates to a communication module for a digital protective relay and a data communication method thereof to enable the function of the present invention to be faithfully performed.

In general, power systems have a very complex structure that includes elements such as numerous power plants, substations and transmission and distribution lines. These power systems must have a constant voltage and frequency and operate reliably to supply the power to meet demand.

However, ever-changing power demands and failures in the natural state according to the consumer's intention affect the voltage, frequency, etc., making it difficult to supply reliable power.

In particular, in the event of a breakdown in the system, relays were used because very large currents could be generated at the point of failure, resulting in human damage, numerous property damages, as well as large power outages.

Here, the relay is also referred to as a digital protection relay, which communicates with the Supervisory Control and Data Acquisition (SCADA) system to detect abnormal grid conditions and react as quickly as possible to return the grid to a normal state. . In order to perform this function, system design for protection relay is essential.

These digital protection relays are mostly configured for real time monitoring of the measurement and operation status by communicating with the SCADA system for more reliable operation of the system.

In this case, industrial fieldbuses are frequently used to communicate with digital protection relays. In case of digital protection relays developed by our company, HDLC (High-level Data Link Control) communication is adopted to realize high-speed and reliable communication. Implemented.

In order to support the HDLC communication protocol, since there is no product with a built-in microprocessor, a separate external HDLC communication control chipset (eg, Z85230 communication module) has been connected and applied.

However, the external HDLC communication control chipset (eg, Z85230 communication module) has been developed long time ago, and has a high defect rate, and frequently causes a failure in use, resulting in a failure of the digital protection relay.

Accordingly, in the case of entry-level digital protection relay, the number of assembly parts must be minimized to lower the development cost of the equipment.

For example, a microprocessor is designed to handle relaying, instrumentation, user interface, and communication with host systems. At this time, when performing HDLC communication with the higher-level monitoring system, a digital protection relay, the microprocessor generates an interrupt signal in units of character data size, and thus frequently encounters an interrupt that must be used in another service.

If you use industrial communication other than HDLC communication, this situation cannot be avoided. In fact, there is a problem that the processing cost caused by the problem situation caused by excessive high-level communication interrupt in the field.

In other words, the main role of the digital protective relay should be to diagnose the abnormal state of the power system and to perform the protection operation in real time, but since the monitoring function must be provided together, to satisfy all the functions, the internal performance should be appropriately lowered and stabilized to be stabilized. Had difficulty.

Accordingly, the present invention is to solve the above-mentioned conventional problems, by providing a communication module and a data communication method for minimizing the interrupt cycle occurring in the microprocessor using HDLC communication, the conventional external HDLC communication control It is an object of the present invention to provide a data communication method of a communication module for a digital protection relay that can replace a chipset (eg, Z85230 communication module) and faithfully perform a function of a digital protection relay.

The communication module for the digital protection relay of the present invention for achieving the above object is a communication module that replaces the application of the Z85230 communication module, which is an external HDLC communication control chipset, because a microprocessor is not built in the digital protection relay. HDLC protocol (High Level Data Link Control Precedure) for transmitting and receiving data by performing a method of communication; A shared memory for transmitting and receiving data with the HDLC protocol and providing a bidirectional interface; A multiplexer (MUX, Multiplexer) which transmits and receives data to and from the shared memory and selects one input signal from a plurality of circuit input signals and loads the input signal to an output circuit; A communication unit for transmitting and receiving data with the multiplexer and communicating with a desktop and a controller; And an interrupt for transmitting one signal to the controller for one communication packet received by the HDLC. .

In addition, the communication unit transmits and receives data to and from the multiplexer, a universal serial communication unit (UART) for transmitting and receiving data by serial communication with the serial device of the desktop on which the data is stored, and transmit and receive data with the multiplexer, and a controller for control It may include a parallel communication unit for transmitting and receiving data at high speed by the parallel communication.

In addition, the parallel communication unit may include an address bus and a data bus.

On the other hand, the data communication method of the communication module, the first step of detecting that the Rx interrupt is generated in the communication module; A second step of checking a length of an area of a reception data packet by reading a reception data length register when a reception (Rx) interrupt is detected; A third step of reading a destination address, a source address, a command / response, and a flag after the second step; A fourth step of reading the data area of the buffer by the value read from the Rx Data length Register; A fifth step of completing a data reception operation after writing a 1 to the Rx Interrupt Flag Bit of the interrupt register to request a Rx Interrupt after the fourth step; It is composed of.

According to the present invention, it is possible to replace an external HDLC communication control chipset (eg, Z85230 communication module) used in the past, and communication module and its data capable of minimizing the interrupt cycle occurring in the microprocessor using HDLC communication. By providing a communication method, it is possible to expect the effect of faithfully performing the original functions of the digital protective relay.

1 is a block diagram showing a communication module for a digital protective relay for the implementation of the present invention.
2 is a view for showing an internal memory and a register for a communication module for a digital protective relay according to the present invention.
3 is a view showing a data packet used in a communication module for a digital protective relay.
Figure 4 is a flow chart showing a data communication method of the communication module for a digital protective relay of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In describing the present invention, the defined terms are defined in consideration of the function of the present invention, and should not be understood in a limiting sense of the technical elements of the present invention.

As shown in the figure, the communication method of the communication module for a digital protective relay according to the present invention relates to a communication method of the HDLC communication module using a field-programmable gate array (FPGA), the interrupt signal period generated in the microprocessor This is to ensure that the original functions of the digital protective relay can be faithfully minimized by minimizing the

To this end, the present invention is a communication module for replacing the Z85230 communication module, which is an external HDLC communication control chipset, because a microprocessor is not built in the digital protection relay, and the digital protection relay communication module is a half-duplex system with a higher monitoring system. HDLC protocol (High Level Data Link Control Precedure, 100) for transmitting and receiving data by performing communication with the shared memory (Shared Memory, 200) for transmitting and receiving data with the HDLC protocol 100 and providing a bidirectional interface. And a multiplexer (MUX, Multiplexer, 300) which transmits and receives data to and from the shared memory 200 and selects one of the input signals according to a control signal selected from a plurality of circuit input signals and loads the same into an output circuit. Send and receive data and communicate with the desktop 10 and the controller 20 to send and receive data The bride includes an interrupt (500) for transmitting a single signal for one communication packet is received in 400 and the HDLC controller to said.

That is, the communication module is equipped with the function of the HDLC protocol 100 to perform HDLC communication, and a shared memory for providing a bidirectional interface for transmitting and receiving data is configured.

Here, the communication unit 400 transmits and receives data to and from the multiplexer 300, and a serial communication unit (UART, 410) for transmitting and receiving data by serial communication with a serial device (not shown) of the desktop 10 in which the data is stored. And a parallel communication unit 420 for transmitting and receiving data with the multiplexer 300 and transmitting and receiving data at high speed by parallel communication with the controller 20 for control. The parallel communication unit 420 may include an address bus and a data bus.

That is, a parallel communication unit 420 composed of an address bus and a data bus for transmitting and receiving data to and from a desktop 10 and a controller 20 having a protective relay or a universal serial port, and a serial for a general purpose but relatively low speed interface. The communication unit 410 may be selectively used.

In this case, the parallel communication unit 420 and the serial communication unit 410 may design a bidirectional internal memory to buffer the data therein, thereby storing and transmitting data up to 1 Kbyte at a time.

In addition, since the HDLC protocol 100 performs half duplex communication, the structure of the memory uses twice as much memory capacity as the bidirectionality by using the same physical memory as the buffer of the transmission and reception. To make it possible.

That is, the memory can use the transmission buffer 1Kbyte during transmission, and conversely, the memory can use the reception buffer 1Kbyte during reception.

In addition, when performing a reception operation in the communication module, a signal for informing the controller 20 in real time about one communication packet received within 1 Kbyte is generated in the interrupt 500.

That is, this function generates one interrupt signal for one communication packet received by the device with its ID. This can significantly reduce the computational load of the CPU when receiving the interrupt signal from the controller 20 and processing it with DMA (Direct Memory Access).

In addition, the response time during the communication of the HDLC protocol 100 may be adjusted so that a collision of a signal with a communication part of the upper system may not occur.

In order to use the parallel communication unit 420, the interface timing is presented for read / write, and the effective time for using the chip can operate at least 120 [nsec].

In addition to the 1 Kbyte of memory for sending the internal data of the relay as communication data, as shown in FIG. 2, the communication speed of the HDLC protocol 100, the communication ID of the protection relay, the directional setting of the interrupt signal, and the number of received data when transmitting and receiving And a setting function for the number of data to be transmitted. And it can be configured to define and use registers to provide the result status for the CRC function that checks for errors in the received data upon receipt.

In order to use the serial communication unit 410, by designating a separate pin inside the present invention to interface at a speed of 115,200 [bps] when the input digital signal is forced to a high level, the parallel communication method As in the interface of HDLC, it can be used as the setting mode to set the communication speed and protection relay ID of HDLC.

Referring to the communication method of the communication module for digital protection relay configured as described above are as follows.

3 illustrates a data packet type used in a communication module.

As shown in FIG. 3, the communication module may transmit and receive a data packet including a flag, an address, data, a cyclic redundancy check (CRC), and a flag through RS-485 communication. It consists of Destination Address (DA), Source Address (SA), Command / Response (C / R), and Flag.

The communication module supports registers to control HDLC communication and has enough data buffers for data transmission and reception.

In addition, the communication baud rate made by the communication module uses 62.5 kbps as the default value, and various baud rates so that the user can control up to 256 kbps using the baud rate control register ).

Baud rate Control Register  H (0 xC000 ) R / W 0x02 (Default) Baud rate Control Register  L (0 xC001 ) R / W 0x71 (Default)

If 62.5kbps is the default as shown in Table 1 above, less than one hundred units are ignored. As above, 625 = 0x0271, so 0x02 is set for the upper byte and 0x71 is set for the lower byte.

The configured communication module may perform various communication settings using a control register. The control register configured in the communication module enables both read / write (R / W), so that it is possible to check how the communication module is set by reading the corresponding register.

Communication setting made by control register Control Register  (0 xC002 ) Bit role Explanation 7 Module Enable
(R / W) -It enables to use communication module.
- Disable in Enable The communication module automatically Reset do.
l 0: Disable  ( Default )
l One: Enable 6 Module Reset
(R / W) -Communication module Reset do. Reset  After that, all setting values of communication module Default Return to value Rx Of Tx Buffer Clear all of them.
- Rx Of Tx Length Register  All values to 0 Reset do.
- Rx Of Tx Interrupt Flag  all Clear  do.
-This Bit Is set to 1, Module this Reset And keep 1 while Reset It will automatically return to zero when it completes.
l 0: Reset  complete ( Default )
l One: Reset  Execution. 5 Rx Buffer Clear
(R / W) - DA , SA , C / R, Flag , Data  Area Rx  All of the realms Buffer To Clear do.
- Rx Length Register  Value to 0 Reset  do.
- Rx Buffer Clear When you run Buffer end Clear At the same time Rx Interrupt Flag Degree Clear  do.
- Rx Buffer Clear It keeps 1 while running and automatically returns to 0 when the Clear process is completed.
l 0: Rx Buffer Clear  complete ( Default )
l One: Rx Buffer Clear  Execution 4 Tx Buffer Clear
(R / W) - DA , SA , C / R, Flag , Data  Area Rx  All of the realms Buffer To Clear do.
- Tx Length Register  Value to 0 Reset  do.
- Tx Buffer Clear When you run Buffer end Clear At the same time Tx Interrupt Flag Degree Clear  do.
- Tx Buffer Clear It keeps 1 while running and automatically returns to 0 when the Clear process is completed.
l 0: Tx Buffer Clear  complete ( Default )
l One: Tx Buffer Clear  Execution 3 Tx Interrupt Enable
(R / W) - Tx Buffer Number Register As many as Data Send, Tx Buffer To Clear After one, again Tx  When you can service, Interrupt Pulse . if Tx  Interrupt Enable If not Tx Buffer In Data After sending all Tx Interrupt Flag By 1 Set Interrupt Pulse Does not generate
l 0: Disable  ( Default )
l One: Enable 2 Rx Interrupt Enable
(R / W) -Communication packets CRC If you receive everything until Rx Interrupt Pulse . if Rx Interrupt To Enable Otherwise, Rx Interrupt Flag By 1 Set And, Interrupt Pulse Does not make.
l 0: Disable  ( Default )
l One: Enable One Tx Enable
(R / W) l 0: Disable  ( Default )
l One: Enable 0 Rx Enable
(R / W)

On the other hand, Table 3 is a method of processing a flag when generating a Rx / Tx Interrupt in the communication module.

Interrupt Flag Register  (0 xC003 ) Bit role Explanation 7 Reserved
(R) -Do not use. 6 5 4 3 2 One Tx Interrupt Flag
(R / W) -When all Tx Data is transmitted and becomes Tx Ready state, it becomes 1.
-It is 0 when data is being transferred, and it is converted back to 1 when the transmission is completed. 0 Rx Interrupt Flag
(R / W) -After receiving all data packets and completing CRC check, if there is no packet error, this bit becomes 1. If Rx Interrupt is enabled, this flag generates Rx Interrupt. If you input 1 again, this bit is changed to 0 again by interrupt ACK.

Referring to the communication method of the communication module of the present invention using the data packet described as follows.

◆ ◆ data reception

Referring to the data receiving method of the present invention with reference to the flowchart of Fig. 4, the first step of detecting that the Rx interrupt is generated in the communication module, and reading the Rx Data length Register when the Rx interrupt is detected to determine the length of the reception data area. A second step of checking, a third step of reading a destination address, a source address, a command / response, a flag after the second step, a fourth step of reading a data area of the buffer by the value read from the Rx data length register, and A fifth step of requesting an Rx Interrupt by writing 1 to the Rx Interrupt Flag Bit of the interrupt register after the fourth step and ending the data receiving operation; It is composed of.

In the third step, only when the destination address (DA) is the same as the value stored in the Self Address Register, the communication data is received until the CRC and the flag is displayed thereafter, and the communication address is received because the Self Address is correct. When receiving, it checks 16bits CRC in communication module and uploads data to Rx Buffer only when CRC is all right, and sets Rx Interrupt Flag to 1.

In addition, it is characterized in that the buffer (DA, SA, C / R, Flag) read after the fourth step.

The communication method of the present invention is described as follows.

First, if an Rx interrupt occurs in the communication module due to the reception data, the communication module checks the length of the reception data area by reading the Rx Data length register when the Rx interrupt is detected.

The size of the received communication data is expressed in bytes and stored in the Rx Data Length Register. For example, if the received communication data is 12 bytes, the message size includes DA, SA, C / R, Flag, and Data.

[Table 4] below shows the contents stored in the Rx Length Register when 500 data are received.

Rx Length Register Read only Rx Data Length  H (0 xC005 ) 0x01 Rx Data Length  L (0 xC006 ) 0 xF4

When the length of the reception data area is confirmed in the second step, the destination address, source address, command / response, and flag are read.

At this time, only when the Destination Address (DA) is the same as the value stored in the Self Address Register as shown in Table 5, communication data is received until the CRC and Flag are displayed.

Self Address Register  (0 xC004 ) R / W 0xXX

When communication data is received because the self address is correct, the communication module checks 16bits CRC and uploads data to Rx buffer only when all CRCs are correct, and sets Rx Interrupt Flag to 1. If Rx Interrupt Enable Bit is set in Control Register, Interrupt occurs.

In this way, when receiving the communication data because the Self Address is correct, the data area of the buffer is read as much as the value read from the Rx Data length Register.

Buffer automatically clears when reading data. Even if the buffer is not read, setting Rx Buffer Clear Bit of Control Register to 1 clears the entire Data Buffer including DA, SA, C / R, and Flag area, and Rx of Control Register. The Buffer Clear Bit goes back to zero. Keep Clear Bit 1 while clearing.

After receiving data, it writes 1 to Rx Interrupt Flag Bit of interrupt register, requests Rx Interrupt and terminates data receiving operation.

On the other hand, when uploading the received communication data, it is divided into Destination Address (DA), Source Address (SA), Command / Response (C / R), Flag, and Data area. For compatibility with existing programs, memory addresses are set in the order of DA, SA, C / R, Flag, Data in order to increase the address so that they can be accessed in order.

Table 6 shows the address change of Rx Buffer during upload.

Rx Buffer  (0x0000) Read Only Address 8 bit Buffer 0x0000 DA 0x0001 SA 0x0002 C / R 0x0003 Flag 0x0004 Data [0] 0x0005 Data [1] ... . ... . 0x0247 (583) Data [580]

In case of reading Rx Buffer, it does not need to set Address again. For example, in case of reading 0x0000, the next time the Read command is continued in the DSP, the address is incremented by 1 so that the next data can be transmitted such as 0x0001 and 0x0002. After that, when the address setting command comes out again, the pointer moves to the address, and when the Read command is issued, data is increased by 1 from the address.

If the data is received again when the buffer is not cleared or only partially cleared, the received data is ignored until all the buffers are cleared.

If the buffer is not cleared within 100ms after the interrupt is generated, the buffer is automatically cleared and the next communication data is waited for.

Although the technical concept of the data communication method of the digital protective relay communication module of the present invention has been described above with the accompanying drawings, this is by way of example and not by way of limitation.

Accordingly, it is a matter of course that various modifications and variations of the present invention are possible without departing from the scope of the present invention. And are included in the technical scope of the present invention.

10: desktop 20: controller
100: HDLC protocol 200: shared memory
300: multiplexer 400: communication unit
410: serial communication unit 420: parallel communication unit
500: interrupt

Claims (7)

A communication module that replaces the Z85230 communication module, which is an external HDLC communication control chipset applied to a digital protective relay, wherein the communication module comprises: a communication module;
An HDLC protocol for transmitting and receiving data by performing half duplex communication with an upper monitoring system;
A shared memory that transmits and receives data with the HDLC protocol and provides a bidirectional interface;
A multiplexer which transmits and receives data to and from the shared memory and selects one input signal from a plurality of circuit input signals and loads the input signal to an output circuit;
A communication unit for transmitting and receiving data with the multiplexer and communicating with a desktop and a controller; And
An interrupt for transmitting one signal to the controller for one communication packet received by the HDLC; Communication module for digital protection relay, characterized in that comprising a. The communication unit of claim 1, wherein the communication unit transmits and receives data to and from the multiplexer, and a universal serial communication unit (UART) which transmits and receives data by serial communication with a serial device of a desktop where data is stored. Digital communication relay communication module comprising a parallel communication unit for transmitting and receiving data at a high speed by the parallel communication with the controller for. 3. The digital protective relay communication module according to claim 2, wherein the parallel communication unit comprises an address bus and a data bus. A first step of detecting that an Rx interrupt is generated in the communication module;
A second step of checking a length of an area of a reception data packet by reading a reception data length register when a reception (Rx) interrupt is detected;
A third step of reading a destination address, a source address, a command / response, and a flag after the second step;
A fourth step of reading the data area of the buffer by the value read from the Rx Data length Register; And
A fifth step of completing a data reception operation after writing a 1 to the Rx Interrupt Flag Bit of the interrupt register to request a Rx Interrupt after the fourth step; Data communication method of a communication module for a digital protective relay, characterized in that to proceed. The method of claim 4, wherein
In the third step, only when the destination address (DA) is the same as the value stored in the Self Address Register, the communication data is received until the CRC and the flag appear later, and the communication data is received because the Self Address is correct. If the 16bits CRC is checked in the communication module, the data is uploaded to the Rx Buffer only when all the CRCs are met, and the Rx Interrupt Flag is set to 1. The data communication method of the communication module for the digital protective relay. 5. The data communication method of claim 4, wherein the read buffers (DA, SA, C / R, Flag) are cleared after the fourth step. The method of claim 4, wherein the data packet used in the communication module
Flag, Address, Data, CRC, Flag and the address is a communication module for a digital protection relay, characterized in that consisting of Destination Address (DA), Source Address (SA), Command / Response (C / R), Flag. Data communication method.

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