KR101685613B1 - Data communication method for Communication module of digital Protective Relay - Google Patents

Abstract

The present invention relates to a communication module for a digital protection relay and a data communication method thereof, and more particularly, to a communication module for a digital protection relay, A second step of reading the Rx data length register when the Rx interrupt is detected to check the length of the area of the received data packet; A third step of reading Destination Address, Source Address, Command / Response and Flag after the second step; A fourth step of reading the data area of the buffer by a value read from the Rx data length register; A fifth step of, after the fourth step, writing 1 to the Rx Interrupt Flag Bit of the interrupt register to request Rx interrupt, and terminating the data receiving operation; .

Description

Technical Field [0001] The present invention relates to a communication module and a data communication method for a digital protection relay,

The present invention relates to a communication module for a digital protection relay and a data communication method thereof, and more particularly, to a data communication method capable of minimizing an interruption period occurring in a microprocessor using HDLC communication, And more particularly, to a communication module for a digital protection relay and a data communication method thereof.

Generally, the power system has a very complicated structure including elements such as power plants, substations, and transmission and distribution lines. Such a power system must have a constant voltage and frequency, and must operate reliably to supply power to meet demand.

However, the power demand and the failure in the natural state, which always fluctuate according to the consumer's will, affect the voltage, frequency and the like, making it difficult to supply reliable electric power.

In particular, when a fault occurs in a system, a very large current is generated at a fault point, and a relay is used because it can cause a large scale power failure as well as damage to human life and damage to property.

Here, the relay is also referred to as a digital protection relay, which detects abnormal system conditions by communicating with the SCADA (Supervisory Control and Data Acquisition) system and reacts as quickly as possible to return the system to a normal state . In order to perform such functions, system design for protection relay is essential.

These digital protection relays are mostly configured for real-time monitoring of the measurement and operation status by communicating with the SCADA system for more reliable operation of the system.

In this case, industrial field buses are often used to communicate with digital protection relays. In the case of digital protection relays developed by our company, high-level data link control (HDLC) communication is adopted to realize high-speed and reliable communication Respectively.

In order to support the HDLC communication protocol, a separate external HDLC communication control chipset (for example, Z85230 communication module) has been connected and applied since there is no product having a built-in microprocessor.

However, the external HDLC communication control chipset (for example, Z85230 communication module) has been developed a long time ago and has a high defect rate, and a failure often occurs during use, causing a failure of the digital protection relay.

Therefore, in the case of low-cost digital protection relays, the number of assembly parts must be minimized in order to lower the development cost of the equipment.

For example, a microprocessor is designed to handle all functions of relaying, measurement, user interface, and communication with higher-level systems. At this time, when HDLC communication is performed with the digital protection relay, which is an upper monitoring system, an interrupt signal is generated in units of character data size in the microprocessor, and frequent collisions with interrupts to be used in other services have occurred.

If you use an industrial communication other than HDLC communication, you will not be able to avoid this situation. There is a problem that a processing cost arises due to a problem situation due to an excessive upper communication interrupt in the field actually.

In other words, the main role of the digital protection relay is to diagnose the abnormal condition of the power system and to perform the protection operation in real time. However, in order to satisfy all the functions, the monitoring function must be provided. I had difficulties.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and it is an object of the present invention to provide a communication module and a data communication method capable of minimizing an interrupt cycle occurring in a microprocessor using HDLC communication, It is an object of the present invention to provide a data communication method of a communication module for a digital protection relay capable of replacing a chipset (for example, Z85230 communication module) while faithfully performing the function of the digital protection relay.

The communication module for digital protection relay according to the present invention for replacing the application of Z85230 communication module which is an external HDLC communication control chipset because a microprocessor is not built in a digital protection relay, (High Level Data Link Control Precedure) for transmitting / A shared memory for transmitting and receiving data with the HDLC protocol means and providing a bidirectional interface; A multiplexer (MUX) for transmitting and receiving data to and from the shared memory, selecting one of the plurality of input signals according to a control signal selected from the plurality of circuit input signals, and outputting the selected input signal to an output circuit; A communication unit for transmitting and receiving data with the multiplexer and communicating with a desktop and a controller to transmit and receive data; And an interrupt for transmitting one signal to one controller for one communication packet received in the HDLC; .

The communication unit includes a general-purpose serial communication unit (UART) that transmits and receives data to and from a multiplexer, and transmits and receives data by serial communication with a serial device of a desktop on which data is stored, a controller for transmitting and receiving data with the multiplexer, And a parallel communication unit that transmits and receives data at a high speed by parallel communication.

The parallel communication unit may include an address bus and a data bus.

On the other hand, the data communication method of the communication module includes: a first step of detecting occurrence of an Rx interrupt in the communication module; A second step of reading the Rx data length register (Rx data length register) to detect the length of the area of the received data packet when a reception (Rx) interrupt is detected; A third step of reading a Destination Address, a Source Address, a Command / Response, and a Flag after the second step; A fourth step of reading a data area of the buffer by a value read from a received data length register (Rx data length register); A fifth step of, after the fourth step, writing 1 to the Rx Interrupt Flag Bit of the interrupt register to request a Rx interrupt, and terminating the data receiving operation; .

According to the present invention, there is provided a communication module capable of replacing a conventional external HDLC communication control chipset (e.g., Z85230 communication module) and minimizing an interrupt cycle occurring in a microprocessor using HDLC communication, It is possible to expect an effect of faithfully performing the function of the digital protection relay by providing a communication method.

1 is a block diagram showing a communication module for a digital protection relay for implementing the present invention;
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a digital protection relay communication module.
3 is a diagram showing a data packet used in a communication module for a digital protection relay.
4 is a flow chart showing a data communication method of a communication module for a digital protection relay according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In describing the present invention, the defined terms are defined in consideration of the function of the present invention, and should not be understood in a limiting sense of the technical elements of the present invention.

As shown in the figure, the communication method of the digital protection relay communication module according to the present invention is related to a communication method of an HDLC communication module using an FPGA (Field-Programmable Gate Array), in which an interrupt signal cycle So that the function of the digital protection relay can be faithfully performed.

A communication module for replacing the Z85230 communication module, which is an external HDLC communication control chipset, because the microprocessor is not incorporated in the digital protection relay. The communication module for the digital protection relay includes an upper monitoring system and a half- An HDLC protocol unit 100 for transmitting and receiving data by performing communication with the HDLC protocol unit 100 and a shared memory 100 for transmitting and receiving data and providing a bidirectional interface with the HDLC protocol unit 100, A multiplexer (MUX) 300 for transmitting and receiving data to and from the shared memory 200, selecting one of the input signals according to a control signal selected from a plurality of circuit input signals, Transmits data to and receives data from the multiplexer, communicates with the desktop 10 and the controller 20, And an interruption 500 for transmitting one signal to the controller 20 for one communication packet received by the HDLC.

That is, the communication module includes a function of the HDLC protocol unit 100 for performing HDLC communication and a shared memory for providing a bidirectional interface for transmitting / receiving data.

The communication unit 400 includes a universal serial communication unit (UART) 410 that transmits and receives data to and from the multiplexer 300 and transmits and receives data by serial communication with a serial device (not shown) of the desktop 10 on which data is stored, And a parallel communication unit 420 transmitting and receiving data with the multiplexer 300 and transmitting and receiving data at a high speed by parallel communication with the controller 20 for control. The parallel communication unit 420 may include an address bus and a data bus.

That is, a parallel communication unit 420 composed of an address bus and a data bus for transmitting / receiving data to / from the desktop 10 and the controller 20 having a protection relay or a general-purpose serial port, and a serial communication unit 420 for a general- The communication unit 410 can be selectively used.

In this case, the parallel communication unit 420 and the serial communication unit 410 may designate a bidirectional internal memory so that data can be buffered therein, thereby storing and transmitting data up to 1 Kbyte at a time.

Since the HDLC protocol unit 100 performs half duplex communication, the structure of the memory also uses the same physical memory for the transmission and reception buffers to double the memory capacity Respectively.

That is, the memory can use 1 Kbyte of the transmission buffer during transmission, while the memory can use 1 Kbyte of reception buffer during reception.

In addition, when a receiving operation is performed in the communication module, a signal for notifying the controller 20 of one communication packet received within 1 Kbyte in real time is generated in the interruption 500.

That is, one interrupt signal is generated for one communication packet received in the ID of the device. This can significantly reduce the computational load of the CPU when the controller 20 receives the interrupt signal and processes it with DMA (Direct Memory Access).

In addition, since the response time of the HDLC protocol means 100 can be adjusted, it is possible to prevent a collision between the communication portion of the upper system and the signal.

In order to use the parallel communication unit 420, the interface timing is provided for reading / writing, and the valid time for using the chip is at least 120 [nsec].

In addition to the 1 Kbyte memory for sending the internal data of the relay as communication data as shown in FIG. 2, the communication speed of the HDLC protocol means 100, the communication ID of the protection relay, the directional setting of the interrupt signal, Information and the number of data to be transmitted. And a register for providing a result status for the CRC function that checks for errors in the received data upon reception.

In order to use the serial communication unit 410, when a separate pin is designated in the present invention to forcibly set the input digital signal to a high level, the interface is interfaced at a speed of 115,200 [bps] The HDLC communication speed and the ID of the protection relay can be set in the setting mode.

A communication method of the digital protection relay communication module configured as described above will be described as follows.

3 illustrates a data packet format used in a communication module.

The communication module can transmit and receive data packets including a flag, an address, data, a cyclic redundancy check (CRC), and a flag via RS-485 communication as shown in FIG. 3, Destination Address (DA), Source Address (SA), Command / Response (C / R), Flag.

The communication module supports registers for controlling HDLC communication and has enough data buffer for data transmission and reception.

In addition, the baud rate of the communication module is 62.5 kbps as a default value, and a baud rate control register (Baud rate control register) is used to control the user up to 256 kbps. ).

Baud rate Control Register  H (0 xC000 ) R / W 0x02 (Default) Baud rate Control Register  L (0 xC001 ) R / W 0x71 (Default)

If 62.5kbps is the default as shown in Table 1 above, it is set by inputting 0x02 in the upper byte and 0x71 in the lower byte because 625 = 0x0271 as above is ignored.

The configured communication module can perform various communication settings using a control register. The control register configured in the communication module enables reading / writing (R / W), so that it can check how the communication module is set by reading the corresponding register.

Communication setting made by control register Control Register  (0 xC002 ) Bit role Explanation 7 Module Enable
(R / W) - It enables to use communication module.
- Disable in Enable When you automate the communication module Reset do.
l 0: Disable  ( Default )
l One: Enable 6 Module Reset
(R / W) - Communication module Reset do. Reset  Then all the settings of the communication module are Default Return to value Rx / Tx Buffer Is cleared.
- Rx / Tx Length Register  Set all values to 0 Reset do.
- Rx / Tx Interrupt Flag  all Clear  do.
- This Bit Is set to 1, Module this Reset While maintaining 1, Reset When it is completed, it returns to 0 automatically.
l 0: Reset  complete ( Default )
l One: Reset  Execution. 5 Rx Buffer Clear
(R / W) - DA , SA , C / R, Flag , Data  Area Rx  All of the area Buffer To Clear do.
- Rx Length Register  Set the value to 0 Reset  do.
- Rx Buffer Clear Quot; Buffer end Clear At the same time Rx Interrupt Flag Degree Clear  do.
- Rx Buffer Clear , It keeps 1, and when it completes the clear process, it returns to 0 automatically.
l 0: Rx Buffer Clear  complete ( Default )
l One: Rx Buffer Clear  Execution 4 Tx Buffer Clear
(R / W) - DA , SA , C / R, Flag , Data  Area Rx  All of the area Buffer To Clear do.
- Tx Length Register  Set the value to 0 Reset  do.
- Tx Buffer Clear Quot; Buffer end Clear At the same time Tx Interrupt Flag Degree Clear  do.
- Tx Buffer Clear , It keeps 1, and when it completes the clear process, it returns to 0 automatically.
l 0: Tx Buffer Clear  complete ( Default )
l One: Tx Buffer Clear  Execution 3 Tx Interrupt Enable
(R / W) - Tx Buffer Number Register As many as Data Lt; / RTI > Tx Buffer To Clear Since then, again Tx  When the service is available, Interrupt Pulse . if Tx  Interrupt Enable If you do not Tx Buffer In Data And then, Tx Interrupt Flag Only 1 Set Interrupt Pulse .
l 0: Disable  ( Default )
l One: Enable 2 Rx Interrupt Enable
(R / W) - Communication packets CRC When you receive all Rx Interrupt Pulse . if Rx Interrupt To Enable If not, Rx Interrupt Flag Only 1 Set And, Interrupt Pulse Do not create.
l 0: Disable  ( Default )
l One: Enable One Tx Enable
(R / W) l 0: Disable  ( Default )
l One: Enable 0 Rx Enable
(R / W)

On the other hand, a method of processing a flag when an Rx / Tx interrupt is generated in the communication module is illustrated in Table 3 below.

Interrupt Flag Register  (0 xC003 ) Bit role Explanation 7 Reserved
(R) - Not used. 6 5 4 3 2 One Tx Interrupt Flag
(R / W) - Transmits all Tx data, and becomes 1 when Tx ready state is established.
- When data is being transmitted, it is 0, and when transmission is completed, it is switched back to 1. 0 Rx Interrupt Flag
(R / W) - After receiving all the data packets and after completing the CRC check, this bit becomes 1 if there is no error in the packet. If Rx Interrupt is enabled, this flag generates Rx Interrupt. If you enter 1 again in this bit, it is changed back to 0 by interrupt ACK.

A communication method of the communication module of the present invention using the data packet described above will be described as follows.

◆ Receive data ◆

The method of receiving data according to the present invention will now be described with reference to the flow chart of FIG. 4. The first step is to detect the occurrence of an Rx interrupt in the communication module. The Rx data length register is read when the Rx interrupt is detected, A third step of reading a Destination Address, a Source Address, a Command / Response, and a Flag after the second step, a fourth step of reading a data area of the buffer by a value read from the Rx Data length Register, A fifth step of, after the fourth step, writing 1 to the Rx Interrupt Flag Bit of the interrupt register to request Rx interrupt, and terminating the data receiving operation; .

In the third step, only when the Destination Address (DA) is the same as the value stored in the Self Address Register, the communication data is received until the CRC and Flag come out, Upon receipt, the communication module checks the 16 bits CRC and uploads the data to the Rx Buffer only when all of the CRC is satisfied, and sets the Rx Interrupt Flag to 1.

Also, the buffer (DA, SA, C / R, Flag) read after the fourth step is cleared.

The communication method of the present invention will be described as follows.

First, when a communication module generates an Rx interrupt due to reception data, the communication module reads the Rx data length register to check the length of the reception data area when an Rx interrupt is detected.

The size of the received communication data is displayed in byte and stored in the Rx Data Length Register. For example, if the received communication data is 12 bytes, it is a message size including DA, SA, C / R, Flag and Data.

[Table 4] below shows the contents stored in the Rx Length Register when there are 500 received data.

Rx Length Register Read only Rx Data Length  H (0 xC005 ) 0x01 Rx Data Length  L (0 xC006 ) 0 xF4

When the length of the received data area is confirmed in the second step, the destination address, source address, command / response, and flag are read.

At this time, only when the Destination Address (DA) is the same as the value stored in the Self Address Register as shown in Table 5, the communication data is received until the CRC and Flag come out.

Self Address Register  (0 xC004 ) R / W 0xXX

When the communication data is received because the Self Address is correct, the communication module checks the 16 bits CRC and uploads the data to the Rx Buffer only when the CRC is fully satisfied, and sets the Rx Interrupt Flag to 1. If the Rx Interrupt Enable Bit is set in the Control Register, an interrupt is generated.

When communication data is received because the Self Address is correct, the data area of the buffer is read by the value read from the Rx data length register.

Buffer is automatically cleared when data is read. If Rx Buffer Clear Bit of Control Register is set to 1, it clears the entire data buffer including DA, SA, C / R and Flag area and Rx Buffer Clear Bit returns to 0 again. Keep Clear Bit at 1 during Clear.

After receiving the data, 1 is written to the Rx Interrupt Flag Bit of the interrupt register to request Rx Interrupt and the data reception operation is terminated.

On the other hand, when uploading the received communication data, it is divided into Destination Address (DA), Source Address (SA), Command / Response (C / R), Flag and Data area. In order to be compatible with existing programs, memory addresses are set in the order of DA, SA, C / R, Flag, and Data so that the addresses can be sequentially accessed by increasing addresses.

Table 6 shows the change in address of the Rx buffer at the time of uploading.

Rx Buffer  (0x0000) Read Only Address 8 bit Buffer 0x0000 DA 0x0001 SA 0x0002 C / R 0x0003 Flag 0x0004 Data [0] 0x0005 Data [1] ... . ... . 0x0247 (583) Data [580]

When reading the Rx Buffer, make sure to increase it by 1 without resetting the address. For example, if you read address 0x0000, then the address is incremented by 1 so that the next data can be transmitted as 0x0001 and 0x0002 even if you continue the Read command only in DSP. When the command to set the address is displayed again, the pointer moves to the address, and when the command is issued, the address is incremented by 1 and the data is transmitted.

If the Buffer is not cleared or only partially cleared, if communication data is received again, the received data is ignored until all buffers are cleared.

If the buffer is not cleared within 100ms after generating the interrupt, it automatically clears the buffer and waits for the next communication data

Although the technical idea of the data communication method of the digital protection relay communication module according to the present invention has been described above with reference to the accompanying drawings, it is to be understood that the present invention is not limited thereto.

Accordingly, it is a matter of course that various modifications and variations of the present invention are possible without departing from the scope of the present invention. And are included in the technical scope of the present invention.

10: Desktop 20: Controller
100: HDLC protocol means 200: shared memory
300: Multiplexer 400:
410: serial communication unit 420: parallel communication unit
500: Interrupt

Claims (7)

A communication module replacing the Z85230 communication module as an external HDLC communication control chipset applied to a digital protection relay, the communication module comprising:
An HDLC protocol means for transmitting and receiving data by performing half duplex communication with an upper monitoring system;
A shared memory for transmitting and receiving data with the HDLC protocol means and providing a bidirectional interface;
A multiplexer for transmitting and receiving data to and from the shared memory, selecting one of the input signals according to a control signal selected from a plurality of circuit input signals, and outputting the selected input signal to an output circuit;
A communication unit for transmitting and receiving data with the multiplexer and communicating with a desktop and a controller to transmit and receive data; And
An interrupt for transmitting one signal to a controller for one communication packet received by the HDLC protocol means; And a communication module for a digital protection relay. [2] The apparatus of claim 1, wherein the communication unit comprises: a general-purpose serial communication unit (UART) that transmits and receives data to and from a multiplexer, and transmits and receives data by serial communication with a serial device of the desktop on which data is stored; And a parallel communication unit for transmitting and receiving data at a high speed by parallel communication with the controller for the digital protection relay. The communication module for a digital protection relay according to claim 2, wherein the parallel communication unit includes an address bus and a data bus. A communication module replacing the Z85230 communication module, which is an external HDLC communication control chipset applied to digital protection relays,
A first step of detecting occurrence of an Rx interrupt in the communication module;
A second step of reading the Rx data length register (Rx data length register) to detect the length of the area of the received data packet when a reception (Rx) interrupt is detected;
A third step of reading a Destination Address, a Source Address, a Command / Response, and a Flag after the second step;
A fourth step of reading a data area of the buffer by a value read from a received data length register (Rx data length register); And
After the fourth step, 1 is written to the Rx Interrupt Flag bit of the interrupt register to request a reception interrupt (Rx Interrupt) so that one signal is transmitted for one communication packet A fifth step of terminating the data receiving operation; And transmitting the data to the digital protection relay module. 5. The method of claim 4,
In the third step, only when the Destination Address (DA) is the same as the value stored in the Self Address Register, communication data is received until the next CRC and Flag, and the communication data is received The communication module checks the 16-bit CRC and uploads the data to the Rx buffer only when the CRC is fully satisfied, and sets the Rx Interrupt Flag to 1. The data communication method of the communication module for the digital protection relay. The data communication method according to claim 4, wherein the buffer (DA, SA, C / R, Flag) read after the fourth step is cleared. 5. The method according to claim 4, wherein the data packet used in the communication module
Wherein the address is composed of a Destination Address (DA), a Source Address (SA), a Command / Response (C / R), and a Flag. / RTI >

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