CN108965118B

CN108965118B - DP-to-FF communication gateway and DP-to-FF method

Info

Publication number: CN108965118B
Application number: CN201811011254.8A
Authority: CN
Inventors: 范福基; 黄玲; 李蒙
Original assignee: Hangzhou Hollysys Automation Co Ltd
Current assignee: Hangzhou Hollysys Automation Co Ltd
Priority date: 2018-08-31
Filing date: 2018-08-31
Publication date: 2021-04-16
Anticipated expiration: 2038-08-31
Also published as: CN108965118A

Abstract

The invention discloses a DP-to-FF communication gateway, which comprises an MCU, an ARM processor and an FPGA chip, wherein the MCU and the ARM processor are both connected with the FPGA chip, the MCU receives an instrument data request instruction sent by a controller of a master station through a DP protocol, and sends the instrument data request instruction to the ARM processor through the FPGA, and the instrument data is uploaded to the controller; the ARM processor sends the instrument data request instruction to the field FF equipment; and receiving the returned instrument data, and sending the instrument data to the MCU through the FPGA chip. By applying the technical scheme provided by the embodiment of the invention, the communication between the main station and the field FF equipment is completed only by the mutual cooperation of the MCU, the ARM processor and the FPGA chip, so that the data transmission efficiency is greatly improved, and the cost is reduced. The invention also discloses a method for converting DP into FF, which has corresponding technical effects.

Description

DP-to-FF communication gateway and DP-to-FF method

Technical Field

The invention relates to the technical field of industrial communication equipment, in particular to a DP-to-FF communication gateway and a DP-to-FF method.

Background

Fieldbus technology is an industrial control network developed in the 80's of the twentieth century. Profibus is a shorthand for process field bus, and DP is a field bus technology used for factory automation plant-room level monitoring and field device layer data communication and control. The Profibus-DP can realize distributed digital control and field communication network from field device layer to workshop level monitoring, and provides a feasible solution for realizing comprehensive automation of factories and intellectualization of field devices. The FF fieldbus (foundation fieldbus) can be viewed as a field-based local area network for connecting various instrumentation, valve positioners, etc. intelligent devices, which themselves can provide control applications to the entire network.

The field bus protocol is generally complex, and the development process of related products is high in cost, long in period, high in difficulty and large in workload. At present, in the market, domestic Control manufacturers generally cannot directly access FF instrument data to a Distributed Control System (DCS) controller module adopting DP bus communication, and need to transmit data to a controller in a master station through a long link such as a Personal Computer (PC), so that the data transmission efficiency is low, the cost is high, and it is difficult to perform mixed logic Control on an FF node and a DCS conventional node in the controller in real time.

In summary, how to effectively solve the problems of low data transmission efficiency, high cost, difficulty in performing mixed logic control on the FF node and the DCS conventional node in real time in the controller, and the like, is a problem that needs to be solved by those skilled in the art at present.

Disclosure of Invention

In order to solve the technical problems, the invention provides the following technical scheme:

the utility model provides a DP changes FF communication gateway, includes MCU, ARM treater and FPGA chip, MCU with the ARM treater all with the FPGA chip links to each other, wherein:

the MCU is used for receiving an instrument data request instruction of the field FF device sent by a controller of a main station through a DP protocol and sending the instrument data request instruction to the FPGA chip; uploading the meter data to the controller;

the FPGA chip is used for sending the instrument data request instruction to an ARM processor through an FF protocol; sending the received instrument data to the MCU;

the ARM processor is used for sending the instrument data request instruction to the field FF equipment through the FF protocol and the FPGA chip; and receiving the instrument data returned by the field FF equipment, and sending the instrument data to the FPGA chip.

In a specific embodiment of the present invention, the FPGA chip is further configured to receive diagnostic data and send the diagnostic data to the MCU; the diagnosis data comprises first diagnosis data for self-diagnosis of each device connected with the FPGA chip in the DP-to-FF communication gateway and second diagnosis data which is sent by the ARM processor and is obtained by diagnosing the field FF equipment;

the MCU is also used for uploading the diagnosis data to the controller.

In a specific embodiment of the invention, the invention further comprises two DP transceiver circuits connected with the MCU,

the MCU is specifically used for receiving the instrument data request instruction of the field FF equipment, which is sent by the controller through two DP transceiving circuits of the DP protocol; and returning the instrument data and the diagnosis data to the controller through two DP transceiving circuits of the DP protocol.

In a specific embodiment of the present invention, the FPGA chip is further configured to collect slave station address information.

In an embodiment of the present invention, the FPGA chip is specifically configured to collect slave station address information set in a decimal jumper cap manner.

A method of DP-to-FF, the method comprising:

the method comprises the following steps that an MCU receives an instrument data request instruction sent by a controller of a main station through a DP protocol, and sends the instrument data request instruction to an FPGA chip;

the FPGA chip sends the instrument data request instruction to an ARM processor through an FF protocol;

the ARM processor sends the instrument data request instruction to the field FF equipment through the FF protocol and the FPGA chip; receiving instrument data returned by the field FF equipment, and sending the instrument data to the FPGA chip;

the FPGA chip sends the received instrument data to the MCU;

and the MCU uploads the instrument data to the controller.

In one embodiment of the present invention, the method further comprises:

the FPGA chip receives diagnosis data and sends the diagnosis data to the MCU; the diagnosis data comprises first diagnosis data for self-diagnosis of each device connected with the FPGA chip in the DP-to-FF communication gateway and second diagnosis data which is sent by the ARM processor and is obtained by diagnosing the field FF equipment;

and the MCU uploads the diagnosis data to the controller.

In a specific embodiment of the present invention, the MCU receives an instrument data request command of the field FF device sent by the controller of the master station through the DP protocol, and the MCU includes:

the MCU receives the instrument data request instruction of the field FF equipment sent by the controller through the two DP transceiving circuits of the DP protocol;

the MCU uploads the instrument data to the controller, and specifically comprises the following steps:

the MCU uploads the instrument data to the controller through the two DP transceiver circuits of the DP protocol;

the MCU uploads the diagnosis data to the controller, and specifically comprises the following steps:

and the MCU uploads the diagnosis data to the controller through the two DP transceiving circuits of the DP protocol.

In one embodiment of the present invention, the method further comprises:

and the FPGA chip acquires slave station address information.

In a specific embodiment of the present invention, the acquiring slave station address information by the FPGA chip includes:

the FPGA chip collects slave station address information set in a decimal jumper wire cap mode.

By applying the DP-to-FF communication gateway provided by the embodiment of the invention, the MCU receives an instrument data request instruction of a field device sent by a controller of a main station through a DP protocol and sends the instrument data request instruction to the FPGA chip, the FPGA chip sends the instrument data request instruction to the ARM processor through an FF protocol, the ARM processor sends the instrument data request instruction to the field FF device through the FF protocol, the field FF device returns instrument data to the ARM processor, the ARM processor sends the instrument data to the FPGA chip, the FPGA chip sends the instrument data to the MCU, and the MCU uploads the instrument data to the controller, so that the communication between the controller of the main station and the field FF device is completed, compared with the mode that the data transmission between the field FF device and the controller of the main station is realized through a longer link such as a PC and the like in the prior art, the invention only needs the mutual cooperation of the MCU, the ARM processor and the FPGA chip to complete the communication between the main station and the field FF device, the data transmission efficiency is greatly improved, and the cost is reduced.

Correspondingly, the embodiment of the present invention further provides a DP-to-FF method corresponding to the DP-to-FF communication gateway, which has the above technical effects and is not described herein again.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a block diagram of a DP-to-FF communication gateway according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a distributed control system integrated with field FF devices according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an FF bus circuit according to an embodiment of the invention;

FIG. 4 is a block diagram of a DP hardware circuit according to an embodiment of the present invention;

FIG. 5 is a schematic block diagram of a station address switch according to an embodiment of the present invention;

FIG. 6 is a logic diagram of a station address in an embodiment of the present invention;

fig. 7 is a flowchart illustrating an implementation of a method for converting DP to FF according to an embodiment of the present invention.

The drawings are numbered as follows:

the system comprises a 1-DP bus, a 2-controller, a 3-FF-H1 bus, a 4-IO slave station, a 5-field FF device, a 6-DP to FF communication gateway, a 61-MCU, a 62-FPGA chip and a 63-ARM processor.

Detailed Description

In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

As shown in fig. 1, the DP-to-FF communication gateway provided in the embodiment of the present invention may include an MCU61, an ARM processor 63, and an FPGA chip 62, where the MCU61 and the ARM processor 63 are both connected to the FPGA chip 62, where:

the MCU61 is used for receiving an instrument data request instruction of the field FF device sent by the controller of the main station through a DP protocol and sending the instrument data request instruction to the FPGA chip 62; uploading the instrument data to a controller;

the FPGA chip 62 is used for sending the instrument data request instruction to the ARM processor 63 through the FF protocol; sending the received meter data to the MCU 61;

the ARM processor 63 is used for sending the instrument data request instruction to the field FF equipment through the FF protocol and the FPGA chip 62; and receives meter data returned by the field FF device and sends the meter data to the FPGA chip 62.

As shown in fig. 2, fig. 2 is a schematic structural diagram of a distributed control system integrating field FF devices in an embodiment of the present invention, where a controller 2 of a master station in the distributed control system performs data interaction with an IO slave station 4 through a DP bus 1, and may need to control a field FF device 5, that is, the field FF device 5 is controlled through a DP-to-FF communication gateway 6 provided in the embodiment of the present invention. The DP-to-FF communication gateway 6 can be connected to a base through an European connector, can be configured to be used as a single machine or used as redundancy, can be used as a middle node or a tail node in a non-redundant FF-H1 bus network to carry out FF-H1 communication with field FF equipment through setting a terminal resistor on the base, and can carry out DP communication with the controller 2 in a redundant DP bus network. For a higher-level DP bus network facing a DCS system, a DP-to-FF communication gateway 6 is a DP slave station and only occupies one node of a higher-level DP master station system; the DP-to-FF communication gateway 6 is an FF-H1 master station, is an LAS (Link Active Scheduler) on the FF-H1 bus 3, and the lower field FF device 5 does not occupy a node address of the upper DP bus system. As shown in fig. 1, the DP-to-FF communication gateway 6 may include an MCU61, an ARM processor 63, and an FPGA chip 62, both the MCU61 and the ARM processor 63 are connected to the FPGA chip 62, the MCU61 is configured to receive, through a DP protocol, a meter data request instruction of the field FF device 5 sent by the controller 2 of the master station, and send the meter data request instruction to the FPGA chip 62, the FPGA chip 62 sends the meter data request instruction to the ARM processor 63 through an FF protocol, the ARM processor 63 runs the FF protocol, sends the meter data request instruction to the field FF device 5 through the FPGA chip 62 and the FF-H1 bus 3, receives meter data returned by the field FF device 5, and sends the meter data to the FPGA chip 62, the FPGA chip 62 sends the received meter data to the MCU61, and the MCU61 uploads the meter data to the controller 2. An isolation circuit may be disposed between the FPGA chip 62 and the field FF device 5 to isolate the DP-to-FF communication gateway 6 from the field FF device 5. The input field 24V power supply is converted into a +5V power supply through a DC/DC isolation and power supply conversion circuit to supply power to the MCU61, the FPGA chip 62, the ARM processor 63 and the DP communication part. In addition, the input field 24V power supply is also converted into a +24V power supply through an isolation DC/DC isolation and power supply conversion circuit to be used as the field power supply, and the power supply is used for supplying power to a Media Attachment Unit (MAU) circuit of the FF-H1.

Under the support of real-time embedded software and configuration interface software, the system is optimally controlled through a DP control network and an FF-H1 field bus 3 by utilizing a data interface provided by matched software. Various FF bus intelligent instruments, execution mechanisms, high-low voltage intelligent protection devices, electromagnetic valves and the like are connected to the main DCS, and meanwhile management information, equipment maintenance information and the like of FF equipment enter the DCS and upper-layer SIS/MIS software through a field bus, so that the optimized operation and optimized maintenance management of the unit are realized.

The DP-to-FF communication gateway provided by the embodiment of the invention is simple and easy to use, has a simple external interface, can be used for an engineer to master the correct use of the device through simple training, has low cost, and can upload the instrument data of the field FF equipment 5 to a DCS.

FF-H1 bus 3 is a half-duplex bus-type data communication system. The MAU is a critical component in a bus-powered fieldbus instrument. As shown in FIG. 3, the analog switch peripheral circuit constitutes the power of the MAUFlat switching circuit of from V_cc1、V_cc2And V_cc3Supplying power with high, middle and low reference voltages set to V_h、V_mAnd V_lBecause two address lines of the analog switch are connected with a pull-down resistor R₁、R₂The input signal A is set by a binary algorithm₀＝0，A₁When equal to 0, select switch S₀Closed, output voltage V_sout＝V_mWhen A is₀＝0，A₁When 1, select switch S₁Closed, output voltage V_sout＝V_mWhen A is₀＝1，A₁When equal to 0, select switch S₂Closed, output voltage V_sout＝V_hWhen A is₀＝1，A₁When 1, select switch S₃Closed, output voltage V_sout＝V_l. For example, at power-up, when the input signal is A₀＝0，A₁＝0，V_sout＝V_mFrom A to A₃、A₄The voltages at two ends of the operational amplifier circuit formed by the same devices are equal, and the current I can be calculated to be only subjected to V_mAnd R_fIt is determined that the circuit has a constant current characteristic in the normal range of FF-H1 bus 3 voltage. In signaling, the MAU draws current from FF-H1 bus 3 with Manchester code positive and negative symmetry. MAU Signal reception portion routing A₁～A₂Is composed of an operational amplifier A₂And the circuit forms an active band-pass filter with a preset central frequency and a hysteresis comparator A behind the active band-pass filter₁In combination, noise can be filtered, FF-H1 carrier signals are converted into digital signals, the digital signals are connected to the FF-H1 bus 3 through the diode FF, circuit protection is carried out through the diode FF, and the digital signals are isolated from the DP-to-FF communication gateway 6 through the isolation circuit, so that the influence on the DP-to-FF communication gateway 6 and a main station caused by the fault of the field FF equipment 5 is avoided.

The MCU61 can select STM32F100R8T6 of ST company, it adopts 32-bit Cortex-M3 inner core based on ARM framework, combine executing 32-bit Harvard micro-system structure and system peripheral hardware of Thumb-2 order, the system clock is the highest 24MHz, the chip performance reaches 1.25DMIPS/MHz, embed 64 kbyte solid state memory and animation editor FLASH and 8 kbyte static random access memory SRAM, the resource is abundant on chip, can meet the system design demand completely in function.

The ARM processor 63 may be selected from LPC2214FBD144, surface mount, TQFP package, 144 pins. The FLASH memory is integrated with an on-chip RAM of 16KB and an on-chip FLASH of 256 KB.

Data forwarding of the DP-to-FF communication gateway 6, long-time fault judgment, reading of the state of a monitoring power supply, state display of a channel lamp and the like are basically completed by hardware logic. The hardware programmable logic device adopts a spartan-6 series xc6slx9 device of the company Cen Linx, which has 5720 LUTs (lookup tables), 9152 LCs (logic units), 11440 FFs (flip-flops), 32 Block RAMs (18kb each), 102 maximum user pins and 144-pin TQFP packaging.

The DP bus communication chip can adopt SN65HVD06D of TI company, and the main indexes are as follows: the communication rate can reach 10 Mbps; minimum differential output voltage 2.5V (54 Ω load); ESD protection in excess of 16 KV; the hot plug device has power-on and power-off protection functions and supports hot plug.

By applying the DP-to-FF communication gateway provided by the embodiment of the present invention, the MCU61 receives the instrument data request instruction of the field device sent by the controller of the master station through the DP protocol, and sends the instrument data request instruction to the FPGA chip 62, the FPGA chip 62 sends the instrument data request instruction to the ARM processor 63 through the FF protocol, the ARM processor 63 sends the instrument data request instruction to the field FF device through the FF protocol, the field FF device returns the instrument data to the ARM processor 63, the ARM processor 63 sends the instrument data to the FPGA chip 62, the FPGA chip 62 sends the instrument data to the MCU61, and the MCU61 uploads the instrument data to the controller, so as to complete the communication between the master station and the field FF device, compared to the prior art that data transmission between the field FF device and the master station controller is achieved through a longer link such as a PC, the present invention only needs the MCU61, The ARM processor 63 and the FPGA chip 62 are matched with each other to complete communication between the main station and the field FF device, so that the data transmission efficiency is greatly improved, and the cost is reduced.

In a specific embodiment of the present invention, the FPGA chip 62 is further configured to receive the diagnostic data and send the diagnostic data to the MCU 61; the diagnostic data comprises first diagnostic data for self-diagnosis of each device connected with the FPGA chip 62 in the DP-to-FF communication gateway 6, and second diagnostic data which is sent by an ARM processor 63 and is obtained by diagnosing field FF equipment;

the MCU61 is also used to upload diagnostic data to the controller 2.

The DP-to-FF communication gateway 6 needs to use the MCU61, the FPGA chip 62, and the ARM processor 63 as well as the auxiliary functions of other devices for transmitting the meter data between the controller 2 and the field FF device, and when there is an abnormality in each device, it can generate the first diagnostic data through self-diagnosis, and directly or indirectly report the first diagnostic data to the FPGA chip 62. The ARM processor 63 may also perform fault diagnosis on the field FF device 5, for example, when a fault such as loss of an instrument occurs, obtain second diagnostic data, and send the second diagnostic data to the FPGA chip 62, the FPGA chip 62 sends the first diagnostic data and the second diagnostic data to the MCU61, the MCU61 uploads the first diagnostic data and the second diagnostic data to the controller 2, and the controller may perform corresponding fault troubleshooting according to the received first diagnostic data and the second diagnostic data.

In an embodiment of the present invention, as shown in fig. 1 and fig. 4, the DP-to-FF communication gateway may further include a two-way DP transceiver circuit connected to the MCU61,

the MCU61 is specifically configured to receive an instrument data request instruction of the field FF device sent by the controller 2 through two DP transceiver circuits of the DP protocol; the meter data and diagnostic data are returned to the controller 2 via two DP transceiver circuits of the DP protocol.

As shown in fig. 1 and 4, the DP-to-FF communication gateway provided in the embodiment of the present invention may further include a two-way DP transceiver circuit connected to the MCU61, where the MCU61 is specifically configured to perform data interaction with the controller 2 of the master station through the two-way DP transceiver circuit of the DP protocol. The power section mainly supplies power to the MCU61, the dual-network switching controller and the DP transceiver circuit. The MCU61 is a controller of the DP transceiver circuit and mainly provides functions of transmitting serial data, receiving serial data, diagnosing a malfunction of the DP transceiver circuit, switching networks, and cutting off malfunctions. The DP dual-network of the DP to FF communication gateway is realized by a dual-universal asynchronous transceiver transmitter UART. When transmitting data, the MCU61 controls the transmit enable of the two DP transceiver circuits through CTRA and CTRB signals. The MCU61 selects TXDA or TXDB of the MCU61 to be connected to TXD through the SEL control dual net controller so that UARTA or UARTB will send data to both DP transceiver circuits simultaneously. RXDA and RXDB are receive ports that access UARTA and UARTB of MCU 61. Thus, the data of the dual network enters two UARTs at the same time, and the data of one UART is selected by the internal diagnosis and switching logic of the MCU61 for processing. The DP transceiver circuit can specifically select a 485 transceiver, the 485 transceiver completes the conversion from 485 differential signals to serial communication, and the DP transceiver consists of a 485 chip, a peripheral pull-down circuit and a protection circuit. The differential signal of the 485 transceiver is connected to the DP bus through the European connector for communication.

In an embodiment of the present invention, the FPGA chip 62 is further configured to collect slave station address information.

When the master station performs data interaction with the slave station, the station address information of the slave station needs to be acquired, and the FPGA chip 62 provided in the embodiment of the present invention may also be used to acquire the slave station address information.

In one embodiment of the present invention, as shown in fig. 5 and 6, the FPGA chip 62 is specifically configured to collect slave station address information set by means of a decimal jumper cap.

The FPGA chip 62 may be specifically configured to collect slave station address information set by way of a decimal jumper cap. The module reads the switching circuitry located on the module and the jumpers on the base to obtain the station address. As shown in fig. 5, the station address of the DP-FF communication gateway needs two rows of pins, each row has a pair of pins inserted into the crowbar, and the address of each IO slave station can be set to 10-109. The row pins in the left column represent digits 1-10 of ten digits of the station address, and the row pins in the right column represent digits 0-9 of one digit of the station address. Among them, COM1 to COM2 form ten-digit rows, No.1 to No.5 form columns which can form 10 states in total, COM3 to COM4 form one-digit rows, and No.1 to No.5 form columns which can form 10 states, and thus 100 addresses can be represented.

As shown in fig. 6, the process of reading the station address information is as follows: first, when the MCU61 is initialized, the/OE _ MCU61_ mouse,/OE _ status _ ADDR,/OE _ ST _ ADDR _ COM signals are initialized to a high level, and the LE _ ST _ ADDR _ COM signals are initialized to a low level. Reading station address bits 0-4, assuming the crowbar shorts address No. 4, MCU61 pin/OE _ ST _ ADDR _ COM sends a low signal, chip select 74LVC573 chip, data bus [ DB 0: DB4] outputs 0x 1E. The MCU61 then asserts a high level through pins LE _ ST _ ADDR _ COM latching data bus DB [0:4] data 0x 1E. Since each chip select and data terminal of the tristate gate 74LVTH125 is connected together, when the input is low level, the low level is output; when the input is high, the output is tri-state. Thus, the output terminal COM1 of the 74LVTH125 is low, and COM2, COM3 and COM4 are tri-stated. Therefore, the station address within the range of 0-4 bits can be read through the jumper wire on the base. The MCU61 then asserts the high/OE _ ST _ ADDR _ COM signal and the low/OE _ STATION _ ADDR signal, the chip select read STATION address 74LVT245 chip. Since the short-circuiting device short-circuits the address No. 4, the COM1 can transmit a low-level signal to the data line DB0 through a jumper wire. The other addresses are kept at the high level of the pull-up because there is no crowbar. Thus, MCU61 has data bits 0x0F on the data bus. The MCU61 obtains STATION addresses within the range of bits 0-4 by reading the data bus DB [0:4], and then the MCU61 sends out a high-level/OE _ STATION _ ADDR signal to complete reading. The station address bits 5-9 are read, which is similar to the station address of the range of read bits 0-4. The reading station address tens 1-5 and the reading station address tens 6-10 are similar to the reading station address of the unit bit 0-4 range.

When more than one short-circuit device exists in the jumper bit or ten bits at the same time, the MCU61 considers that there is a fault and cannot read the station address information. When no short exists on the jumper bits and the tens bits, the MCU61 considers that there is a fault and the station address information cannot be read. Since the 74 device of the station address circuit needs to increase the hot plug grade, the LVT logic device is selected to support the 2-grade hot plug. Because the 74LVC573 is not high in antistatic and hot-plug protection level and does not support tri-state, a 74LVTH125 supporting a 2-level hot-plug level is added after the 74LVC573, and a clamping diode is added on an output circuit to protect static electricity. 74LVT245 and the protection circuit are capable of resisting static electricity and supporting hot plugging.

Corresponding to the above DP to FF communication gateway, the embodiments of the present invention further provide a DP to FF method, and a DP to FF method described below and a DP to FF communication gateway described above may be referred to correspondingly.

Referring to fig. 7, which is a flowchart illustrating an implementation of a method for converting DP to FF in an embodiment of the present invention, the method may include the following steps:

s701: the MCU receives an instrument data request instruction of the field FF equipment sent by the controller of the main station through the DP protocol, and sends the instrument data request instruction to the FPGA chip.

S702: and the FPGA chip sends the instrument data request instruction to the ARM processor through the FF protocol.

S703: the ARM processor sends the instrument data request instruction to field FF equipment through an FF protocol and an FPGA chip; and receiving the instrument data returned by the field FF equipment, and sending the instrument data to the FPGA chip.

S704: and the FPGA chip sends the received instrument data to the MCU.

S705: the MCU uploads the meter data to the controller.

By applying the method for converting DP to FF provided by the embodiment of the invention, the MCU receives an instrument data request instruction of a field device sent by a controller of a main station through a DP protocol and sends the instrument data request instruction to the FPGA chip, the FPGA chip sends the instrument data request instruction to the ARM processor through an FF protocol, the ARM processor sends the instrument data request instruction to the field FF device through an FF protocol, the field FF device returns instrument data to the ARM processor, the ARM processor sends the instrument data to the FPGA chip, the FPGA chip sends the instrument data to the MCU, the MCU uploads the instrument data to the controller, thereby completing the communication between the main station and the field FF device, compared with the prior art that the data transmission between the field FF device and the controller of the main station is achieved through a long link such as a PC, the invention only needs the mutual cooperation of the MCU, the ARM processor and the FPGA chip to complete the communication between the main station and the field FF device, the data transmission efficiency is greatly improved, and the cost is reduced.

In one embodiment of the present invention, the method may further comprise the steps of:

the method comprises the following steps: the FPGA chip receives the diagnosis data and sends the diagnosis data to the MCU; the diagnosis data comprises first diagnosis data for self-diagnosis of each device connected with the FPGA chip in the DP-to-FF communication gateway and second diagnosis data which is sent by an ARM processor and is obtained by diagnosing field FF equipment;

step two: the MCU uploads the diagnostic data to the controller.

In an embodiment of the present invention, the receiving, by the MCU through the DP protocol, the instrument data request command of the field FF device sent by the controller of the master station may include the following steps:

the method comprises the following steps that an MCU receives an instrument data request instruction of the field FF equipment sent by a controller through two DP transceiving circuits of a DP protocol;

step S705 may include the steps of:

the MCU uploads the instrument data to the controller through two DP transceiving circuits of a DP protocol;

the MCU uploads the diagnostic data to the controller, and may include the steps of:

the MCU uploads the diagnosis data to the controller through two DP transceiving circuits of the DP protocol.

and the FPGA chip acquires slave station address information.

In a specific embodiment of the present invention, the acquiring the slave station address information by the FPGA chip may include the following steps:

and the FPGA chip acquires slave station address information set in a decimal jumper cap mode.

The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. For the method disclosed by the embodiment, since the method corresponds to the DP-to-FF communication gateway disclosed by the embodiment, the description is simple, and the relevant points can be referred to the description of the method part.

Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims

1. The utility model provides a DP changes FF communication gateway which characterized in that, includes MCU, ARM treater and FPGA chip, MCU with the ARM treater all with the FPGA chip links to each other, wherein:

the ARM processor is used for sending the instrument data request instruction to the field FF equipment through the FF protocol and the FPGA chip; receiving instrument data returned by the field FF equipment, and sending the instrument data to the FPGA chip;

the DP is a field bus technology used for factory automation workshop level monitoring and field device layer data communication and control; FF is a field-based local area network for connecting intelligent devices, providing control applications to the entire network.

2. The DP-to-FF communication gateway of claim 1, wherein the FPGA chip is further configured to receive diagnostic data and send the diagnostic data to the MCU; the diagnosis data comprises first diagnosis data for self-diagnosis of each device connected with the FPGA chip in the DP-to-FF communication gateway and second diagnosis data which is sent by the ARM processor and is obtained by diagnosing the field FF equipment;

the MCU is also used for uploading the diagnosis data to the controller.

3. The DP-to-FF communication gateway of claim 2, further comprising a two-way DP transceiver circuit connected to the MCU,

4. The DP-to-FF communication gateway of claim 1, wherein the FPGA chip is further configured to collect slave station address information.

5. The DP-to-FF communication gateway of claim 4, wherein the FPGA chip is specifically configured to collect slave station address information set by way of a decimal jumper cap.

6. A method of DP-to-FF, the method comprising:

the FPGA chip sends the received instrument data to the MCU;

the MCU uploads the instrument data to the controller;

7. The method of claim 6, further comprising:

and the MCU uploads the diagnosis data to the controller.

8. The method of claim 7, wherein the MCU receives a meter data request command of the field FF device from the controller of the master station via the DP protocol, comprising:

9. The method of claim 6, further comprising:

and the FPGA chip acquires slave station address information.

10. The method of claim 9, wherein the FPGA chip collects slave station address information, comprising: