KR20130033829A - Liquid crystal display device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A liquid crystal display device and a method for manufacturing the same are provided to connect a pixel bar to a pad, to form a second protection layer and a pixel electrode at the same time using a halftone mask, and to prevent the contact fault of the pixel bar. CONSTITUTION: A second contact hole(185) is formed on a second protection layer on a pixel bar(244). A pixel electrode is formed on the second contact hole. The pixel bar is connected to a pad(242) using a bridge layer(280) composed of a contact pattern and a lower metal. Even if the pixel electrode is collapsed in a contact area, the connection between the pad and the pixel bar using the bridge layer prevents the disconnection of the contact.

Description

Liquid crystal display and its manufacturing method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and in particular, by forming a protective layer (PAS) and a pixel electrode at the same time in a single mask process using a half tone mask to increase manufacturing efficiency, The present invention relates to a liquid crystal display and a method for manufacturing the same, which can prevent contact failure due to loss.

Recently, in the application of a touch screen to a liquid crystal display, development has been made in a form in which a touch screen is embedded in a liquid crystal panel for slimming. In particular, an in-cell touch type liquid crystal display using a common electrode formed on a lower substrate as a touch sensing electrode has been developed.

1 is a view showing a liquid crystal display device according to the prior art, Figure 2 is a view showing a pixel structure of the liquid crystal display device according to the prior art.

1 and 2 illustrate a TFT array substrate (lower substrate) structure in a FFS (Fringe Field Switch) mode, and show that a touch screen is embedded in a TFT array substrate in an in-cell touch type.

1 and 2, illustration of a color filter array substrate (upper substrate) and a liquid crystal layer, and a driving circuit portion for driving the liquid crystal panel is omitted.

The display area 1 in which an image is displayed is formed in a TFT array substrate, and the some pad part 3, 4, 5 is formed in the non-display area of an outer part.

A plurality of pixels is formed in the display area 1.

The plurality of pad portions 3, 4, and 5 may include a unit on-off pad portion 3, a unit FPC pad portion / unit FPC shorting connection 4, unit_fpc_pad, unit_fpc_shorting, and bump input dummy / bump output dummy. (5, bump_input_dmy, bump_output_dmy).

In FIG. 1, the pad part is formed outside the upper end of the panel, but the pad part may also be formed on the left and right outer sides and the lower end of the panel.

Each of the pixels formed in the display area is defined by data lines (not shown) and gate lines (not shown) that cross each other. A thin film transistor (TFT) is formed in each region where the data lines intersect the gate lines.

Referring to FIG. 2, a pixel of the liquid crystal display according to the related art includes a TFT, a common electrode 60, and a pixel electrode 90 formed on the glass substrate 10.

In detail, the pixel may include a light shielding layer 20, a buffer layer 22, a TFT, a gate insulating layer 36 (GI), an interlayer insulating layer 40 (ILD), and a plurality of layers. the protective layer (50, 80: PAS1, PAS2 ), the data contacts (45, data contact), a common electrode (60, Vcom electrode), the touch sensing lines ^{(70, sensing line (3 rd} metal)) and a pixel electrode (90 , pixel electrode).

The TFT is composed of an active 30 formed under the gate insulating layer 36, a source 32, a drain 34, and a gate 38 formed over the gate insulating layer 36.

The touch sensing line 70 is formed on the common electrode 60 to cross the pixels to connect the common electrodes 60 of the pixels.

Here, the common electrode 60 performs the function of supplying the common voltage Vcom to the pixel in the display period, and performs the function of the touch sensing electrode for detecting the touch in the non-display period.

The pixel having the above-described configuration is formed through the manufacturing method shown in FIG.

3 is a view showing a problem according to the manufacturing method of the liquid crystal display according to the prior art. In FIG. 3, a drawing of a manufacturing method for forming layers formed under the interlayer insulating layer 40 is not shown.

Referring to FIG. 3, the first protective layer 50 (PAS1) is formed of the interlayer insulating layer 40 photo acryl, and the region overlapping with the data contact 45 is etched to form the first contact hole 55. ). In this case, the first protective layer 50 is formed to a thickness of 3um, and the upper surface of the data contact 45 is exposed by the first contact hole 55.

Subsequently, the common electrode 60 may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO) in the pixel area of the upper portion of the first passivation layer 50. To form.

Thereafter, the touch sensing line 70 is formed on the common electrode 60 to connect the common electrodes 60 of adjacent pixels.

Next, second protective layers 80 and PAS2 are formed on the first protective layer 50 to cover the common electrode 60 and the touch sensing line 70.

Subsequently, the second passivation layer 80 (PAS2) is etched to expose the top surface of the data contact 45 by performing a photolithography process and an etching process using a half tone mask to thereby expose the second contact hole 85. ).

In addition, the photoresist 95 (PR) is applied on the second protective layer 80, and indium tin oxide (ITO), indium zinc oxide (IZO), or the like is formed on the photoresist 95 to form a pixel electrode. A pixel electrode layer is formed of indium tin zinc oxide (ITZO) material.

Thereafter, the pixel electrode layer is patterned, the photoresist 95 is ashed, and a lift off process is performed to form the pixel electrode 90 in a finger shape.

In this case, the pixel electrode 90 is formed in a pinker shape on the second passivation layer 80 by using the halftone region of the halftone mask. Then, the second protective layers 80 and PAS2 in the region overlapping with the data contact 45 are etched using the full tone region of the halftone mask. The pixel electrode 90 is also formed in the second contact hole 85 to contact the data contact 45 and the pixel electrode 90.

In the liquid crystal display according to the related art, the first protective layer 50 is formed to a thickness of 3 μm, and the photoresist 95 is coated to a thickness of 2 μm to 3 μm.

When the photoresist 95 is coated, the flattening characteristics of the photoresist 95 increase the thickness of the portion where the photoresist 95 is formed in the portion corresponding to the futon region, 5 μm to 6 μm. In this case, the photoresist 95 applied to form the pixel electrode 90 during the manufacturing process may remain in the contact hole without being removed during the ashing process.

Specifically, the thickness (3um) of the first protective layer 50 is added to the target thickness (0.5um to 1.0um) of the halftone region, so that the photoresist 95 is 3.5um to 5.5 on the sidewall portion of the contact hole. It will remain in the thickness of um.

When the lift-off process is performed while the photoresist 95 remains, the port resist 95 is stripped in the contact hole, causing the pixel electrode 90 to be lost.

After the ashing of the photoresist 95, the lift-off process removes the photoresist 95 remaining in the contact hole, and also removes the pixel electrode 90 formed in the contact hole.

4 is a diagram illustrating a problem that disconnection of a pixel bar occurs in a pad part of a liquid crystal display according to the related art. In FIG. 4, the FPC pad part / unit FPC shorting connection part 4, unit_fpc_pad and unit_fpc_shorting among the plurality of pad parts 3, 4, and 5 are illustrated.

Referring to FIG. 4, among the plurality of pad parts 3, 4, and 5, the FPC pad part / unit FPC shorting connection part 4, unit_fpc_pad, unit_fpc_shorting may include a plurality of pads 12, a pixel bar 14, and a pixel bar 14. ) And power line 16.

The FPC pad part / unit FPC shorting connection part 4 formed on the outer side of the panel 4 is formed using a manufacturing process for forming pixels of the display area.

The first contact layer 55 is formed by widely etching the first passivation layer 50 (PAS1). A plurality of pixel pads are arranged in the first contact hole 55, and the pad 12 and the pixel bar 14 are connected to each other.

In this case, the pixel electrode 90 formed in the pad region does not function as an electrode to which a data voltage is supplied as the pixel electrode of the pixel region, but functions as a contact connecting the pixel bar 14 to the pad 12.

During the manufacturing process, a pixel region in which the second contact hole 85 does not exist is formed by using the halftone region. As a result, the pixel is formed on the second protective layer 80 in the pad region in the same manner as the pixel region. The problem that the electrode 90 is lost may occur.

As such, when the pixel electrode 90 is lost in the pad region, a signal cannot be supplied to a plurality of pixels formed in the display region, so that inspection of the completed panel can not be performed smoothly, and an image cannot be displayed normally. There is a problem that a defect occurs.

As a method for preventing contact failure of the pixel bar 14 due to the loss of the pixel electrode 90, the pad 12 and the pixel bar 14 may be formed using a metal of the touch sensing line 70 during the manufacturing process. Can be connected.

However, after the inspection of the panel is completed, the pad 12 and the pixel bar 14 are cut along the scribe line so that the metal connecting the pad 12 and the pixel bar 14 is exposed to the outside. There is a problem that is difficult to apply.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and provides a liquid crystal display device and a method of manufacturing the same, which may improve the manufacturing efficiency by simultaneously forming a protective layer and a pixel electrode in a single mask process using a half tone mask. It is technical problem to do.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and to provide a liquid crystal display device and a method of manufacturing the same, which can prevent disconnection in a pad region caused by a loss of a pixel electrode due to a lift off process. It is a task.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-described problems, and it is an object of the present invention to provide a liquid crystal display and a method of manufacturing the same, which can improve the contact performance of a pixel bar in a pad region.

Other features and advantages of the invention will be set forth in the description which follows, or may be obvious to those skilled in the art from the description and the claims.

A liquid crystal display according to an embodiment of the present invention is a liquid crystal display in which a pad portion including a pad area having a pad and a contact area where a pixel bar is formed is formed at an outer portion of the panel, the upper portion of the first protective layer of the pad area; A bridge layer formed over the first passivation layer and the first contact hole region of the contact region; A second protective layer formed to cover the bridge layer; At least one second contact hole formed by removing the second passivation layer in the second passivation layer of the pad region and the overlapping contact bar of the contact region from the pad region; And a contact electrode formed of a transparent conductive material on the pad region and on the contact region, wherein the pad of the pad region and the pixel bar of the contact region are connected through the bridge layer.

In the manufacturing method of the liquid crystal display according to the embodiment of the present invention, a pad portion including a pad region having a pixel pad and a contact region having a pixel bar is formed in the outer portion of the panel, wherein the pad region and Forming a first protective layer in the contact region, and removing a portion of the first protective layer in the contact region to form a first contact hole; Forming a bridge layer on the first passivation layer of the pad area, and forming a bridge layer on the first passivation layer and the first contact hole area of the contact area; Forming a second protective layer to cover the first protective layer and the bridge layer; Forming at least one second contact hole by removing a portion of a second passivation layer in an area overlapping the pad area and the bridge layer of the contact area; And forming a pixel electrode by applying a transparent conductive material on the pad region and the contact region, and connecting the pad of the pad region and the pixel bar of the contact region through the bridge layer.

In the method of manufacturing the liquid crystal display according to the exemplary embodiment of the present invention, the protective layer and the pixel electrode may be simultaneously formed in a single mask process using a half tone mask to increase manufacturing efficiency.

The manufacturing method of the liquid crystal display according to the exemplary embodiment of the present invention can prevent disconnection in the pad region caused by the loss of the pixel electrode by the lift off process.

The liquid crystal display according to an exemplary embodiment of the present invention and a method of manufacturing the same may improve the contact performance of the pixel bar in the pad area.

In addition, other features and advantages of the present invention may be newly understood through embodiments of the present invention.

1 is a view showing a liquid crystal display device according to the prior art.
2 illustrates a liquid crystal display pixel structure according to the prior art.
3 is a view showing a problem according to the manufacturing method of the liquid crystal display device according to the prior art.
4 is a diagram illustrating a problem that disconnection of a pixel bar occurs in a pad part of a liquid crystal display according to the related art.
5 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
6 is a diagram illustrating a pixel structure of a liquid crystal display according to an exemplary embodiment of the present invention.
7 is a diagram illustrating a pad portion of a liquid crystal display according to an exemplary embodiment of the present invention.
FIG. 8 is an enlarged view of a contact area of a pad unit shown in FIG. 7; FIG.
FIG. 9 is a cross-sectional view taken along lines A1-A2 and B1-B2 shown in FIG. 7; FIG.
10 to 14 illustrate a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention.

Hereinafter, a liquid crystal display and a method of manufacturing the same in which a touch screen is built according to embodiments of the present invention will be described with reference to the accompanying drawings.

In describing embodiments of the present invention, when a structure (electrode, line, wiring layer, contact) is described as being formed "on or under" and "under or under" another structure, such descriptions may be It should be interpreted as including not only the case where they are in contact with each other, but also when a third structure is interposed between these structures.

In addition, the expressions "above or on" and "below or below" are intended to explain the configuration and manufacturing method of the present invention based on the drawings. Thus, the expressions "above or above" and "below or below" may differ from each other in the manufacturing process and in the configuration after manufacture is complete.

Liquid crystal displays have been developed in various ways, such as twisted nematic (TN) mode, vertical alignment (VA) mode, in plane switching (IPS) mode, and fringe field switching (FFS) mode.

In the IPS mode and the FFS mode, a pixel electrode and a common electrode are disposed on a lower substrate to adjust the arrangement of the liquid crystal layer by an electric field between the pixel electrode and the common electrode.

Particularly, in the IPS mode, the pixel electrode and the common electrode are alternately arranged in parallel to each other to generate a transverse electric field between both electrodes to adjust the alignment of the liquid crystal layer.

The IPS mode has a disadvantage in that the arrangement of the liquid crystal layer is not controlled in the upper portion of the pixel electrode and the common electrode, so that light transmittance in the region is reduced.

The FFS mode is designed to overcome the shortcomings of the IPS mode. In the FFS mode, the pixel electrode and the common electrode are formed to be spaced apart with an insulating layer therebetween.

In this case, one electrode is configured in a plate shape or a pattern and the other electrode is configured in a finger shape to adjust the arrangement of the liquid crystal layer through a fringe field generated between the two electrodes. That's the way.

According to embodiments of the present invention, a liquid crystal display having a touch screen includes an in-cell touch type liquid crystal panel having a touch screen for detecting a touch position of a user, and light to the liquid crystal panel. It is configured to include a backlight unit (Back Light Unit) and a driving circuit for supplying.

The driving circuit unit includes a power supply unit for supplying driving power to a timing controller T-con, a data driver D-IC, a gate driver G-IC, a sensing driver, a backlight driving unit, and driving circuits.

Here, all or part of the driving circuit unit may be formed on the liquid crystal panel in a chip on glass (COG) or chip on flexible printed circuit (chip on film) method.

5 is a diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 6 is a diagram illustrating a pixel structure of a liquid crystal display according to an exemplary embodiment of the present invention.

5 and 6 show a TFT array substrate (lower substrate) structure in a FFS (Fringe Field Switch) mode, and show that the touch screen is internalized in the TFT array substrate in an in-cell touch type.

5 and 6, illustration of the color filter array substrate (upper substrate), the liquid crystal layer, the backlight unit, and the driving circuit portion is omitted.

Referring to FIG. 5, a display area 100 in which an image is displayed is formed on a TFT array substrate, and a plurality of pad parts 230, 240, and 250 are formed in a non-display area 200 of an outer portion.

A plurality of pixels is formed in the display area 100.

The plurality of pad units 230, 240, and 250 formed in the non-display area 200 may include a unit on-off pad unit 230 and a unit FPC pad unit / unit FPC shorting connection unit 240 (unit_fpc_pad and unit_fpc_shorting). And bump input dummy / bump output dummy 250 (bump_input_dmy, bump_output_dmy).

In FIG. 5, the pad part is formed outside the upper end of the panel, but the pad part may also be formed on the left and right outer sides and the lower end of the panel.

Each of the pixels formed in the display area is defined by data lines (not shown) and gate lines (not shown) that cross each other. A thin film transistor (TFT) is formed in each region where the data lines intersect the gate lines.

A plurality of pixels are formed on the TFT array substrate, each of which is defined by data lines (not shown) and gate lines (not shown) that cross each other.

Thin film transistors (TFTs) are formed in regions where the data lines intersect the gate lines. In addition, each of the plurality of pixels includes a common electrode Vcom electrode and a pixel electrode.

Referring to FIG. 6, the TFT array substrate may include a glass substrate 110, a light blocking layer 120, a buffer layer 122, a buffer insulating layer, a gate insulator 136, a data contact 145, and an interlayer. Insulating layer 140 (ILD: Inter Layer Dielectric), first protective layer 150, common electrode 160, Vcom electrode, touch sensing line 170, second protective layer 180, pixel electrode 190 electrode) and a TFT consisting of an active 130, a source 132, a drain 134, and a gate 138.

The light blocking layer 120 is formed in the TFT region on the glass substrate 110, and the buffer layer 122 is formed to cover the light blocking layer 120. The light blocking layer 120 may be formed of molybdenum (Mo) or aluminum (Al), and may have a thickness of 500 μs.

The buffer layer 122 may be formed of an inorganic material, for example, SiO ₂ , or SiNx, and may have a thickness of 2,000 μs to 3,000 μs.

An active 130, a source 132, and a drain 134 of the TFT are formed in an area overlapping the light blocking layer 120 among the buffer layer 122 of the TFT region.

Here, the active 130 may be formed of low temperature polysilicon (P-Si), and may have a thickness of 500 μs. The source 132 and the drain 134 may be formed by doping P-type or N-type impurities into the semiconductor layer of the active 130.

A gate insulating layer 136 is formed on the upper front surface of the buffer layer 122 to cover the active 130, the source 132, and the drain 134. In this case, the gate insulating layer 136 may be formed of SiO ₂ , and may have a thickness of 1,300 μs.

The gate insulating layer 136 may be formed by depositing TEOS (Tetra Ethyl Ortho Silicate) or MTO (Middle Temperature Oxide) by Chemical Vapor Deposition (CVD).

A gate 138 is formed in an area of the gate insulating layer 136 that overlaps the active 130. In this case, the gate 138 may be formed of aluminum (Al) or molybdenum (Mo), and may have a thickness of 3,000 μm.

As such, the active 130, the source 132, the drain 134, and the gate 138 are formed with the gate insulating layer 136 interposed therebetween, thereby forming a TFT.

An interlayer insulating layer 140 is formed on the gate insulating layer 136 to cover the gate 138.

In this case, the interlayer insulating layer 140 may be formed of SiO ₂ or SiNx, and may have a thickness of 6,000 μs. As another example, the interlayer insulating layer 140 may also be formed in a structure of SiO ₂ (3,000 μs) / SiNx (3,000 μs).

A portion of the gate insulating layer 136 and the interlayer insulating layer 140 are etched to expose the top surface of the drain 134, and the data contact 145 is formed to be connected to the drain 134.

The data contact 145 connects the drain 134 and the pixel electrode 190 described later. In this case, the data contact 145 may be formed to have a thickness of 6,000 μm and may have a structure in which molybdenum (Mo) / aluminum (Al) molybdenum (Mo) is stacked.

The first passivation layer 150 (PAS1) is formed on the interlayer insulating layer 140 to cover the data contact 145. In this case, the first protective layer 150 is formed of photo acryl and has a thickness of 3 μm.

A common electrode 160 (Vcom electrode) is formed in the pixel area of the first passivation layer 150.

The common electrode 160 is a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO), and may be formed to have a thickness of 500 μs.

The touch sensing line 170 is formed on the common electrode 160 to cross the pixels to connect the common electrodes 160 of adjacent pixels. As a result, the common electrode 160 has a function of the touch sensing electrode in the non-display period.

Here, the touch sensing line 170 may be formed of molybdenum (Mo) or aluminum (Al), and may have a thickness of 1,500 kPa to 2,000 kPa. Meanwhile, the touch sensing line 170 may be formed in a structure in which molybdenum (Mo) / aluminum (Al) / molybdenum (Mo) is stacked.

The touch sensing line 170 connects the common electrodes 160 of adjacent pixels to form a touch block. In this case, the touch block includes a touch row block for detecting the touch position in the X-axis direction and a touch column block for detecting the touch position in the Y-axis direction.

Since the touch screen needs to recognize the coordinates of the X and Y axes in order to detect the touch position of the user, the touch row block and the touch column block should be separated from each other without contact.

To this end, the touch sensing line 170 of the touch column block is connected in the Y-axis direction by using a conductive line formed to overlap the data line of the TFT array substrate, so that the user's touch position is recognized in the Y-axis direction.

The touch sensing line 170 of the touch row block uses the gate metal formed together when the gate line is formed on the TFT array substrate as a bridge to avoid contact with the touch column block and to recognize the touch position of the user in the X-axis direction. do.

In this way, the touch row block and the touch column block are separated so that the touch position of the user is detected in the X and Y axis directions.

The second passivation layer 180 is formed on the first passivation layer 150 to cover the common electrode 160 and the touch sensing line 170. In this case, the second protective layer 180 may be formed of SiO ₂ or SiNx, and may have a thickness of 2,000 μs to 3,000 μs.

A first contact hole 155 is formed in an area of the first passivation layer 150 that overlaps the data contact 145.

The second passivation layer 180 is etched on the first contact hole 155 to form a second contact hole 185.

The pixel electrode 190 is formed in a pixel shape on the pixel area among the second passivation layer 180. The pixel electrode 190 is formed in the first contact hole 155 and the second contact hole 185 to be connected to the data contact 145. Through this contact structure, the drain 134 of the TFT and the pixel electrode 190 are connected via the data contact 145.

In this case, the pixel electrode 190 may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO), and may have a thickness of 500 μs.

The second passivation layer 180 and the pixel electrode 190 may be simultaneously formed through a single mask process using one half tone mask (HTM).

In the liquid crystal display according to the exemplary embodiment of the present invention, in the display period, the transmittance of light passing through the liquid crystal layer is adjusted according to the image signal according to the data voltage applied to the pixel electrodes of the pixels and the common voltage Vcom applied to the common electrode. Display an image.

In the non-display period, the common electrode 160 of each pixel connected by the touch sensing line 170 is driven by the touch sensing electrode to detect a change in capacitance Ctc according to a user's touch. The touch position TS is detected by comparing the touch capacitance according to the user's touch with the reference capacitance.

FIG. 7 is a view illustrating a pad portion of a liquid crystal display according to an exemplary embodiment of the present invention, FIG. 8 is an enlarged view of the contact area shown in FIG. 7, and FIG. 9 is a line A1-A2 shown in FIG. 7 and FIG. Sectional view along lines B1-B2.

7 to 9 illustrate a unit FPC pad unit / unit FPC shorting connection unit 240 among the plurality of pad units 230, 240, and 250, unit_fpc_pad and unit_fpc_shorting.

7 to 9, the unit FPC pad unit / unit FPC shorting connection unit 240 among the plurality of pad units 230, 240, and 250 may include a plurality of pads 242 and pads and a pixel bar 244. Or pixel lines) and power lines 246.

The unit FPC pad unit / unit FPC shorting connection unit 240 includes a pad area in which a plurality of pads 242 are formed, and a contact area connecting the pixel bar 244 and the pad 242.

The FPC pad unit / unit FPC shorting connection unit 240 is formed using a manufacturing process for forming a pixel, and each pad 242 has a structure in which a pad pattern for supplying a signal to the pixel is arranged.

In addition, a lower metal 270 and a pixel electrode 190 are formed in the contact area of the FPC pad part / unit FPC shorting connection part 240. In this case, the lower metal 270 and the pixel electrode 190 formed in the contact region are formed to be spaced apart from the first contact hole 155.

The pixel bar 244 and the pad 242 of the FPC pad unit / unit FPC shorting connection unit 240 are formed to be spaced apart from each other, and thus are not directly connected to each other. Is connected via).

The bridge layer 280 may be formed of a contact pattern 260 and a lower metal 270.

The contact pattern 260 may be formed on the same layer as the common electrode 160 in the pixel area, and the contact pattern 260 is formed of a transparent conductive material (ITO) that is a material of the common electrode 160.

The lower metal 270 may be formed using the metal of the touch sensing line 170 formed in the pixel area, and the lower metal 270 may be formed together when the touch sensing line 170 is formed.

In order to connect the pixel bar 244 and the pad 242, a second contact hole 185 is formed in the second passivation layer 180 on the pixel bar 244, and a pixel electrode 190 is formed thereon. . In this case, the pixel bar 244 and the pad 242 are connected using the bridge layer 280 formed of the contact pattern 260 and the lower metal 270.

Therefore, when the second protective layer 180 and the pixel electrode 190 are simultaneously formed using a photolithography process, an etching process, and a lift-off process using a halftone mask, even if the pixel electrode 190 is lost in the contact region. The pixel bar 244 and the pad 242 are connected to the bridge layer 280 so that the contact is not disconnected.

Here, the pixel bar 244 is formed at an interval of 20 um so as not to overlap with the first contact hole 155.

The second contact hole 185 formed on the pixel bar 244 is formed to have a size of 6um * 6um.

As illustrated in FIG. 7, one second contact hole 185 may be formed on one pixel bar 244. However, the present invention is not limited thereto, and in order to further improve the contact performance of the pixel bar 244, as illustrated in FIG. 8, a plurality of second contact holes 185 may be formed on one pixel bar 244. have.

The contact area of the pixel bar 244 uses a clear area during the manufacturing process, where the clear area is formed to have a smaller size than the lower metal 270. When the second protective layer 180 is etched to form the second contact hole 185, the lower metal 270 functions as an etch stop.

As shown in FIG. 9, the second contact hole 185 formed in the contact region is formed to have a smaller size than the lower metal 270. As an example, the second contact hole 185 is formed to have a size smaller than one side of the lower metal 270.

In addition to the unit FPC pad unit / unit FPC shorting connection 240, the on-off pad unit 230 and the bump input dummy / bump output dummy 250 may be connected to the pad 242 using the bridge layer 280 described above. The pixel bars 242 may be connected.

The pad part of the liquid crystal display according to the exemplary embodiment of the present invention having the above-described configuration forms a second contact hole 185 in the pixel bar 244 and includes a bridge formed of the lower metal 270 and the contact pattern 260. The pixel bar 244 may be connected to the pad 242 of the pad area using the layer 280. As a result, the second passivation layer 180 and the pixel electrode 190 may be simultaneously formed using the halftone mask while preventing contact failure of the pixel bar 244 in the pad region.

10 to 14 illustrate a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention.

10 to 14 illustrate manufacturing processes based on cross sections taken along lines A1-A2 and B1-B2 shown in FIG. 7, and a description of a manufacturing method for forming pixels in the display area is omitted.

Hereinafter, a method of manufacturing a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to FIGS. 10 to 14. A cross-sectional view along the lines A1-A2 shows a portion corresponding to one pad in the pad area. A cross-sectional view along the lines B1-B2 shows the contact area of the pixel bar.

Referring to FIG. 10, first protective layers 150 and PAS1 may be formed in the pad region and the contact region.

Subsequently, a portion of the first passivation layer 150 (PAS1) is etched by performing a photolithography process and an etching process using a halftone mask in the contact region. The region where the first protective layer 150 is etched becomes the first contact hole 155. The first protective layer 150 may be formed using a clear region of the halftone mask.

In this case, the first protective layer 150 may be formed of photo acryl and may have a thickness of 3 μm.

Thereafter, the contact pattern 260 and the lower metal 270 are sequentially formed in the pad region and the contact region to form the bridge layer 280.

In this case, in the contact region, the contact pattern 260 is formed in both the upper portion of the first passivation layer 150 and the region of the first contact hole 155. The lower metal 270 is formed only on the first passivation layer 150.

Here, the lower metal 270 serves as an etch stop of the second contact hole formed by etching the second protective layer in a subsequent process.

Subsequently, referring to FIG. 11, second passivation layers 180 and PAS2 are formed on the first passivation layer 150 and in the region of the first contact hole 155. In this case, the bridge layer 280 is covered with the second protective layer 180. The second passivation layer 180 may be formed of SiO ₂ or SiNx, and may have a thickness of 2,000 μs to 3,000 μs.

Next, referring to FIG. 12, after the photoresist 195 is coated on the second passivation layer 180, a photolithography process and an etching process using a halftone mask are performed.

In the pad region, the photoresist 195 in the region partially overlapping the bridge layer 280 is removed to form a clear region. In this case, the clear region is formed to have a smaller size than the lower metal 270.

Meanwhile, in the contact region, the photoresist 195 in an area partially overlapping the bridge layer 280 is removed to form a clear region.

The photoresist 195 of the portion not overlapping with the bridge layer 280 is formed as a halftone region or a normal region.

The upper portion of the second passivation layer 180 is exposed by the clear region formed in the pad region and the contact region.

Subsequently, referring to FIG. 13, the bridge layer 280 is exposed by removing the second protective layer 180 exposed by the clear region by performing an ashing process.

In detail, the second protective layer 180 of the clear region is removed from the pad region to form the second contact hole 185. The bridge layer 280 is exposed by the second contact hole 185.

In addition, the second protective layer 180 of the clear region is removed from the contact region to form the second contact hole 185. In this case, as illustrated in FIGS. 7 and 8, the second contact hole 185 formed in the contact region is formed on the pixel bar 244 to expose the pixel bar 244.

The second contact hole 185 formed on the pixel bar 244 is formed to have a size of 6um * 6um.

As illustrated in FIG. 7, one second contact hole 185 may be formed on one pixel bar 244. However, the present invention is not limited thereto, and in order to further improve the contact performance of the pixel bar 244, as illustrated in FIG. 8, a plurality of second contact holes 185 may be formed on one pixel bar 244. have.

The first contact hole 155 and the second contact hole 185 are formed using a clear region of the halftone mask.

14, the pixel electrode 190 is formed of a transparent conductive material such as ITO on the pad region.

In addition, the pixel electrode 190 may be formed of a transparent conductive material such as ITO on the periphery of the pad region and the contact region.

Here, the pixel bar 244 of the contact region and the pad 242 of the pad region are formed to be spaced apart from each other, and are not directly connected, but are connected through the bridge layer 280.

Therefore, a lift-off process is performed to simultaneously form the second passivation layer 180 and the pixel electrode 190, so that even if the pixel electrode 190 is partially lost in the pad region, the pad 242 and the pixel bar 244 may be removed. The contact will not be shorted.

Here, the pixel bar 244 is formed at an interval of 20 um so as not to overlap with the first contact hole 155.

The second contact hole 185 is formed to have a smaller size than the lower metal 270. As an example, the second contact hole 185 is formed to have a size smaller than one side of the lower metal 270.

In order to prevent the contact of the pixel bar 244 from breaking at the boundary of the first contact hole 155, the length of the contact pattern 260 of the bridge layer 280 in the contact area is extended to increase the length of the contact between the pixel bar 244 and the pixel bar 244. It is used as a bridge for the contact of the pad 242.

As a bridge for contacting the pixel bar 244, the contact pattern 260 may extend to the bottom of the pixel bar 244. In this case, the contact pattern 260 may be formed using all the transparent metals of the common electrode.

In addition to the unit FPC pad unit / unit FPC shorting connection 240, the on-off pad unit 230 and the bump input dummy / bump output dummy 250 may be connected to the pad 242 using the bridge layer 280 described above. The pixel bars 242 may be connected.

The size of the second contact hole 185 and the pad 242 of the second passivation layer 180 formed in the pad region may be changed, and may be a size that can be inspected by a probe tip.

The liquid crystal display according to the exemplary embodiment of the present invention and a method of manufacturing the same according to the exemplary embodiment of the present invention provide a manufacturing efficiency by simultaneously forming the second passivation layer 180 and the pixel electrode 190 in a single mask process using a half tone mask. Can increase.

In addition, when the pixel electrode 190 is formed, the pixel bar 244 may be prevented from being disconnected in the pad area caused by the loss of the pixel electrode 190 due to a lift off process. Through this, the contact performance of the pixel bar formed in the pad portion may be improved.

It will be understood by those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive.

The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: display area 200: non-display area
110: glass substrate 120: light shielding layer
122: buffer layer 130: active
132: source 134: drain
136: gate insulating layer 138: gate
140: interlayer insulating layer 145: data contact
150: first protective layer 155: first contact hole
160: common electrode 170: touch sensing line
180: second protective layer 185: second contact hole
190: pixel electrode 195: photoresist
242: Pad 244: Pixel Bar
246: power line 260: contact pattern
270: lower metal 280: bridge layer
230: unit on-off pad portion
240: unit FPC pad part / unit FPC shorting connection part
250: Bump Input Dummy / Bump Output Dummy

Claims (16)

A liquid crystal display device, wherein a pad portion including a pad region on which a pad is formed and a contact region on which a pixel bar is formed is formed on an outer portion of a panel.
A bridge layer formed over the first passivation layer of the pad region, over the first passivation layer and the first contact hole region of the contact region;
A second protective layer formed to cover the bridge layer;
At least one second contact hole formed by removing the second passivation layer in the second passivation layer of the pad region and the overlapping contact bar of the contact region from the pad region; And
And a contact electrode formed of a transparent conductive material on the pad region and on the contact region.
And a pad of the pad area and a pixel bar of the contact area are connected through the bridge layer. The method of claim 1,
The bridge layer is a liquid crystal display comprising a contact pattern formed of a transparent conductive material and a lower metal formed of an opaque conductive metal material. The method of claim 2,
In the contact region, the contact metal is formed on the first protective layer and the first contact hole region,
And the lower metal is formed on the first passivation layer. The method of claim 1,
And a second contact hole formed on the pixel bar having a size of 6 μm in width and 6 μm in length. The method of claim 1,
And the pixel bar is spaced apart from the first contact hole at a distance of 20 um from the first contact hole. The method of claim 1,
The size of the second contact hole is formed to be 10um smaller than the one side of the lower metal. The method of claim 1,
And the pad unit includes a unit on-off pad unit, a unit FPC pad / unit FPC shorting connection unit (unit_fpc_pad, unit_fpc_shorting), and a bump input dummy / bump output dummy. A method of manufacturing a liquid crystal display device, wherein a pad portion including a pad region on which a pixel pad is formed and a contact region on which a pixel bar is formed is formed at an outer portion of the panel.
Forming a first protective layer on the pad region and the contact region, and removing a portion of the first protective layer from the contact region to form a first contact hole;
Forming a bridge layer on the first passivation layer of the pad area, and forming a bridge layer on the first passivation layer and the first contact hole area of the contact area;
Forming a second protective layer to cover the first protective layer and the bridge layer;
Forming at least one second contact hole by removing a portion of a second passivation layer in an area overlapping the pad area and the bridge layer of the contact area; And
And forming a pixel electrode by applying a transparent conductive material on the pad region and the contact region.
And a pixel bar of the contact area and a pad of the pad area through the bridge layer. The method of claim 8,
Wherein the first contact hole and the second contact hole are formed using a clear region of a halftone mask. The method of claim 8,
And a second contact hole formed on the pixel bar having a width of 6 μm and a length of 6 μm. The method of claim 8,
And the pixel bar is formed to be spaced apart from the first contact hole at a distance of 20 um. The method of claim 8,
The size of the second contact hole is formed to be less than 10um than the one side of the lower metal, the manufacturing method of the liquid crystal display device. The method of claim 8,
The bridge layer may include a contact pattern formed of a transparent conductive material and a lower metal formed of an opaque conductive metal material. The method of claim 13,
The contact pattern is formed of a transparent metal of a common electrode formed in the display area,
And the lower metal is formed of a metal of a touch sensing line formed in the display area. The method of claim 8,
And the lower metal functions as an etch stop when the second protective layer is etched. The method of claim 8,
In the step of forming the second contact hole,
After applying the photoresist on the second protective layer, performing a photolithography process and an etching process using a halftone mask to form a normal region, a halftone region, and a clear region,
And removing the second protective layer through the clear region to form the second contact hole.

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