KR20130022030A - Light emitting diode - Google Patents

Light emitting diode Download PDF

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Publication number
KR20130022030A
KR20130022030A KR1020110084680A KR20110084680A KR20130022030A KR 20130022030 A KR20130022030 A KR 20130022030A KR 1020110084680 A KR1020110084680 A KR 1020110084680A KR 20110084680 A KR20110084680 A KR 20110084680A KR 20130022030 A KR20130022030 A KR 20130022030A
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South Korea
Prior art keywords
light emitting
layer
type
pad
pad portion
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KR1020110084680A
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Korean (ko)
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KR101803014B1 (en
Inventor
김종규
이소라
양명학
곽준식
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서울옵토디바이스주식회사
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Priority to KR1020110084680A priority Critical patent/KR101803014B1/en
Publication of KR20130022030A publication Critical patent/KR20130022030A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

A light emitting diode is disclosed. This light emitting diode comprises: a substrate; A plurality of light emitting cells formed on the substrate and each comprising a p-type region and an n-type region; And a wiring layer formed to connect the p-type region and the n-type region of neighboring light emitting cells. The wiring layer includes a laminated structure of a contact layer / reflective layer / barrier layer / bonding layer, wherein the contact layer is formed of Ni, Cr or Ti, the reflective layer is formed of Al, and the bonding layer is formed of Au. do.

Description

[0001] LIGHT EMITTING DIODE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to light emitting diodes comprising compound semiconductors, and more particularly, to an AC driven light emitting diode.

A light emitting diode is a light emitting device made of a compound semiconductor, in particular, a group III nitride-based compound semiconductor, and has been widely used in display devices and backlight devices. Use area is getting wider.

A typical light emitting diode is turned on / off in accordance with the direction of the current under AC power. Therefore, when the light emitting diode is directly connected to an AC power source, the light emitting diode does not emit light continuously and is easily damaged by reverse current. As a technology for solving the problem of the light emitting diode, a light emitting diode that can be used by connecting directly to a high voltage AC power source is disclosed in International Publication No. WO2004 / 023568 (A1) "Light-EMITTING DEVICE HAVING LIGHT -EMITTING ELEMENTS, which was disclosed by SAKAI et.al.

1 is a view for explaining a conventional AC light emitting diode. Referring to FIG. 1, the AC light emitting diode 1 includes rectangular light emitting cells 4 formed by forming a group III nitride-based compound semiconductor layer on an insulating substrate, in particular, a sapphire substrate 2. In addition, electrode pads 3a and 3b are formed on the substrate 2. Each of the light emitting cells 4 includes an n-type semiconductor layer, a p-type semiconductor layer, and an active layer interposed therebetween, and a transparent electrode layer such as an ITO layer may be formed thereon. In addition, the plurality of light emitting cells 4 are formed by dividing a plurality of stacked layers of the compound semiconductor layers as described above.

The conventional light emitting diode 1 includes an n-type electrode pad 6 and a p-type electrode pad 8 on the light emitting cell 4. The light emitting cell 4 is partially removed from the top to a certain depth to expose a part of the layer in the middle of the light emitting cell 4, which is usually an n-type semiconductor layer, and the exposed n-type semiconductor. An n-type electrode pad 6 is formed in one region of the layer. The p-type electrode pad 8 is formed in the p-side region in the uppermost layer of the light emitting cell 4. The n-type electrode pads 6 and the p-type electrode pads 8 are positioned to face each other while being positioned at opposite corners of the light emitting cell 4 while being formed in a straight or bar shape. The electrode pads 3a and 3b and the light emitting cells 4 therebetween are connected in series by the wirings 5. The p-type electrode pad 8 and the n-type electrode pad 8 of neighboring light emitting cells are connected by the wiring 5. Although shown separately, the wiring 5, the p-type electrode pad 8 and the n-type electrode pad 8 may be portions of the wiring layer formed together by a step cover process.

In the conventional light emitting diode, when the distance between the n-type electrode pad 6 and the p-type electrode pad 8 is large in the light emitting cell, the current concentrates only around the p-type electrode pad 8, so that p Only the periphery of the type electrode pad 8 emits light strongly. In addition, when the p-type electrode pad 8 is placed close to the n-type electrode pad 6, the brightness of the region between the p-type electrode pad 8 and the n-type electrode pad 6 will increase, but the p-type Brightness between the electrode pad 8 and the edge of the light emitting cell is greatly reduced. This greatly hinders the uniformity of light emission of the light emitting diodes, which is a major obstacle to the large area of the light emitting diodes.

In addition, as another type of light emitting diode in the related art, n-type electrode pads and p-type electrode pads are formed in a square or a circle, and these electrode pads are arranged to face diagonally at both corners of the light emitting cell. The light emitting diode of was also bright only around the p-type electrode pad 8, resulting in poor uniformity of light emission.

In addition, conventionally, a wiring layer including an n-type electrode pad, a p-type electrode pad, and a pad connection portion connecting therebetween is formed by a step cover process, and the light emitting cells on the substrate are electrically connected with the wiring layer. At this time, conventionally, a wiring layer including a Cr / Au laminated structure is mainly used, Cr serves as a contact layer, and Au serves as a bonding layer. In the conventional wiring layer of Cr (contact layer) / Au (bonding layer) structure, the light loss by light absorption by Au is large.

One problem to be solved by the present invention is to provide a light emitting diode having improved luminous efficiency and light output by improving the reflectivity of the wiring layer including the p-type pad portion and the n-type pad portion without deteriorating electrical characteristics.

Therefore, one problem to be solved by the present invention, in the light emitting diode including a plurality of light emitting cells on the substrate, through the improvement of the structure and arrangement of the p-type pad portion and the n-type pad portion formed on the light emitting cell, the current It is to provide a light emitting diode of an improved structure that is well dispersed and the current distribution is more uniform.

According to an aspect of the present invention, a light emitting diode includes: a substrate; A plurality of light emitting cells formed on the substrate and each comprising a p-type region and an n-type region; And a wiring layer formed to connect the p-type region and the n-type region of neighboring light emitting cells, wherein the wiring layer includes a stacked structure of a contact layer / reflection layer / barrier layer / bonding layer, wherein the contact layer is formed of Ni. , Cr or Ti, the reflective layer is formed of Al, the bonding layer is formed of Au.

According to one embodiment, further comprising an adhesion reinforcement layer formed on the bonding layer, the adhesion reinforcement layer comprises Ti.

According to one embodiment, the contact layer is preferably a Ni layer having a thickness of 5 ~ 50 kPa.

According to one embodiment, the reflective layer is an Al layer having a thickness of 1000 ~ 3000Å, the bonding layer is preferably a Au layer of 0.5um thickness or more.

According to one embodiment, the barrier layer preferably comprises a structure of Ni / Ti multilayers, Ni / Pt monolayers, or multiple layers of Ni / Pt repeating.

The wiring layer may include a p-type pad portion formed in the p-type region, an n-type pad portion formed in the n-type region, the p-type pad portion and the n-type pad portion of a neighboring light emitting cell. It includes a pad connection for connecting.

According to an exemplary embodiment, the p-type pad part has an isosceles triangle with straight lines connecting the center and both ends thereof, and the n-type pad part has a length smaller than the base side with the straight line connecting both ends parallel to the base of the isosceles triangle. The vertex angle of the isosceles triangle is set to 90 degrees or more.

According to the present invention, the luminous efficiency and the light output of the light emitting diode can be improved by improving the reflectivity of the p-type pad portion and the n-type pad portion without deteriorating electrical characteristics. In addition, the present invention, in the light emitting diode including a plurality of light emitting cells on the substrate, it is possible to increase the current dispersion effect through the optimum structure and arrangement of the p-type pad portion and the n-type pad portion which is part of the wiring layer electrically connecting the light emitting cells. have. Such an optimum structure and an optimal arrangement include making the distance between the p-type pad portion and the n-type pad portion as close as possible and making the distance as uniform as possible within a predetermined area of the light emitting cell. In addition, a close area between the p-type pad portion and the n-type pad portion, while minimizing the area where the p-type pad portion and the n-type pad portion do not face, minimizes the dark area of the entire area of the light emitting cell. Can be.

1 is a plan view for explaining a conventional light emitting diode.
2 is a plan view showing another light emitting diode according to an embodiment of the present invention.
FIG. 3 is an enlarged plan view of a portion of the light emitting diode shown in FIG. 2, and illustrates a plan view for explaining neighboring light emitting cells and a wiring layer pattern therebetween;
FIG. 4 is an enlarged plan view of a portion of the light emitting diode shown in FIG. 2, illustrating a first light emitting block and a light emitting cell adjacent thereto, and a wiring layer pattern between the first light emitting block and the light emitting cell;
FIG. 5 is an enlarged plan view of a portion of the light emitting diode shown in FIG. 2, illustrating a second light emitting block and a light emitting cell adjacent thereto, and a wiring layer pattern between the second light emitting block and the light emitting cell;
6 is a cross-sectional view illustrating a cross-sectional structure of a light emitting diode according to an embodiment of the present invention.
7A and 7B are cross-sectional views illustrating the cross-sectional structure of the wiring layer in the n-type region and the p-type region, in which circle “D” of FIG. 6 and circle “E” of FIG. 6 are enlarged. Sections.
8A and 8B are photographs showing light emission uniformity test results of a light emitting diode according to an embodiment of the present invention and a conventional light emitting diode (comparative example).
9A and 9B are photographs showing a comparison of an example using Ni and an example of Cr in the laminated structure of the wiring layer illustrated in FIG. 7.
10A and 10B are graphs comparing n-omic characteristics before heat treatment and n-omic characteristics after heat treatment when Cr is used as the contact layer in the laminated structure of the wiring layer described in FIG. 7.
FIG. 11 is a graph showing a comparison of n-omic characteristics before and after heat treatment when Ni is used in the laminated structure of the wiring layer illustrated in FIG. 7.
12 is a graph illustrating a comparison of changes in forward voltage (VF) of light emitting diodes before and after heat treatment.
13 is a graph showing a change in ohmic characteristics before and after heat treatment according to the type of barrier layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention can be fully conveyed to those skilled in the art. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience.

2 is a plan view illustrating a light emitting diode according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the light emitting diode includes a substrate 20 and a plurality of light emitting cells 40. An n-type pad part 60 and a p-type pad part 80 are formed on each of the light emitting cells 40. The plurality of light emitting cells 40 are formed on a single substrate 20, and the n-type pad part 60, the p-type pad part 80, and the neighboring light emitting cells 40 and 40 are formed on a single substrate 20. ) Is connected in series by the pad connection unit 52 connecting the n-type pad unit 60 and the p-type pad unit 80 to form a series array of light emitting cells.

In the present embodiment, the n-type pad portion 60, the p-type pad portion 80 and the pad connection portion 52 are included in one wiring layer (ie, step cover layer) formed by a step cover process. As parts, which are formed integrally and simultaneously.

In addition, the light emitting diode according to the present exemplary embodiment includes a p-type first electrode pad 80 ′ and an n-type second electrode pad 60 ″ so as to receive power from the outside. 80 'and the second electrode pad 60' are formed on the first light emitting block 40 'and the second light emitting block 40', respectively.

The substrate 20 is provided except that the first and second light emitting blocks 40 ′ and 40 ″ include a first electrode pad 80 ′ and a second electrode pad 60 ″ as input / output terminals. Although substantially the same as the light emitting cells formed on, in this specification, the term "light emitting block" is defined to distinguish from the other light emitting cells 40.

The first light emitting block 40 'includes terminal n-type pad portions 60' and 60 'together with the p-type first electrode pad 80', and the second light emitting block 40 ' A terminal p-type pad portion 80 ″ is included along with the n-type second electrode pad 60 ″.

As mentioned above, the pad connection portion 52 connects the n-type pad portion 60 and the p-type pad portion 80 of the neighboring light emitting cells 40 and 40. Further, at one end of the array, there is a first terminal pad between the terminal n-type pad portions 60 'and 60' of the first light emitting block 40 'and the p-type pad portion 80 of the light emitting cell 40 adjacent thereto. It is connected by the connection parts 52 'and 52'.

Also, at the other end of the array, there is a second end pad connection portion 52 ″ between the p-type pad portion 80 ″ of the second light emitting block 40 ″ and the n-type pad portion 60 of the light emitting cell 40 adjacent thereto. Are connected by

In the present embodiment, the first and second electrode pads 80 'and 60', the terminal n-type pad portion 60 'and the terminal p-type pad portion 80 ", and the first and second terminal pads. The connections 52 ', 52 "may also be formed integrally and simultaneously with the wiring layer as described above. That is, the end and middle n-type pad portions 60 ', 60, the end and middle p-type pad portions 80', 80, and the end and middle pad connection portions 52 ', 52', 52 are All belong to one interconnection layer formed at the same time, except that they are termed as described above according to their respective positions and functions.

Although not shown, the light emitting cells 40 may be configured in two or more arrays on a single substrate, and the arrays may be connected in anti-parallel to be driven under an AC power source.

According to the present embodiment, the pad connection portions 52, 52 ', 52' serving as wirings are integrally and simultaneously with the n-type pad portions 60, 60 'and the p-type pad portions 80, 80'. Although formed, the n-type pad portion and the p-type pad portion may be formed first, and the n-type pad portion and the p-type pad portion adjacent to each other may be considered to be connected later by a layered or wire-shaped pad connection portion.

As the substrate 20, an insulating substrate capable of electrically insulating the light emitting cells 40 is used. A sapphire substrate is preferred as a growth substrate for growing the nitride semiconductor layers constituting the light emitting cells 40. The light emitting cells 40 may be formed to have the same area, but may have different areas. Each of the light emitting cells 40 may sequentially include an n-type semiconductor layer, an active layer, and a p-type semiconductor layer from the substrate 20, and a transparent electrode layer such as an ITO layer may be formed on the p-type semiconductor layer. .

3 shows an enlarged view of two neighboring light emitting cells 40 and 40.

Referring to FIG. 3, each of the light emitting cells 40 includes a substantially rectangular edge having first and second side edges S1 and S2 and first and second longitudinal sides S3 and S4. The first and second transverse sides S1 and S2 have a length longer than the first and second longitudinal sides S3 and S4. In addition, the light emitting cells 40 share most of their edges, that is, the first and second longitudinal edges S3 and S4, the second horizontal edge S2, and the left and right edges of the first horizontal edge S1 as edges. The upper portion includes an n-type region 40p and an n-type region 40n defined between the edge of the light emitting cell 40, that is, the first horizontal side S1 and the p-type region 40p.

The n-type region 40n is formed by partially etching an active layer, a p-type semiconductor layer, and an additional n-type semiconductor layer in a stacked structure of a light emitting cell including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. The n-type semiconductor layer is removed and is exposed in a relatively recessed form. In addition, a transparent electrode layer such as an ITO layer may be formed on the p-type semiconductor layer. In this case, an upper surface of the transparent electrode layer directly contacts the p-type pad part 80 in the p-type region 40n.

 In the present exemplary embodiment, the n-type region 40n exists in the central partial length region of the first lateral side S1, and a linear n-type pad portion 60 is formed in the n-type region 40n. It is formed in parallel with the horizontal side S1. In the present embodiment, for the purpose of preventing the area of the p-type region 40p from being reduced, the n-type region 40n is formed only in a central portion of the first horizontal side S10, but the first horizontal side is formed. An n-type region 40n may be formed over almost the length of S10. Also in this case, the n-type pad part 60 may be formed in a straight line in parallel with the first side edge S1 at a position adjacent to the first side edge S1.

On the p-type region 40p, a p-type pad portion 80 formed in a substantially linear shape is provided at a position adjacent to the second lateral side S2. The p-type pad part 80 is symmetrical with respect to a vertical center line passing through its center portion c and the center of the n-type pad part 60.

The lateral length of the p-type pad part 80 is greater than the lateral length of the n-type pad part 60, and the central portion c is oriented toward the second lateral side S2. An isosceles triangle with a vertex angle of 90 degrees or more is formed when the central portion c of the P-type pad part 80 and both ends of the P-type pad part 80 are connected in a straight line. Arrangement and structure of the pad portions 60 and 80 are such that the n-type pad portion 60 and the p-type pad portion 80 face each other despite the lateral length of the relatively small n-type pad portion 60. The area is widened, and the distance from each end of each of the n-type pad portions 60 to each end of the p-type pad portions 80 is reduced.

However, when the p-type pad portion 80 is formed with the same trajectory as the isosceles triangle described above, the p-type pad portion (ie, the region between the p-type pad portion 80 and the rear edge thereof, that is, in the same light emitting cell) The area of the region where 80 does not face the n-type pad portion 60 will be increased.

The area of such an area is defined by the p-type pad portion 80 having a bow or straight main pad portion 82 and a first transverse side where the n-type pad portion 60 is adjacent from both ends of the main pad portion 82. It can be reduced by forming the structure including a pair of linear outer pad extension part 84 extended toward S1). End portions of each of the pair of outer pad extensions 84 become both ends of the p-type pad portion 80. In this case, since the main pad portion 82 and the outer pad extension portion 84 are oriented backwards from both sides of the isosceles triangle toward the second transverse side S1, the P-type pad portion ( 80 is a structure or pattern as described above, which is an isosceles triangle in a straight line between both ends thereof and its center portion c without reducing the area of the region not facing the n-type pad portion 60. I can keep it.

Further, the main pad portion 82 is more preferably formed in a bow shape that intersects a straight line or a curve upward with respect to the center portion c. Further, each of the pair of outer pad extensions 84 preferably extends vertically from the main pad portion 82, ie, parallel to the first and second longitudinal sides S3, S4.

In addition, the p-type pad portion 80 is the center of the main pad portion 82, that is, the center pad extension portion 83 extending in the vertical direction from the central portion (c) toward the n-type pad portion 60 More). The pad portions in the vicinity of the center portion c and the vicinity thereof are not too far from the n-type pad portion 60. In this case, the minimum distance from each of the outer pad extension portions 84 to the n-type pad portion 60 is greater than or equal to the minimum distance from the center pad extension 83 to the n-type pad portion 60. It is preferable.

The n-type pad part 60 and the p-type pad part 80 based on an imaginary vertical straight line passing through the center of the n-type pad part 60 and the central portion c of the p-type pad part 80. It is good for everyone to have a symmetrical structure. In the present embodiment, the linear n-type pad portion 60 is parallel to the base of the isosceles triangle formed when the central portion c and both ends of the p-type pad portion 80 are connected by straight lines. At this time, the straight length of the n-type pad portion 60, as described above, is shorter than the base of the isosceles triangle. At this time, even when the n-type pad portion 60 does not have a perfect straight line shape, the straight line connecting both ends of the n-type pad portion 60 is parallel to the base of the isosceles triangle and has a length shorter than that of the base. good. In addition, the bottom side is parallel to the first side S1 and the second side S2 constituting the long side of the edge of the light emitting cell.

Meanwhile, the pad connection portion 52 passes through a gap between two neighboring light emitting cells 40 and 40, and the n-type pad part 60 and the p-type pad part 80 of two neighboring light emitting cells 40 and 40. ). As mentioned above, the pad connection portion 52, the n-type pad portion 60, and the p-type pad portion 80 are preferably included in a single step cover layer or wiring layer formed by a step cover process. Do. As shown in FIG. 3, the pad connection part 52 is preferably formed to connect the center of the p-type pad part 80 to the center of the n-type pad part 60. However, in a position where it is difficult due to the arrangement of the light emitting cells 40, it is preferable that one end of the pad connection portion 52 is connected to a bending point or an intersection point of the pad portion, particularly, the p-type pad portion 80. (FIG. 2). Reference)

Referring to FIG. 4, an enlarged view of the first light emitting block 40 ′ and one neighboring light emitting cell 40 is provided.

Referring to FIG. 4, the first light emitting block 40 ′ is positioned at one corner of the edge of the substrate and is positioned substantially parallel to the neighboring light emitting cells 40. In the present embodiment, since the first light emitting block 40 'and the light emitting cell 40 are formed together by the same processes, the first light emitting block 40' is the ones of the light emitting cell 40. The same semiconductor layers as in the same structure.

The first light emitting block 40 'may include first and second side edges S1 and S2 of each of the light emitting cells 40 and side edges facing each other corresponding to the first and second longitudinal sides S3 and S4. It includes an approximately rectangular border with longitudinal sides facing each other.

Like the light emitting cell 40, the first light emitting block 40 ′ has a length longer than each of the longitudinal sides. In addition, the first light emitting block 40 'is a rectangular P-type region 40p', and an n-type region defined between a portion of the edge of the first light emitting block 40 'and the P-type region 40p'. 40n ') at the top. The n-type region 40n ′ includes a region formed along each of two longitudinal sides of the first light emitting block 40 ′ and both edge regions of a horizontal side adjacent to the light emitting cell.

The n-type region 40n 'of the first light emitting block 40' is partially etched by an active layer and a p-type semiconductor layer in a stacked structure of a light emitting cell including an n-type semiconductor layer, an active layer and a p-type semiconductor layer. Removed, thereby exposing the n-type semiconductor layer in a relatively recessed form. In addition, a transparent electrode layer, such as an ITO layer, may be formed on the p-type semiconductor layer. In this case, the upper surface of the transparent electrode layer is directly in contact with the p-type first electrode pad 80 ′ in the p-type region 40p '. I touch it.

The p-type first electrode pad 80 'is electrically connected to an external power source by, for example, a bonding wire to serve as a terminal of the light emitting diode, and is circular in the center of the p-type region 40p'. It is formed into a cross section. In the n-type region 40n 'of the first light emitting block 40', a pair of terminal n-type pad portions 60 'and 60' are formed in a symmetrical manner.

Each of the pair of terminal n-type pad portions 60 'and 60' is separated from a predetermined length region at the center of the upper side of the upper side of the first light emitting block 40 'close to the light emitting cell 40 The left and right sides of the first light emitting block 40 'are symmetrically formed along the left and right and left and right longitudinal sides of the first light emitting block 40'. The two terminal n-type pad portions 60 'and 60' are divided into two single p-type pad portions 80 of the adjacent light emitting cells 40 by two symmetrical terminal pad portions 52 'and 52'. Is connected to the end pad connecting portion 52 ', 52' in the p-type pad portion 80. The two end pad connections 52 ', 52' are preferably bilaterally symmetrical and parallel to each other.

The connection structure between the first light emitting block 40 ′ and the light emitting cell 40 adjacent thereto, that is, the structure in which the two n-type pad portions and the pad connection portions merge in the p-type pad portion is a current. It makes for better dispersion.

Meanwhile, the p-type region of the first light emitting block 40 'may be a predetermined length region in the center of the upper horizontal side where the two n-type pad portions 60' and 60 'of the first light emitting block 40' are separated. 40p 'is further extended in the region, which is caused by the position of the first electrode pad 80' having a relatively large area on the p-type region 40p '. This function compensates for the reduction of the light emitting area at.

Referring to FIG. 5, an enlarged view of the second light emitting block 40 ″ and a neighboring light emitting cell 40 is shown.

Referring to FIG. 5, the second light emitting block 40 ″ is positioned at the other corner of the edge of the substrate and is positioned substantially parallel to the neighboring light emitting cells 40. The second light emitting block 40 ″ may be positioned diagonally to the first light emitting block 40 ′ described above. In the present embodiment, since the second light emitting block 40 ″ and the light emitting cell 40 are formed together by the same processes, the second light emitting block 40 ″ is the ones of the light emitting cell 40. The same semiconductor layers as in the same structure.

The second light emitting block 40 ″ may include first and second side edges S1 and S2 of each of the light emitting cells 40 and side edges facing each other corresponding to the first and second longitudinal sides S3 and S4. It includes an approximately rectangular border with longitudinal sides facing each other.

Like the light emitting cell 40, the second light emitting block 40 ″ has a length longer than each of the longitudinal sides. In addition, the second light emitting block 40 ″ includes a P-type region 40p ″ which shares most of the edges of the edge, and an n-type region defined between the edge of the light emitting block and the P-type region 40p ″. 40n ”). In this case, the n-type region 40n ″ includes a region concavely extending from the center of the upper transverse side to the p-type region of the edge of the second light emitting block 40 ″, which has n having a relatively large cross-sectional area. Type second electrode pad 60 'is formed.

The n-type region 40n ″ of the second light emitting block 40 ″ partially has an active layer and a p-type semiconductor layer along an edge in a stacked structure of a light emitting cell including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer. It is removed by etching to expose the n-type semiconductor layer in a relatively recessed form. In addition, a transparent electrode layer such as an ITO layer may be formed on the p-type semiconductor layer. In this case, the terminal p-type pad portion 80 ″ may be directly formed on the upper surface of the transparent electrode layer of the p-type region 40p ″. .

The n-type second electrode pad 60 ″ is electrically connected to an external power source by, for example, a bonding wire to serve as a terminal of the light emitting diode. The terminal p-type pad portion 80 ″ formed in the p-type region 40 p ″ of the second light emitting block 40 ″ is a virtual vertical straight line passing through the center of the n-type second electrode pad 60 ″. It is formed as a concave cup cross-section symmetrical with respect to. Due to the shape of the cup cross section, the terminal p-shaped pad portion 80 ″ is adjacent to the main pad portion 82 ″ and the second electrode pad 60 ″ from both ends of the main pad portion 82 ″. And a pair of straight outer pad extensions 84 ", 84" extending toward the transverse side. In addition, the terminal p-type pad portion 80 ″ has a central portion c ″ at the main pad portion 82, which is oriented vertically toward the neighboring light emitting cell 40. do.

The linear n-type pad portion 60 of the light emitting cell 40 and the p-type pad portion 80 ″ of the second light emitting block 40 ″ are formed of the n-type pad portion 60 on the light emitting cell 40. The center and the central portion c ″ of the terminal p-type pad portion 80 ″ on the second light emitting block 40 ″ are electrically connected by the terminal pad connecting portion 52 ″.

In addition, the second p-type pad portion 80 ″ of the second light emitting block 40 ″ has a cup cross-sectional shape surrounding the front and both sides of the second electrode pad 60 ″, so that the second light emitting block 40 ′ may be formed. Current dispersion within (40 ”) can be better.

6 is a cross-sectional view illustrating a cross-sectional structure of a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 6, the light emitting diode includes a single substrate 20, and a plurality of light emitting cells 40 as described above are formed on the single substrate 20. Each of the light emitting cells 40 includes an n-type semiconductor layer 42, a p-type semiconductor layer 44 positioned on one region of the n-type semiconductor layer 42, and the n-type semiconductor layer 42 and the p. It includes an active layer 43 interposed between the type semiconductor layer 44. In addition, the light emitting diode includes a transparent electrode layer 46 in each light emitting cell 40. In addition, the light emitting diode includes an insulating layer 99 and a wiring layer 100. In the present embodiment, the wiring layer 100 is formed by a step cover process, and includes the n-type pad part 60, the p-type pad part 80, and the pad connection part 52 integrally shown in FIG. 2. do. In addition, the light emitting diode may include a buffer layer 41 under the light emitting cell 40.

Referring back to FIG. 6, the n-type semiconductor layer 42, the active layer 43, and the p-type semiconductor layer 44 are gallium nitride based semiconductor materials, that is, (B, Al, In, Ga) N, respectively. It can be formed as. The active layer 43 has a composition element and a composition ratio determined so as to emit light of a desired wavelength such as ultraviolet light or blue light, and the n-type semiconductor layer 42 and the p-type semiconductor layer 44 are provided on the active layer 43. In comparison, the band gap is formed of a material. As illustrated, the n-type semiconductor layer 42 and / or the p-type semiconductor layer 44 may be formed in a single layer, but may also be formed in a multilayer structure. In addition, the active layer 43 may have a single quantum well or multiple quantum well structures.

The n-type semiconductor layer 42 has stepped portions formed on sidewalls. The stepped portion forms an n-type region 40n '(see FIG. 4) as described above. Here, the light emitting cell portion formed above the stepped portion is defined as mesa based on the stepped portion formed in the n-type semiconductor layer 42. The mesa sidewall may be inclined so that the width of the mesa becomes narrower as it goes up. The inclination angle of the mesa sidewall with respect to the upper surface of the substrate 20 may be in the range of 15 degrees to 80 degrees. Meanwhile, the n-type semiconductor layer 42 positioned below the mesa may also have a sidewall inclined upward from the substrate 20. An inclination angle of the sidewall of the n-type semiconductor layer 42 with respect to the upper surface of the substrate 20 may be in a range of 15 degrees to 80 degrees.

By the above-mentioned inclined structure, it helps the continuous deposition of other layers to be formed on the light emitting cells 40, for example, the insulating layer 99 and the wiring layer 100. Also, although not shown, a secondary insulating layer may be formed that entirely covers the elements.

The inclination angle of the mesa sidewall may be the same as the inclination angle of the lower side of the lower semiconductor layer 42, but is not limited thereto. These inclination angles may be adjusted differently. For example, the inclination angle of the mesa sidewall may be smaller than the inclination angle of the sidewall of the n-type semiconductor layer 42. Accordingly, light generated in the active layer 43 can be easily emitted through the mesa sidewalls, thereby improving light extraction efficiency and securing a light emitting cell region relatively wide.

On the other hand, the above-described buffer layer 41 is adopted to mitigate lattice mismatch between the substrate 20 and the n-type semiconductor layer 42 to be formed thereon, when the substrate 20 is a growth substrate, especially a sapphire substrate.

The transparent electrode layer 46 may be located on an upper surface of the upper semiconductor layer 44 and may have an area smaller than that of the upper semiconductor layer 44. That is, the transparent electrode layer 46 may be recessed from the edge of the upper semiconductor layer 44. Therefore, it is possible to prevent the current from being concentrated through the sidewall of the light emitting cell 40 at the edge of the transparent electrode layer 46.

On the other hand, the insulating layer 99 covers the light emitting cells 40 almost entirely. The insulating layer 99 has openings on the n-type semiconductor layers 42 and also has openings on the p-type semiconductor layers 44 or the transparent electrode layer 46. Meanwhile, sidewalls of the light emitting cells 40 are covered by the insulating layer 99. The insulating layer 99 may also cover the substrate 20 in the regions between the light emitting cells 40. The insulating layer 99 may be formed of a silicon oxide film (SiO 2 ) or a silicon nitride film.

The wiring layer 100 is formed on the insulating layer 67. The wiring layer 100 may be formed in a predetermined pattern in the n-type region on the n-type semiconductor layer 42 and the p-type region on the p-type semiconductor layer 44 or the transparent electrode layer 46 through the openings. In this case, the wiring layer 100 includes at least an n-type pad 60, a p-type pad 80, and a pad connector 52 as shown in FIG. 2.

The wiring layer 100 may be electrically connected to the p-type semiconductor layer 44 under the transparent electrode layer 46. Meanwhile, the wiring layer 100 electrically connects the n-type semiconductor layer 42 and the p-type semiconductor layer 44 of adjacent light emitting cells 40 and 40 to form a series array of light emitting cells 40. A plurality of such arrays may be formed, and a plurality of arrays may be connected in antiparallel to each other and connected to an AC power source to be driven. In addition, a bridge rectifier (not shown) connected to a series array of light emitting cells may be formed, and the light emitting cells may be driven under AC power by the bridge rectifier. The bridge rectifier may be formed by connecting light emitting cells having the same structure as the light emitting cells 40 using a wiring layer or wirings. The wiring layer or wirings may be formed of a conductive material, such as a doped semiconductor material or metal, such as polycrystalline silicon.

In addition, a secondary insulating layer 130 as a protective insulating layer 130 is further formed to cover and protect the upper and side surfaces of the light emitting cells in which the wiring layer 100 is formed. The secondary insulating layer 130 may be made of SiO 2.

7A and 7B are cross-sectional views illustrating the cross-sectional structure of the wiring layer in the n-type region and the p-type region, in which circle “D” of FIG. 6 and circle “E” of FIG. 6 are enlarged. Cross-sectional views.

As shown in FIG. 7A, the wiring layer 100 is formed on the n-type semiconductor layer 42 in the n-type region 40n (see FIG. 3). In addition, as shown in FIG. 7B, a transparent electrode layer 46 is formed on the p-type semiconductor layer 43 in the p-type region 40p (see FIG. 3). In this case, the wiring layer 100 may have a structure of a contact layer 101 / reflection layer 103 / barrier layer 106 / bonding layer 109 / adhesion reinforcement layer 111.

The contact layer 101 has a thickness, for example, in the range of 5 to 50 microns, and is used for ohmic contact to the n-type semiconductor layer 42 of the n-type region 40n (see FIG. 3). The contact layer 101 may be formed of Ni, Cr or Ti. When Ni is used as the contact layer 101, a good n-ohmic contact can be achieved at a relatively very thin thickness, for example, about 5 GPa, thereby lowering light loss. On the other hand, the reflective layer 103 reflects the light generated in the active layer 43, the pad portions and electrode pads 60, 60 ', 60 ", 80 provided in the n and p region of the light emitting cell and / or light emitting blocks. 80 ', 80 ”; see FIGS. 2 to 5) light is absorbed and prevented from being lost in the pad portions and the electrode pads. The reflective layer 103 is made of aluminum (Al). The reflective layer 103 may be formed to a thickness of approximately 1000 ~ 3000Å. The barrier layer 106 is used to maintain the reflective function of the reflective layer 103 by preventing intermixing of the bonding layer metal and the reflective layer metal. The barrier layer 106 may be formed of the bilayers 106a and 106, for example, Cr / Pt, Ni / Ti, Ni / Pt, etc., but is not limited thereto. For example, the barrier layer 106 may be a single layer such as Ni. Or it may be formed of multiple layers of two or more layers, such as Ni / Ti / Ni / Ti. The bonding layer 109 is formed of a bonding metal for bonding a bonding wire (not shown), and is formed of Au in this embodiment. The bonding layer 109 may be formed to a thickness of 1 μm or more. In the conventional wiring layer of Cr (contact layer) / Au (bonding layer) structure, the light loss by light absorption by Au is large. However, according to the present embodiment, by applying the Al reflective layer 103 on the contact layer 101, it is possible to greatly reduce the light loss in the region where the wiring layer 100 is present.

The Al reflecting layer in the wiring layer 100, that is, the Al layer 103, may reduce the resistance by the wiring layer 100 while minimizing the cross-sectional area of the Au bonding layer, that is, the Au layer 109, and may be driven at high voltage and high power. Improve the efficiency of the light emitting diodes. The resistance can be lowered by increasing the cross-sectional area of the Au layer 109 in the wiring layer 100. In this case, the area occupied by the wiring layer 100 on the upper surface of the light emitting cell 40, which is the main light emitting surface of the light emitting cell 40. This increases, resulting in a reduction in the light emitting area of the light emitting cell 40, and in addition, a large amount of Au, which is an expensive material, causes a problem of an increase in manufacturing cost of the light emitting diode. According to this embodiment, the cross-sectional area of the wiring layer 100 is increased by the Al layer 103 added in addition to the Au layer 109, whereby the resistance can be reduced. For example, by maintaining the cross-sectional area of the Au layer 109 equal to the cross-sectional area of the wiring layer including the conventional Cr (contact layer) / Au (bonding layer) and increasing the cross-sectional area (or thickness) of the Al layer 103, It can reduce resistance and increase power efficiency. Since Al is less expensive than Au, a structure in which the resistance of the wiring layer 100 is lowered by applying the Al layer 103 instead of increasing the cross-sectional area of the Au layer 109 is economically advantageous.

Al and Au, however, are materials that are likely to chemically intermix by diffusion. Therefore, the light emitting diode according to the present embodiment is interposed between the Al reflecting layer 103 and the Au bonding layer 109 through the barrier layer 106 as described above. The barrier layer 106 is located between the Al reflective layer 103 and the Au bonding layer 109, thereby preventing chemical diffusion between the Al reflective layer 103 and the Au bonding layer 109, whereby the Al reflective layer The 103 functions under the Au bonding layer 109 to reduce the loss due to light absorption and to increase the power efficiency by reducing the resistance of the wiring layer without increasing the cross-sectional area of the Au bonding layer 109.

Ti is used as the adhesion reinforcing layer 111. The Ti adhesion reinforcing layer 111 enhances adhesion with SiO 2 constituting the secondary insulating layer 130 further formed on the wiring layer 100, thereby suppressing peeling of the secondary insulating layer. Can be.

As described above, the wiring layer 100 having the structure of the contact layer / Al reflecting layer / barrier layer / Au bonding layer 109 / adhesion reinforcing layer has a reflectivity of 70 to 80% of the wiring layer composed of conventional Cr / Au / Ti It was confirmed that the reflection was greatly improved compared to 30 to 45%.

[Experimental Example 1]

8A and 8B are photographic diagrams illustrating light emission uniformity test results of a light emitting diode according to an embodiment of the present invention and a conventional light emitting diode (comparative example), and [Table 1] below is an embodiment of the present invention. The electrical characteristics of the comparative example were tested and compared. In both Examples and Comparative Examples, an ITO layer of 1200 Å thickness was used on the upper part of the light emitting cell.

8A and 8B are photographic diagrams illustrating light emission uniformity test results of a light emitting diode according to an embodiment of the present invention and a conventional light emitting diode (comparative example), and [Table 1] below is an embodiment of the present invention. The electrical characteristics of the comparative example were tested and compared. In both Examples and Comparative Examples, an ITO layer of 1200 Å thickness was used on the upper part of the light emitting cell.

 As can be seen from Table 1 below, the light emitting diode according to the present embodiment can be seen that the power (light output) and power efficiency are greatly improved compared to the light emitting diode of the comparative example. There is little difference in forward voltage.

division Forward voltage Power Power efficiency
WPE (%) Avg. [V] Std Avg. [mW] Std Comparative example 56.92 2.70 362.87 19.19 31.88 Example 56.82 0.55 418.5 5.7 36.8

8A shows that the light emitting diode of the present embodiment is uniform in brightness, whereas the light emitting diode of Comparative Example shown in FIG. 8B shows a large difference in brightness between the portions close to and far from the p-type pad portion. have. Note that the relatively dark areas in FIGS. 8A and 8B are actually brighter areas.

8A shows that the light emitting diode of the present embodiment is uniform in brightness, whereas the light emitting diode of Comparative Example shown in FIG. 8B shows a large difference in brightness between the portions close to and far from the p-type pad portion. have. Note that the relatively dark areas in FIGS. 8A and 8B are actually brighter areas.

[Experimental Example 2]

9A and 9B are photographs showing a comparison between an example using Ni and an example of Cr in the laminated structure of the wiring layer illustrated in FIG. 7. From these photographs, it was confirmed that the Ni crystal shown in FIG. 9A was superior to the hard information of Cr shown in FIG. 9B.

[Experimental Example 3]

10A and 10B are graphs comparing n-omic characteristics before heat treatment and n-omic characteristics after heat treatment when Cr is used as the contact layer in the laminated structure of the wiring layer described in FIG. 7, and FIG. 11 is FIG. Fig. 12 is a graph showing the change of n-omic characteristics before and after heat treatment when Ni is used in the laminated structure of the wiring layer described in FIG. 12, and FIG. 12 shows the change in forward voltage (VF) of the light emitting diodes before and after heat treatment. It is a graph.

Referring to FIGS. 10A, 10B, 11, and 12, when Ni is used as the contact layer, substantially no change in n-omic properties is caused by the heat treatment process, whereas n is used before and after heat treatment when Cr is used as the contact layer. -It was confirmed that the change in the ohmic characteristics is large.

[Experimental Example 4]

Table 2 below shows the difference in reflectance and forward voltage of various samples having different materials and layers of the barrier layer in the structure of the wiring layer described in FIG. 7. In this case, Ni was used for all the samples, Al for the reflective layer, Au for the bonding layer, and Ti for the adhesion reinforcing layer.

Sample Reflectivity (%) Forward voltage
(as-dep / SSP) Cr / Pt (reference) 76.6 ↑ 55.3 / 55.8 V  Ni / Pt 77.5 55.3 / 55.5 V Ni 1000Å 78.1 55.4 / 55.6 V Ni / Ti 78.3 55.4 / 56.3 V (Ni / Ti) ^ 2 77.9 55.3 / 55.5 V

FIG. 13 is a graph showing changes in ohmic characteristics before and after heat treatment according to the type of barrier layer. No substantial change in ohmic properties before and after heat treatment was found due to all kinds of barrier layers used in the experiment from FIG. 13.

Claims (7)

Board;
A plurality of light emitting cells formed on the substrate and each comprising a p-type region and an n-type region; And
A wiring layer formed to connect the p-type region and the n-type region of neighboring light emitting cells,
The wiring layer includes a laminated structure of a contact layer / reflective layer / barrier layer / bonding layer,
Wherein the contact layer is formed of Ni, Cr or Ti, the reflective layer is formed of Al, and the bonding layer is formed of Au. The light emitting diode of claim 1, further comprising an adhesion reinforcing layer formed on the bonding layer, wherein the adhesion reinforcing layer comprises Ti. The light emitting diode of claim 1, wherein the contact layer is a Ni layer having a thickness of 5 to 50 GPa. The light emitting diode of claim 3, wherein the reflective layer is an Al layer having a thickness of 1000 to 3000 GPa, and the bonding layer is an Au layer having a thickness of 0.5 μm or more. The light emitting diode of claim 1, wherein the barrier layer comprises a structure of Ni / Ti multilayers, Ni / Pt monolayers, or multiple layers of Ni / Pt repeating. The method according to claim 1, wherein the wiring layer,
A p-type pad portion formed in the p-type region,
An n-type pad portion formed in the n-type region,
And a pad connection portion connecting the p-type pad portion and the n-type pad portion of a neighboring light emitting cell. The method of claim 6,
The p-type pad part is a straight line connecting the center and both ends forms an isosceles triangle,
The n-type pad portion has a length smaller than the base side while the straight line connecting both ends parallel to the base side of the isosceles triangle,
The vertex angle of the isosceles triangle is more than 90 degrees light emitting diodes.
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