KR20130008374A - Manufacturing method of transistor array substrate - Google Patents

Abstract

PURPOSE: A method for manufacturing a transistor array substrate is provided to form an active layer and an etch stopper by using a second mask process. CONSTITUTION: A first mask process, a gate line, a first gate pad layer and a gate electrode are formed by patterning the first metal layer on a substrate in a first mask process. The gate insulating layer is formed on the substrate. An active layer, an etch stopper and a first gate pad hole are formed by patterning a first material layer and a second material layer on the gate insulating layer in the second mask process.

Description

Manufacturing Method of Transistor Array Substrate

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor array substrate applied to a flat panel display of an active matrix driving method, defining a plurality of pixel regions corresponding to a plurality of pixels, and selectively driving the plurality of pixels.

In recent years, as the information age has entered, the display field for visually expressing electrical information signals has been rapidly developed, and various flat panel display devices having excellent performance of thinning, light weight, and low power consumption have been developed. Flat Display Device has been developed to quickly replace the existing Cathode Ray Tube (CRT).

Specific examples of such a flat panel display include a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD, Electric Paper Display), Plasma Display Panel Device (PDP), Field Emission Display Device (FED), Electroluminescence Display Device (ELD) and Electro-Wetting Display (EWD) Etc. can be mentioned. These are commonly required components of a flat panel display panel that implements an image. The flat panel includes a pair of substrates bonded to each other with a layer of a light emitting material or a polarizer interposed therebetween.

Meanwhile, the driving method of the flat panel display panel may be classified into a passive matrix driving mode and an active matrix driving mode.

In the passive matrix driving method, a plurality of pixels are formed at an intersection area of a gate line and a data line, and each pixel is driven by applying signals to gate lines and data lines that cross each other. While the passive matrix driving method has the advantage of being simple to control, signals applied to the gate line and the data line, respectively, affect several pixels corresponding to them, so that it is difficult to drive each pixel independently. There is a disadvantage of having a low sharpness and a long response speed, and thus has a disadvantage of difficult to realize high resolution.

The active matrix driving method is a method of selectively driving a plurality of pixels by using a transistor array including a plurality of switching elements respectively corresponding to the plurality of pixels. While the active matrix driving method has a disadvantage of complicated control, each pixel can be driven independently through a plurality of transistors that can be selectively turned on and off, thereby providing higher clarity and shorter response than the passive matrix driving method. There is an advantage in that speed can be realized, and thus an advantage in high resolution.

In general, a transistor array includes gate lines and data lines intersecting to define a plurality of pixel regions corresponding to a plurality of pixels, and gate pads formed at ends of the gate lines and ends of the data lines. The data pad may include a plurality of thin film transistors disposed in an intersecting region of the gate line and the data line, and a plurality of pixel electrodes respectively formed in the plurality of pixel regions.

The thin film transistor overlaps the gate electrode with the gate electrode connected to the gate line, the source electrode connected with the data line, the drain electrode connected with the pixel electrode corresponding to each pixel, and the gate insulating layer interposed therebetween. And an active layer forming a channel between the source electrode and the drain electrode according to the voltage level. When the thin film transistor is turned on in response to the signal of the gate line, the thin film transistor applies a signal of the data line to the pixel electrode.

The thin film transistor is covered by a protective film thereon, and a plurality of pixel electrodes are formed on the protective film.

The transistor array substrate further includes a first contact hole penetrating the passivation layer and the gate insulating layer corresponding to at least a portion of the gate pad, and a second contact hole penetrating the passivation layer corresponding to at least a portion of the data pad, thereby forming the gate pad and the data pad. Is connected to the external load, and further includes a third contact hole penetrating through the passivation layer corresponding to at least part of the drain electrode of the thin film transistor, thereby connecting the plurality of thin film transistors and the plurality of pixel electrodes.

In this case, according to the related art, in order to prevent an increase in the mask process, the first contact hole penetrating both the passivation layer and the gate insulating layer, and the second contact hole and the third contact hole penetrating only the passivation layer are simultaneously used as one mask process. Form.

At this time, in the process of forming the first to third contact holes, in order to form the first contact hole, the etching process must be performed for a long process time that can be patterned to the gate insulating film. Therefore, as a part of each of the data pad and the thin film transistor exposes the second and third contact holes to the etching process, the surface of the data pad and the thin film transistor may be damaged and the pixel electrodes stacked on the upper part may be disconnected.

Meanwhile, when the thin film transistor has a bottom gate structure including an active layer formed on the gate insulating layer covering the gate electrode, the thin film transistor may further include an etch stopper formed on a portion of the active layer including the channel region. have. At this time, the etch stopper is to protect the pre-formed active layer during the process of forming the source electrode and the drain electrode on the active layer.

However, according to the related art, since the mask process for forming the etch stopper must be further included, there is a problem in that the manufacturing method is limited.

The present invention is to provide a method of manufacturing a transistor array substrate that can manufacture a transistor array substrate including an etch stopper, while reducing the mask process than in the prior art, which can simplify the process.

In order to solve the above problems, the present invention is to pattern the first metal film on the substrate in the first mask process, so that the gate line, the first gate pad layer at the end of the gate line, and the gate electrode branched from the gate line. Forming; Forming a gate insulating film on the entire surface of the substrate to cover the gate line, the first gate pad layer, and the gate electrode; In a second mask process, the gate insulating layer, a first material layer on the gate insulating layer, and a second material layer are selectively patterned to partially overlap the gate electrode with at least a portion of the active layer, including a channel region of the active layer. Forming a etch stopper and a first gate pad hole penetrating through the gate insulating layer corresponding to a portion on the first gate pad layer; In a third mask process, the second metal layer on the gate insulating layer is patterned to separate the data line, the source electrode branched from the data line to be in contact with one side on the active layer, and spaced apart from the source electrode with the channel region interposed therebetween. Forming a drain electrode in contact with the other side of the active layer, a second gate pad layer in contact with the first gate pad layer through the first gate pad hole, and a first data pad layer at the end of the data line; Forming a passivation layer on the gate insulating layer, the passivation layer covering the data line, the source electrode, the drain electrode, the second gate pad layer, and the first data pad layer; In the fourth mask process, a second gate pad hole penetrating the passivation layer corresponding to a portion on the second gate pad layer, a data pad hole penetrating the passivation layer corresponding to a portion on the first data pad layer, and the Forming a pixel electrode hole penetrating the passivation layer corresponding to a portion of the drain electrode; And a third gate pad layer contacting the second gate pad layer through the second gate pad hole by patterning a third metal layer on the passivation layer in the fifth mask process, and the first data through the data pad hole. A method of manufacturing a transistor array substrate includes forming a second data pad layer in contact with a pad layer, and a pixel electrode connected to the drain electrode through the pixel electrode hole.

As described above, the method of manufacturing the transistor array substrate according to the present invention includes forming the active layer and the etch stopper by using the second mask process, and thus, unlike the conventional method, includes a single mask process corresponding to the formation of the etch stopper. Since there is no need to do so, the process can be simplified.

According to the present invention, the first gate pad hole penetrating the gate insulating film is formed in the second mask process, and then the second gate pad hole penetrating the protective film is formed in the fourth mask process. That is, the gate pad hole having the structure including the first and second gate pad holes is formed through two etching processes.

Accordingly, unlike the related art, in order to form the gate pad hole, an etching process is performed for a long time that can be patterned to the gate insulating film, so that a part of the surface of the first data pad layer and the drain electrode formed on the gate insulating film is formed. The data pad hole and the pixel electrode hole can be prevented from being damaged by being exposed to the etching process.

In addition, since the formation of the first gate pad hole is performed together in the second mask process for forming the active layer and the etch stopper, it is not necessary to add a separate mask process, thereby preventing the complexity of the process and the increase of the process time. have.

1 is a plan view illustrating a transistor array substrate according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating A-A ', BB', and C-C 'of FIG. 3.
3 is a flowchart illustrating a method of manufacturing a transistor array substrate according to an embodiment of the present invention.
FIG. 4 is a flow chart showing "step of forming an active layer, an etch stopper and a first gate pad hole" shown in FIG.
5A to 5C, 6, 7A to 7H, 8A to 8D, and 9 to 11 illustrate a method of manufacturing the transistor array substrate illustrated in FIGS. 3 and 4, each step A-. Process sectional drawing which shows A ', BB', and C-C '.

Hereinafter, a method of manufacturing a transistor array substrate according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a transistor array substrate according to an embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a plan view illustrating a transistor array substrate according to an exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating A-A ', B-B', and C-C 'of FIG. 3. 1 is a diagram showing only one pixel among a plurality of pixels defined by a transistor array substrate for convenience.

As shown in FIG. 1, a transistor array substrate according to an exemplary embodiment of the present invention may include a gate line GL and a gate line GL in a first direction (shown as “horizontal direction” in FIG. 1). A gate pad GP formed at an end, a common line CL in a first direction parallel to the gate line GL, spaced apart from the gate line GL, and a second direction crossing the gate line GL. Data line (DL) of the data line (shown in FIG. 1 in the “vertical direction”), the data pad DP formed at the end of the data line DL, and the gate line GL and the data line DL. And a thin film transistor (TFT) disposed in the intersecting area. In this case, the gate line GL and the data line DL are intersected with each other to define a plurality of pixel regions corresponding to the plurality of pixels. The gate pad GP includes a gate pad hole H_GP, and the data pad DP includes a data pad hole H_DP. The gate pad GP and the data pad DP are connected to the outside. It is used as a terminal.

The transistor array substrate further includes a common electrode CE connected to the common line CL through the common electrode hole H_CE, and a pixel electrode PE connected to the thin film transistor TFT through the pixel electrode hole H_PE. Include. In this case, the pixel electrode PE and the common electrode CE are arranged in branch forms alternate with each other in each pixel area.

In order to maintain a voltage difference between the pixel electrode PE and the common electrode CE for a predetermined time, the transistor array substrate includes a storage capacitor Cst connected in parallel between the pixel electrode PE and the common electrode CE. It includes more. The storage capacitor Cst is generated in an area where the storage lower electrode formed as part of the common line CL and the storage upper electrode extended from the pixel electrode PE overlap each other. The transistor array substrate further includes a storage additional electrode extending from the drain electrode of the thin film transistor TFT to at least partially overlap the storage lower electrode and the storage upper electrode in order to further increase the capacity of the storage capacitor in the limited region. do.

As shown in A-A 'of FIG. 2, the thin film transistor TFT is formed on the substrate 110 by branching from a gate line (corresponding to “GL” in FIG. 1) on the substrate 110 and the substrate 110. The gate insulating layer 130 formed on the entire surface of the top surface and covering the gate electrode 121, and the active layer 141 and the active layer 141 overlapping at least a portion of the gate electrode 121 on the gate insulating layer 130. An etching stopper 151 formed on a portion including the channel region of the middle region is branched from the data line (corresponding to “DL” in FIG. 1) on the gate insulating layer 130 to be in contact with one side of the active layer 141. And a drain electrode 162 spaced apart from the source electrode 161 with the channel region interposed therebetween so as to be in contact with the other side of the active layer 141. The thin film transistor TFT is covered by the passivation layer 200 formed on the entire surface of the gate insulating layer 130.

The active layer 141 is selected as an oxide semiconductor of AxByCzO (x, y, z? 0), which is known to have higher charge mobility and stable electrostatic properties than silicon semiconductor. In this case, each of A, B, and C is selected from Zn, Cd, Ga, In, Sn, Hf, and Zr. In particular, the active layer 141 may be selected from ZnO, InGaZnO ₄ , ZnInO, ZnSnO, InZnHfO, SnInO, and SnO, but the present invention is not limited thereto.

The gate insulating layer 130 may be formed of a single layer including any one of a nitride-based insulating material and an oxide-based insulating material, or a plurality of layers in which two or more different layers are stacked.

Representative examples of the nitride-based insulating material may be silicon nitride (SiNx). Silicon nitride (SiNx) has a relatively high dielectric constant, and has the advantage of ensuring an appropriate level of capacitance even at a relatively thin thickness, while maintaining a constant composition ratio of nitrogen (N) and silicon (Si) during lamination. There is a disadvantage in that each region has a different dielectric constant.

When the gate insulating film 130 includes a single layer of silicon nitride (SiNx) or a second gate insulating film 132 of silicon nitride (SiNx), the nitrogen and silicon (Si) forming the silicon nitride (SiNx) may be formed. Since the composition ratio is hard to be kept constant in each region, there is a problem in that oxygen of the oxide semiconductor constituting the active layer 141 is captured with nitrogen supplements insufficient in some regions. As the oxygen of the oxide semiconductor is concentrated at the interface between the active layer 141 and the gate insulating layer 130 of the oxide semiconductor, the crystallinity of the active layer 141 is reduced due to the lack of oxygen, and thus the charge transfer is also lowered. Is generated.

Accordingly, the gate insulating layer 130 and the passivation layer 200 disposed adjacent to and below the active layer 141 are considered in consideration of the active layer 141 of the oxide semiconductor that reacts sensitively to the surrounding dielectric constant. It is selected as an oxide-based insulating material that can be laminated at a stable composition ratio than the insulating material. In this case, a representative example of the oxide-based insulating material may be silicon oxide (SiO ₂ ).

That is, according to the exemplary embodiment of the present invention, the gate insulating layer 130 is formed on the first gate insulating layer 131 of SiNx formed on the entire surface of the substrate 110, and SiO ₂ formed on the entire surface of the first gate insulating layer 131. The second gate insulating layer 132 may have a stacked structure, and the passivation layer 200 may be formed of SiO ₂ .

As described above, when the second gate insulating layer 132 and the protective layer 200 are formed of SiO ₂ , the dielectric constant variation of each region is maintained as the composition ratio of silicon (Si) and oxygen (O) is more stable than that of silicon nitride (SiNx). It is possible to minimize and to prevent the oxygen escape problem of the oxide semiconductor.

Therefore, the electrostatic characteristic of the thin film transistor TFT can be more stabilized, and the uniformity of characteristics can be increased, so that the thin film transistor TFT can be suitably applied to a transistor array substrate of a high resolution or large size flat panel display device.

Meanwhile, the pixel electrode 310 (which corresponds to “PE” in FIG. 1) and the common electrode 320 (which corresponds to “CE” in FIG. 1) are formed on the passivation layer 200. In this case, the pixel electrode 310 is connected to the drain electrode 162 through the pixel electrode hole H_PE passing through the passivation layer 200 corresponding to at least a portion of the drain electrode 162.

In addition, the storage lower electrode 122 is formed on the substrate 110 as a part of a common line (corresponding to “CL” in FIG. 1), and the drain electrode 162 is disposed between the gate insulating layer 130 and the storage lower electrode. Extend to overlap at least a portion of 122. In addition, the storage upper electrode extending from the pixel electrode 310 overlaps at least a portion of the storage lower electrode 122 with the passivation layer 200 and the gate insulating layer 130 interposed therebetween, and the passivation layer 200 interposed therebetween. At least a portion of the drain electrode 162 overlaps with the drain electrode 162.

As shown in BB ′ of FIG. 2, the gate pad GP at the end of the gate line (corresponding to “GL” in FIG. 1) is formed of a substrate formed together with the gate line GL and the gate electrode 121. The first gate pad layer 123 on the 110, the gate insulating layer 130 covering the first gate pad layer 123, and the at least a portion of the first gate pad layer 123 penetrate through the gate insulating layer 130. Formed on the gate insulating layer 130 together with the first gate pad hole H1_GP and the source / drain electrodes 161 and 162 and connected to the first gate pad layer 123 through the first gate pad hole H1_GP. A second gate penetrating the passivation layer 200 corresponding to at least a portion of the second gate pad layer 163, the passivation layer 200 covering the second gate pad layer 163, and the second gate pad layer 163. The pad hole H2_GP and the pixel electrode 310 and the common electrode 320 are formed on the passivation layer 200 and connected to the second gate pad layer 163 through the second gate pad hole H2_GP. A third gate pad layer 330 is formed. Here, the gate pad hole H_GP shown in FIG. 1 includes a first gate pad hole H1_GP and a second gate pad hole H2_GP.

As shown in C-C 'of FIG. 2, the data pad DP at the end of the data line (corresponding to "DL" in FIG. 1) is together with the data line DL and the source / drain electrodes 161 and 162. The passivation layer 200 corresponding to at least a portion of the first data pad layer 164, the passivation layer 200 covering the first data pad layer 164, and the first data pad layer 164 formed on the gate insulating layer 130. ) Is formed on the passivation layer 200 together with the data pad hole H_DP and the pixel electrode 310 and the common electrode 320, and the first data pad layer 164 is formed through the data pad hole H_DP. And a second data pad layer 340 connected thereto.

Next, referring to FIGS. 3, 4, 5A to 5C, 6, 7A to 7H, 8A to 8D, and 9 to 11, a transistor array substrate according to an embodiment of the present invention will be described. A manufacturing method is demonstrated.

FIG. 3 is a flowchart illustrating a method of manufacturing a transistor array substrate according to an exemplary embodiment of the present invention, and FIG. 4 is a flowchart illustrating "forming an active layer, an etch stopper, and a first gate pad hole" shown in FIG. 3. . 5A to 5C, 6A, 7A to 7H, 8A to 8D, and 9 to 11 illustrate a method of manufacturing the transistor array substrate illustrated in FIGS. 3 and 4 for each step. Process sectional drawing which shows A-A ', BB', and C-C '.

As shown in FIG. 3, in the method of manufacturing the transistor array substrate according to the exemplary embodiment of the present invention, in the first mask process, the first metal layer on the substrate is patterned to form a gate line, a gate electrode branched from the gate line, and a gate. Forming a first gate pad layer at the end of the line (S100), forming a gate insulating film covering the gate line, the gate electrode, and the first gate pad layer on the entire surface of the substrate (S200), in the second mask process Selectively patterning the gate insulating film, the first material layer and the second material layer on the gate insulating film so as to at least partially overlap the gate electrode, an etch stopper on a portion of the active layer including a channel region, and a first gate pad layer Forming a first gate pad hole penetrating through the gate insulating layer corresponding to a portion of the phase (S300); in the third mask process, forming the second metal layer on the gate insulating layer Turning, the source electrode branched from the data line and in contact with one side on the active layer, the drain electrode spaced apart from the source electrode with the channel region interposed therebetween, and the first electrode through the first gate pad hole. Forming a second gate pad layer in contact with the gate pad layer and a first data pad layer at the end of the data line (S400); a data line, a source electrode, a drain electrode, and a second gate pad layer on the entire surface of the gate insulating layer; And forming a passivation layer covering the first data pad layer (S500), a second gate pad hole penetrating through the passivation layer corresponding to a portion on the second gate pad layer in a fourth mask process, and a portion on the first data pad layer. Forming a data pad hole penetrating the passivation layer corresponding to the passivation layer and a pixel electrode hole penetrating the passivation layer corresponding to a portion of the drain electrode (S600); and a fifth mask hole. Patterning the third metal layer on the passivation layer to form a pixel electrode connected to the drain electrode through the pixel electrode hole, a third gate pad layer contacting the second gate pad layer through the second gate pad hole, and a data pad hole. Forming a second data pad layer in contact with the first data pad layer through (S700).

As shown in FIG. 4, in the forming of the active layer, the etch stopper and the first gate pad hole (S300), the first material layer, the second material layer and the photoresist layer are sequentially formed on the entire surface of the gate insulating layer. Step S310 and patterning the photoresist layer to form a first pattern (S320).

In this case, the first pattern includes a hole penetrating through the photoresist layer corresponding to a portion on the first gate pad layer in the first region, and a photoresist layer having a first thickness corresponding to a portion on the gate electrode in the second region. And a photoresist layer having a thickness less than or equal to the first thickness in the third region except for the first region and the second region.

By using the first pattern as a mask, a portion of the second material layer exposed in the first region, a portion of each of the subsequent first material layer and the gate insulating film that are subsequently removed, and a portion of the first gate pad layer are exposed. Forming a first gate pad hole (S330), and performing a first ashing treatment on the first pattern to remove the photoresist layer in the first region and the third region, and to remove the photoresist layer in the second region. Forming a second pattern including a photoresist layer having a third thickness and a first width that is less than or equal to the thickness (S340), and using the second pattern as a mask to expose the gate insulating film in the first region and the third region. Removing other portions of the material layer and subsequent portions of the first material layer, and forming an active layer with the first material layer remaining by the second pattern in the second region (S350); The second ashing process is performed to the second area. Forming a third pattern of a photoresist layer corresponding to a portion including the channel region of the active layer and having a second width less than the first width (S360); using the third pattern as a mask, Removing another part of the second material layer to expose another part of the active layer in the step S, forming an etch stopper with the second material layer remaining by the third pattern (S370), and remaining on the etch stopper. Removing the third pattern (S380).

Hereinafter, referring to process cross-sectional views shown in FIGS. 5A to 5C, 6, 7A to 7H, 8A to 8D, and 9 to 11, a transistor array substrate according to an embodiment of the present invention will be described. The manufacturing method will be described in more detail.

As shown in FIG. 5A, the first metal film 120 is stacked on the entire surface of the substrate 110, and the first metal film pattern 410 is formed by the first mask process. Next, as shown in FIG. 5B, the first metal film 120 is patterned using the first metal film pattern 410 as a mask. Accordingly, the gate line (not shown, corresponding to "GL" in FIG. 1), the gate electrode 121 branched from the gate line, the common line (not shown, corresponding to "CL" in FIG. 1), and extended from the common line The storage lower electrode 122 and the first gate pad layer 123 at the end of the gate line are formed (S100).

In this case, the first metal film 120 on the substrate 110 may be a single layer of at least one of Al, Cu, Mo, Nd, Ti, Pt, Ag, Nb, Cr, W, and Ta, or at least two or more layers, or May be selected as the alloy.

Subsequently, as shown in FIG. 5C, the first remaining on the gate line GL, the common line CL, the gate electrode 121, the storage lower electrode 122, and the first gate pad layer 123, respectively. The pattern (“410” in FIG. 5B) is removed.

As shown in FIG. 6, the gate insulating layer 130 is formed on the entire surface of the substrate 110 (S200). In this case, the gate line GL, the common line CL, the gate electrode 121, the storage lower electrode 122, and the first gate pad layer 123 formed on the substrate 110 may have a gate insulating layer 130 formed thereon. Covered by).

In particular, the forming of the gate insulating layer 130 (S200) may include stacking an oxide-based insulating material on the entire surface of the substrate 110.

Alternatively, the forming of the gate insulating layer 130 (S200) may include forming a first gate insulating layer 131 of a nitride-based insulating material, and forming a gate insulating layer 130 on the entire surface of the first gate insulating layer 131. The gate insulating layer 132 may be formed.

The nitride-based insulating material has a composition including nitrogen (N) and is selected as an insulating material having a higher dielectric constant than the oxide-based insulating material, in particular, may be selected as silicon nitride (SiNx).

The oxide-based insulating material is selected as an insulating material having a composition containing oxygen (O) and capable of maintaining a stable composition ratio than the nitride-based insulating material, in particular, silicon oxide (SiNx), more preferably SiO ₂ may be selected. .

In addition, according to an exemplary embodiment of the present invention, the active layer 141 to be formed on the gate insulating layer 130 is a layer which is directly in contact with the active layer 141 such that the active layer 141 is disposed adjacent to the oxide-based insulating material stacked at a stable composition ratio. The gate insulating film 132 is selected as an oxide insulating material.

However, embodiments of the present invention are not limited thereto, and the gate insulating layer 130 may be formed of a single layer of an oxide insulating material, or may be formed of two or more layers including the uppermost layer of the oxide insulating material.

Subsequently, as shown in FIG. 7A, the first material layer 140 and the second material layer 150 are sequentially stacked on the entire surface of the gate insulating film 130, and as shown in FIG. 7B, the second material. The photoresist layer 420 is stacked on the entire surface of the layer 150 (S310).

At this time, the first material layer 140 is selected as an oxide semiconductor of AxByCzO (x, y, z ≥ 0), wherein A, B and C are each selected from Zn, Cd, Ga, In, Sn, Hf and Zr. Is selected. In particular, the first material layer 140 may be selected from ZnO, InGaZnO ₄ , ZnInO, ZnSnO, InZnHfO, SnInO, and SnO.

In addition, the second material layer 150 may be selected as a material having a relatively high etching ratio to the etching liquid or the etching gas used in the subsequent step of forming the source / drain electrodes. For example, the material layer 150 may be selected from at least one of inorganic materials of SiOx, SiNx, SiOCx, and SiONx, or at least one of an organic material and a polymer organic material, and in particular, SiOx.

The photoresist layer 420 is selected as a photosensitive material which is a polymer material whose physical properties change with light in a specific wavelength region. At this time, the photosensitive material is classified into a positive type in which a region exposed to light is dissolved in a solvent and a negative type in which a region exposed to light is not dissolved in a solvent, according to an embodiment of the present invention. The photoresist layer 420 may be selected as a negative photosensitive material.

As shown in FIG. 7B, light is selectively irradiated onto the photoresist layer 420 using the halftone mask 500, and developed to pattern the photoresist layer 420.

In this case, the halftone mask 500 includes a shielding part 501 for blocking light, a first transmitting part 501 for transmitting light at a first transmittance, and a second transmitting part for transmitting light at a second transmittance lower than the first transmittance. 503. By the halftone mask 500, a differential amount of light may be irradiated onto the photoresist layer 420.

As a result, as illustrated in FIG. 7C, the first pattern 421 is formed (S320). In this case, the first pattern 431 includes a hole H penetrating the photoresist layer to expose the second material layer 150 in the first region P1, and in the second region P2. The photoresist layer is formed of a photoresist layer having a first thickness TH1 and is formed of a photoresist layer less than or equal to the second thickness TH2 that is less than the first thickness in the third region P3.

For example, when the photoresist layer 420 is a negative photosensitive material, the shielding portion 501 of the halftone mask 500 is disposed on the first region P1 to form the first region P1. All light is dissolved by blocking light in the photoresist layer. The first transmission part 502 of the halftone mask 500 is disposed on the second region P2, and a large amount of light is irradiated to the photoresist layer of the second region P2, thereby not dissolving the first thickness ( TH1). The second transmission part 503 of the halftone mask 500 is disposed on the third region P3, so that a smaller amount of light is applied to the photoresist layer of the third region P3 than the second region P2. By irradiating, it melt | dissolves in part and becomes thinner by 2nd thickness TH2.

7B and 7C, and the description thereof are merely examples of the step of forming the first pattern 421 by patterning the photoresist layer 420. Of course, it is not limited. For example, when the photoresist layer 420 is a positive type, another halftone mask 500 may be applied, and the patterning of the photoresist layer 420 may be performed in other ways.

As shown in FIG. 7D, in the first region P1, a portion of the second material layer 150 is exposed by the hole H in the first region P1 by using the first pattern 421 as a mask. By performing the process, a portion of the exposed second material layer 150 and a portion of each of the first material layer 140 and the gate insulating layer 130 subsequent thereto are removed. Accordingly, in the first region P1, a first gate pad hole H1_GP penetrating the gate insulating layer 130 is formed to expose the first gate pad layer 123 (S330).

As shown in FIG. 7E, a first ashing treatment is performed on the first pattern (“421” in FIG. 7D) to form a second pattern 422 (S340).

In this case, the primary ashing process is to reduce the thickness of the photoresist layer as a whole. As the thickness of the first pattern 421 is generally thinned, in the first and third regions P1 and P3, the photoresist layer The second pattern 422 is formed by exposing the second material layer 150 and forming a photoresist layer having a third thickness and a first width W1 that are less than or equal to the first thickness TH1 in the second region P2. ) Is formed.

As shown in FIG. 7F, the second material layer 150 is different from the first and third regions P1 and P3 except for the second region P2 by using the second pattern 422 as a mask. In the exposed state, the etching process is performed to remove other portions of the exposed second material layer 150 and subsequent portions of the first material layer 140. Accordingly, other portions of each of the first and second material layers 140 and 150 are removed to expose the gate insulating layer 130 in the first and third regions P1 and P3. At this time, in the second region P2, the first and second material layers 141 and 150 ′ remain due to the second pattern 422, and the active layer 141 is the remaining first material layer. To form (S350).

Meanwhile, in the forming of the active layer 141 (S350), another part of each of the first and second material layers 140 and 150 in the first and third regions P1 and P3 may be formed using a wet etching process. It can be carried out by removing the batch.

Alternatively, in the forming of the active layer 141 (S350), another portion of the second material layer 150 is first removed from the first and third regions P1 and P3 using a dry etching process, and then wet etching is performed. The process may be used to remove other portions of the first material layer 140 that follow the other portions of the second material layer 150 removed in the first and third regions P1 and P3.

Meanwhile, after the etching process using the second pattern, the remaining second material layer 150 ′ has a wider width than the first material layer, that is, the active layer 141. Therefore, the active layer 141 and the second material layer 150 ′ formed thereon form an under cut structure.

To compensate for this, the formation of the third pattern 423 and the patterning of the second material layer 150 ′ using the third pattern as a mask are additionally performed.

That is, as illustrated in FIG. 7G, the second ashing process is performed on the second pattern (“422” in FIG. 7E) to form a third pattern 423 (S360).

In this case, the secondary ashing process is to uniformly cut off the side surface of the photoresist layer, and the side surface of the second pattern 422 is gradually cut off at a similar speed, and is less than the first width W1 in the second region P2. A third pattern 423 formed of a photoresist layer having two widths W2 is formed.

By the third pattern 423, another portion of the second material layer 150 ′ that does not correspond to a portion including the channel region of the active layer 141 is exposed.

In this state, another part of the exposed second material layer 150 ′ is removed by performing an etching process using the third pattern 423 as a mask. Thus, the etch stopper 151 is formed of the second material layer remaining by the third pattern 423 (S370).

As shown in FIG. 7H, the third pattern (“423” in FIG. 7G) remaining on the etch stopper 151 is removed (S380).

Next, as shown in FIG. 8A, a second metal film 160 is formed on the entire surface of the gate insulating film 130 including the active layer 141 and the etch stopper 151 thereon, and as shown in FIG. 8B. As described above, the second metal film pattern 430 is formed by patterning the photoresist layer stacked on the second metal film 160 using the third mask process.

In this case, like the first metal film 120, the second metal film 160 on the gate insulating film 130 may include at least one of Al, Cu, Mo, Nd, Ti, Pt, Ag, Nb, Cr, W, and Ta. It may be selected as one single layer, or at least two or more layers or alloys.

Next, as shown in FIG. 8C, the second metal film 160 is patterned using the second metal film pattern 430 to thereby contact the source electrode 161 and the drain electrode on both sides of the active layer 141. 162, a second gate pad layer 163 contacting the first gate pad layer 123 through the first gate pad hole H1_GP, and a data line (not shown, corresponding to “DL” in FIG. 1) and data. The first data pad layer 164 at the end of the line DL is formed (S400).

As shown in FIG. 8D, the second metal remaining on the data line DL, the source electrode 161, the drain electrode 162, the second gate pad layer 163, and the first data pad layer 164. The film pattern ("430" in FIG. 8C) is removed.

In this case, a channel region of the gate electrode 121, the gate insulating layer 130, the active layer 141, the etch stopper 151, the source electrode 161 branched from the data line DL, and the active layer 141 may be formed. A thin film transistor TFT including a source electrode 161 and a drain electrode 162 spaced apart from each other is generated.

As shown in FIG. 9, a gate insulating layer 130 including a data line DL, a source electrode 161, a drain electrode 162, a second gate pad layer 163, and a first data pad layer 164. A protective film 200 is formed on the entire surface of the image (S500).

In this case, the passivation layer 200 may be selected as an insulating material capable of maintaining a constant dielectric constant for each region with a constant composition. In particular, like the second gate insulating layer 312, the protective layer 200 may be selected as an oxide-based insulating material such as SiO _2. have.

As shown in FIG. 10, by using a fourth mask process, a photoresist layer (not shown) on the passivation layer 200 is patterned, so that a portion on the drain electrode 162 and a portion on the second gate pad layer 163 are formed. And a hole pattern (not shown) including holes (not shown) corresponding to portions of the first data pad layer 164. The passivation layer 200 is patterned by using a hole pattern (not shown) as a mask, so that the pixel electrode hole H_PE, the second gate pad hole H2_GP, and the data pad hole H_DP penetrate the passivation layer 200. To form (S600).

In other words, a pixel electrode hole H_PE penetrating the passivation layer 200 is formed corresponding to a portion of the drain electrode 162, and penetrating the passivation layer 200 corresponding to a portion of the second gate pad layer 163. A second gate pad hole H2_GP is formed, and a data pad hole H_DP penetrating through the passivation layer 200 is formed corresponding to a portion of the first data pad layer 164.

Next, as illustrated in FIG. 11, a third metal film (not shown) and a photo are formed on the passivation layer 200 including the pixel electrode hole H_PE, the second gate pad hole H2_GP, and the data pad hole H_DP. A resist layer (not shown) is sequentially formed, and a third metal film pattern (not shown) is formed by patterning a photoresist layer (not shown) on the third metal film (not shown) using a fifth mask process. do. Then, the third metal film (not shown) is patterned using the third metal film pattern (not shown) to thereby form the pixel electrode 310 ("PE" in FIG. 1) and the common electrode 320 ("CE" in FIG. 1). "), The third gate pad layer 330 and the second data pad layer 340 are formed (S700).

Subsequently, the remaining material on the pixel electrode 310 ("PE" in FIG. 1), the common electrode 320 ("CE" in FIG. 1), the third gate pad layer 330, and the second data pad layer 340. 3 Remove the metal film pattern (not shown).

In this case, at the end of the gate line GL, the first gate pad layer 123 on the substrate 110, the first gate pad hole H1_GP penetrating through the gate insulating layer 130, and the second gate pad layer 163. The gate pad GP including the second gate pad hole H2_GP and the third gate pad layer 330 penetrating the passivation layer 200 is formed.

The first data pad layer 164 on the gate insulating layer 130, the data pad hole H_DP penetrating through the passivation layer 200, and the second data pad layer 340 are included at the end of the data line DL. The data pad DP is formed.

As described above, according to the exemplary embodiment of the present invention, both the active layer 141 and the etch stopper 151 may be formed using one mask process, that is, the second mask process. Since a one-time mask process for forming 151 is not necessary, the process can be simpler than before.

The gate pad hole H_GP penetrating both the gate insulating layer 130 and the passivation layer 200 is not formed in one etching process, and the first gate pad hole H1_GP penetrating the gate insulating layer 130 is formed. Due to the structure including the second gate pad hole H2_GP penetrating through the passivation layer 200, it is formed by dividing it into two etching processes. In particular, the second gate pad hole H2_GP, the pixel electrode hole H_PE, and the data pad hole H_DP are formed by an etching process of removing the protective layer 200 only.

Accordingly, since the etching process does not need to be performed for a long process time to remove the gate insulating film 130 to form the gate pad hole H_GP, the drain electrode 162 formed on the gate insulating film 130. ) And a part of the surface of the first data pad layer 164 may be prevented from being damaged by being exposed to the etching process by the pixel electrode hole H_PE and the data pad hole H_DP.

In this case, since the formation of the first gate pad hole H1_GP is simultaneously performed in the second mask process together with the active layer 141 and the etch stopper 151, the formation of the gate pad hole H_GP is divided into two etching processes. Even if it does, it is not necessary to add a separate mask process, and a manufacturing process does not become complicated and long compared with the former.

Therefore, damage to the passivation layer 200 forming the sidewalls of the pixel electrode hole H_PE and the data pad hole H_DP can be minimized, so that the junction surface between the drain electrode 162 and the first data pad layer 164 is reduced. This can be kept flat. Accordingly, even in the pixel electrode hole H_PE, the pixel electrode PE may be evenly formed, and thus, the risk of disconnection of the pixel electrode PE may be reduced, so that the control of each pixel may be uniform, thereby forming a transistor array substrate. The device reliability of can be improved.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes may be made without departing from the technical spirit of the present invention.

GL: Gate Line GP: Gate Pad
H_GP: Gate pad hole CL: Common line
DL: data line DP: data pad
H_DP: Data pad hole TFT: Thin film transistor
PE, 310: pixel electrode H_PE: pixel electrode hole
CE, 320: common electrode H_CE: common electrode hole
121: gate electrode 130: gate insulating film
141: active layer 151: etch stopper
161: source electrode 162: drain electrode
200: protective film 123: first gate pad layer
H1_GP: first gate pad hole 163: second gate pad layer
H2_GP: Second gate pad hole 330: Third gate pad layer
164: first data pad layer 340: second data pad layer

Claims (12)

Patterning a first metal film on the substrate to form a gate line, a first gate pad layer at the end of the gate line, and a gate electrode branched from the gate line in a first mask process;
Forming a gate insulating film on the entire surface of the substrate to cover the gate line, the first gate pad layer, and the gate electrode;
In a second mask process, the gate insulating layer, a first material layer on the gate insulating layer, and a second material layer are selectively patterned to partially overlap the gate electrode with at least a portion of the active layer, including a channel region of the active layer. Forming a etch stopper and a first gate pad hole penetrating through the gate insulating layer corresponding to a portion on the first gate pad layer;
In a third mask process, the second metal layer on the gate insulating layer is patterned to separate the data line, the source electrode branched from the data line to be in contact with one side on the active layer, and spaced apart from the source electrode with the channel region interposed therebetween. Forming a drain electrode in contact with the other side of the active layer, a second gate pad layer in contact with the first gate pad layer through the first gate pad hole, and a first data pad layer at the end of the data line;
Forming a passivation layer on the gate insulating layer, the passivation layer covering the data line, the source electrode, the drain electrode, the second gate pad layer, and the first data pad layer;
In the fourth mask process, a second gate pad hole penetrating the passivation layer corresponding to a portion on the second gate pad layer, a data pad hole penetrating the passivation layer corresponding to a portion on the first data pad layer, and the Forming a pixel electrode hole penetrating the passivation layer corresponding to a portion of the drain electrode; And
In a fifth mask process, a third metal layer on the passivation layer is patterned to contact the second gate pad layer through the second gate pad hole, and the first data pad through the data pad hole. Forming a second data pad layer on the layer and a pixel electrode connected to the drain electrode through the pixel electrode hole. The method of claim 1,
Forming the active layer, the etch stopper and the first gate pad hole,
Sequentially forming the first material layer, the second material layer and the photoresist layer on the entire surface of the gate insulating film;
Patterning the photoresist layer to include a hole passing through the photoresist layer corresponding to a portion on the first gate pad layer in a first region, and having a first thickness corresponding to a portion on the gate electrode in a second region Forming a first pattern comprising a photoresist layer having a photoresist layer having a thickness less than or equal to the first thickness in the remaining third regions except for the first and second regions;
By using the first pattern as a mask, a portion of the second material layer exposed in the first region, a portion of the first material layer and the gate insulating layer subsequent to it are removed, and a portion of the first gate pad layer is removed. Forming the first gate pad hole exposing the first gate pad hole;
A first ashing treatment is performed on the first pattern to remove the photoresist layer in the first region and the third region, and a third thickness and a third thickness less than or equal to the first thickness in the second region. Forming a second pattern consisting of a photoresist layer of one width;
Using the second pattern as a mask, removing another portion of the second material layer and another portion of the first material layer subsequent to the other portion of the second material layer to expose the gate insulating film in the first region and the third region; Forming the active layer with a first material layer remaining by the second pattern in a second region;
Secondary ashing is performed on the second pattern to form a third pattern including a photoresist layer having a second width corresponding to a portion including the channel region of the active layer in the second region and less than the first width. Doing;
Using the third pattern as a mask, in the second region, another portion of the second material layer is removed to expose another portion of the active layer, and the second material layer remaining by the third pattern is removed. Forming the etch stopper; And
Removing the third pattern remaining on the etch stopper. The method of claim 2,
In the step of sequentially forming the first material layer, the second material layer and the photoresist layer, the first material layer is an oxide semiconductor of AxByCzO (x, y, z ≥ 0), the A, B and C Each of Zn, Cd, Ga, In, Sn, Hf and Zr. The method of claim 3,
And the first material layer is selected from ZnO, InGaZnO ₄ , ZnInO, ZnSnO, InZnHfO, SnInO, and SnO. The method of claim 3,
And sequentially forming the first material layer, the second material layer and the photoresist layer, wherein the second material layer is selected as an oxide-based insulating material. The method of claim 3,
And forming the passivation layer, wherein the passivation layer is selected from an oxide insulating material. The method of claim 3,
And forming the gate insulating film, wherein the gate insulating film is selected from an oxide insulating material. The method of claim 3,
Forming the gate insulating film,
Forming a first gate insulating film selected as a nitride based insulating material on the entire surface of the substrate; And
Forming a second gate insulating film selected as an oxide-based insulating material on the entire surface of the first gate insulating film. 9. The method of claim 8,
Forming the first gate pad hole
Removing at least a portion of each of the first material layer, the second material layer, and the second gate insulating film in the first region using a wet etching process; And
Removing at least a portion of the first gate insulating film in the first region by using a dry etching process. The method of claim 2,
In the step of forming the active layer,
Using a wet etching process to collectively remove another portion of the second material layer and subsequent portions of the first material layer in the first region and the third region. The method of claim 2,
Forming the active layer,
Using a dry etching process to remove other portions of the second material layer in the first region and the third region; And
Removing another portion of the first material layer subsequent to another portion of the second material layer in the first region and the third region using a wet etch process. The method of claim 2,
In the forming of the first pattern, a shielding part blocking light corresponding to the first area, a first transmitting part transmitting light at a first transmittance corresponding to the second area, and a corresponding third area And a halftone mask comprising a second transmission portion for transmitting light at a second transmission rate lower than the first transmission rate.

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