KR20130012742A

KR20130012742A - Transistor array substrate and manufacturing method of the same

Info

Publication number: KR20130012742A
Application number: KR1020110074089A
Authority: KR
Inventors: 유태상; 정득수
Original assignee: 엘지디스플레이 주식회사
Priority date: 2011-07-26
Filing date: 2011-07-26
Publication date: 2013-02-05

Abstract

PURPOSE: A transistor array substrate and a manufacturing method thereof are provided to reduce parasitic capacitors of a thin film transistor by arranging nitridebased insulating materials between a drain electrode and a gate electrode. CONSTITUTION: A first gate insulating film(131) is formed as nitridebased insulating materials on the front surface of a substrate. A gate line, a common line, and a lower storage electrode(122) are covered with the first gate insulating film. A second gate insulating film(132) is formed as oxide insulating materials on the front surface of the first gate insulating film. A part of an upper storage electrode(182) is overlapped with a lower storage electrode through a storage hole. A space between the upper storage electrode and the lower storage electrode includes a passivation film(170) and the first gate insulating film.

Description

Transistor Array Substrate and Manufacturing Method of The Same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor array substrate and a method for manufacturing the same, which are applied to a flat panel display of an active matrix driving method, define a plurality of pixel regions corresponding to a plurality of pixels, and selectively drive the plurality of pixels.

In recent years, as the information age has entered, the display field for visually expressing electrical information signals has been rapidly developed, and various flat panel display devices having excellent performance of thinning, light weight, and low power consumption have been developed. Flat Display Device has been developed to quickly replace the existing Cathode Ray Tube (CRT).

Specific examples of such a flat panel display include a liquid crystal display (LCD), an organic light emitting display (OLED), an electrophoretic display (EPD, Electric Paper Display), Plasma Display Panel Device (PDP), Field Emission Display Device (FED), Electroluminescence Display Device (ELD) and Electro-Wetting Display (EWD) Etc. can be mentioned. These are commonly required components of a flat panel display panel that implements an image. The flat panel includes a pair of substrates bonded to each other with a layer of a light emitting material or a polarizer interposed therebetween.

Meanwhile, the driving method of the flat panel display panel may be classified into a passive matrix driving mode and an active matrix driving mode.

In the passive matrix driving method, a plurality of pixels are formed at an intersection area of a gate line and a data line, and each pixel is driven by applying signals to gate lines and data lines that cross each other. While the passive matrix driving method has the advantage of being simple to control, signals applied to the gate line and the data line, respectively, affect several pixels corresponding to them, so that it is difficult to drive each pixel independently. There is a disadvantage of having a low sharpness and a long response speed, and thus has a disadvantage of difficult to realize high resolution.

The active matrix driving method is a method of selectively driving a plurality of pixels by using a transistor array including a plurality of switching elements respectively corresponding to the plurality of pixels. While the active matrix driving method has a disadvantage of complicated control, each pixel can be driven independently through a plurality of transistors that can be selectively turned on and off, thereby providing higher clarity and shorter response than the passive matrix driving method. There is an advantage in that speed can be realized, and thus an advantage in high resolution.

In general, a transistor array includes a plurality of thin films disposed in a gate line and a data line intersecting to define a plurality of pixel regions respectively corresponding to a plurality of pixels, and intersecting regions of the gate line and the data line. A transistor includes a thin film transistor and a plurality of pixel electrodes respectively formed in the plurality of pixel regions.

The thin film transistor overlaps the gate electrode with the gate electrode connected to the gate line, the source electrode connected with the data line, the drain electrode connected with the pixel electrode corresponding to each pixel, and the gate insulating layer interposed therebetween. And an active layer forming a channel between the source electrode and the drain electrode according to the voltage level.

In this case, the active layer is generally formed of silicon semiconductors such as amorphous silicon (a-Si) and crystalline silicon (poly silicon, p-Si).

By the way, the active layer of the crystalline silicon has the advantage of having a relatively high charge mobility (mobility) and stable electrostatic properties. On the other hand, there is a disadvantage of limiting the material of the support substrate due to the high temperature atmosphere in the lamination, and high defect rate of crystal defects due to high temperature, making it difficult to secure uniform device characteristics. There is a problem that causes degradation.

The active layer of amorphous silicon can be laminated in a low temperature atmosphere compared to crystalline silicon, there is an advantage in the manufacturing process. On the other hand, there is a disadvantage in that it has lower charge mobility and unstable electrostatic characteristics than crystalline silicon, which is a factor to maintain the wiring resistance and parasitic capacitance of the transistor array above the threshold, and thus is limited to be applied to large or high resolution flat panel display devices. There is a problem.

On the other hand, oxide semiconductors having higher charge mobility and stable electrostatic properties than amorphous silicon, which can be stacked in a low temperature atmosphere compared to crystalline silicon, have recently been proposed as a new active layer material.

However, oxide semiconductors have a disadvantage in that they have electrostatic characteristics that are sensitive to the dielectric constant of the surroundings. Accordingly, the gate insulating layer and the protective layer disposed adjacent to the upper and lower portions of the active layer should be selected as an oxide-based insulating material that can be stacked with a relatively stable composition ratio so that the dielectric constant of each region is kept constant.

On the other hand, the oxide-based insulating material has a disadvantage of showing a low bonding properties and a low dielectric constant compared to the nitride-based insulating material.

Accordingly, when the gate insulating layer is selected as an oxide insulating material, there is a problem of deterioration of device characteristics due to poor bonding with the substrate.

The storage capacitor corresponding to each pixel is generated in an area where the storage lower electrode and the storage upper electrode overlap with each other with a gate insulating film or a protective film interposed therebetween. Accordingly, the capacity of the storage capacitor is proportional to the dielectric constant of the gate insulating film or the protective film between the storage lower electrode and the storage upper electrode. Therefore, the lower the dielectric constant of the gate insulating film or the protective film, the lower the capacity of the storage capacitor.

That is, when the gate insulating film and the protective film are selected as an oxide dielectric material having a low dielectric constant, a storage capacitor having a predetermined capacity can be secured only by increasing the area of the storage capacitor or by increasing the thickness of at least one of the gate insulating film and the protective film. .

Here, the predetermined capacitance of the storage capacitor refers to a capacitance that maintains the voltage level of the pixel electrode above the offset voltage during each frame. That is, if a storage capacitor of a predetermined capacity cannot be secured, the brightness of each pixel cannot be maintained for one frame, and thus there is a problem in that image quality deteriorates.

At this time, when the gate insulating layer is formed to a thick thickness, the parasitic capacitance of the thin film transistor is increased together with the kick back voltage. Here, the kickback voltage refers to a voltage at which the voltage level of the pixel electrode raised in the turn-on operation of the thin film transistor is rapidly lowered due to the parasitic capacitance of the thin film transistor immediately after the turn-off operation of the thin film transistor.

In addition, since the storage capacitor is formed in the pixel area, when the storage capacitor is formed in a large area, the effective area in which light is substantially emitted in the pixel area is reduced, so that image quality is deteriorated.

The present invention provides a transistor array substrate including an active layer of an oxide semiconductor, while securing a storage capacitor having a predetermined capacity, while preventing the increase of the parasitic capacitance of the thin film transistor or the increase of the area of the storage capacitor, and its manufacture It is to provide a method.

In order to solve such a problem, the present invention is a substrate; A gate line in a first direction formed on the substrate; A common line formed on the substrate and insulated from the gate line; A storage lower electrode formed as part of the common line; A first gate insulating layer formed of a nitride based insulating material on an entire surface of the substrate to cover the gate line, the common line, and the storage lower electrode; A second gate insulating film formed of an oxide insulating material on an entire surface of the first gate insulating film; A storage hole penetrating through the second gate insulating layer corresponding to a portion of the storage lower electrode; A data line in a second direction perpendicular to the first direction on the second gate insulating film to define a pixel area corresponding to each pixel together with the gate line; A thin film transistor connected to the gate line and the data line; A passivation layer formed on an entire surface of the second gate insulating layer to cover the second data line and the thin film transistor; A pixel electrode formed in the pixel area on the passivation layer; And a storage upper electrode extending from the pixel electrode and at least partially overlapping the storage lower electrode through the storage hole, the protective layer and the first gate insulating layer interposed therebetween.

In order to solve this problem, the present invention is to pattern a first metal film on the substrate, the gate line in the first direction, the gate electrode branched from the gate line, the first direction insulated from the gate line and the gate electrode Forming a common line and a storage lower electrode which is part of the common line; Forming a first gate insulating film on the entire surface of the substrate, the nitride insulating material covering the gate line, the common line, the gate electrode, and the storage lower electrode; Forming a second gate insulating film on an entire surface of the first gate insulating film by using an oxide insulating material; An active layer overlapping at least a portion of the gate electrode on the second gate insulating layer, an etch stopper on a portion including a channel region of the active layer, and a portion of the storage lower electrode penetrating through the second gate insulating layer; Forming a storage hole; Patterning a second metal layer on the second gate insulating layer to define a pixel region corresponding to each pixel together with the gate line; a data line in a second direction perpendicular to the first direction; A source electrode in contact with one side on the layer, a drain electrode in contact with the other side on the active layer spaced apart from the source electrode with the channel region therebetween, and an extension of the drain electrode to extend the first gate insulating layer through the storage hole. Forming a storage extension electrode overlapping at least a portion of the storage lower electrode in between; Forming a passivation layer on an entire surface of the second gate insulating layer to cover the data line, the source electrode, the drain electrode, and the storage extension electrode; Forming a contact hole penetrating the passivation layer corresponding to a portion of the storage extension electrode; Patterning a third metal layer on the passivation layer to extend from the pixel electrode of the pixel region and the pixel electrode to be connected to the storage extension electrode through the contact hole, and overlap at least partially with each of the storage lower electrode and the storage extension electrode; It provides a method of manufacturing a transistor array substrate comprising the step of forming a storage upper electrode.

As described above, the transistor array substrate according to the present invention corresponds to a gate insulating film and a storage lower electrode formed of a double layer structure of a first gate insulating film of a nitride-based insulating material and a second gate insulating film of an oxide-based insulating material. It includes a storage hole penetrating.

Accordingly, a nitride-based insulating material having a relatively high dielectric constant is disposed between each of the source / drain electrodes and the active layers of the thin film transistor and the gate electrode, thereby reducing parasitic capacitance of the thin film transistor.

The storage capacitor is generated in an area where the lower storage electrode and the upper storage electrode overlap each other with the first gate insulating film and the passivation layer excluding the second gate insulating film through the storage hole. That is, the distance between the storage lower electrode and the storage upper electrode is reduced by the thickness of the second gate insulating layer by the storage hole, and in proportion thereto, the storage capacitor may have an increased area-to-capacity. Therefore, since the area of the storage capacitor can be reduced, the pixel area can be widened by that amount, and the image quality of the flat panel display device including the transistor array substrate can be improved.

In addition, the method of manufacturing a transistor array substrate according to the present invention forms a storage hole in a mask process corresponding to an active layer or an etch stopper, thereby preventing an increase in the number of mask processes, thereby reducing process time and manufacturing cost. have.

1 is a plan view illustrating a transistor array substrate according to an exemplary embodiment of the present invention.
FIG. 2 is a cross-sectional view illustrating II ′ of FIG. 1.
3 is a flowchart illustrating a method of manufacturing a transistor array substrate according to an embodiment of the present invention.
FIG. 4 is a flowchart of the first embodiment showing "step of forming an active layer, an etch stopper and a storage hole" shown in FIG.
FIG. 5 is a flow chart of the second embodiment showing "step of forming an active layer, an etch stopper and a storage hole" shown in FIG.
6A to 6C, 7, 7, 8, 9A to 9I, 10A to 10I, 11A to 11D, 12, 13A and 13B, and 14A to 14D are FIGS. 3 to 5. In the method for manufacturing a transistor array substrate shown in Fig. 1, it is a process sectional view showing I-I 'for each step.

Hereinafter, a transistor array substrate and a method of manufacturing the same according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a transistor array substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a plan view illustrating a transistor array substrate according to an exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating II ′ of FIG. 1. 1 is a diagram showing only one pixel among a plurality of pixels defined by a transistor array substrate for convenience.

As illustrated in FIG. 1, a transistor array substrate according to an exemplary embodiment of the present invention may be formed from gate lines GL and gate lines GL in a first direction (shown as “horizontal direction” in FIG. 1). Common line CL in the first direction to be insulated, data line DL in the second direction (shown as "vertical direction" in FIG. 1) crossing the gate line GL, and gate A thin film transistor TFT is disposed in an area where the line GL and the data line DL intersect each other. In this case, the gate line GL and the data line DL are intersected with each other to define a pixel area corresponding to each pixel. Although not separately illustrated in FIG. 1, the transistor array substrate is formed at the gate pad formed at the end of the gate line GL, the data pad formed at the end of the data line DL, and the end of the common line CL. A common pad is further included, and the gate pad, the data pad, and the common pad are used as terminals connecting the respective lines GL, DL, and CL to the outside.

The transistor array substrate further includes a pixel electrode PE formed in each pixel region, and a contact hole H_PE connecting the thin film transistor TFT and the pixel electrode PE.

In addition, the transistor array substrate is connected in parallel between the pixel electrode PE and the common electrode (not shown), and the pixel electrode PE to which the data signal of the data line DL is applied through the turned-on thin film transistor TFT. A storage capacitor Cst is further included to maintain the voltage level at or above the offset voltage Voffset until the end of one frame.

As shown in FIG. 2, the transistor TFT is formed on the entire surface of the gate electrode 121 and the substrate 110 formed by branching from a gate line (corresponding to “GL” in FIG. 1) on the substrate 110. The gate insulating layer 130 covering the gate electrode 121, the active layer 141 formed of an oxide semiconductor on the gate insulating layer 130, overlapping at least a portion of the gate electrode 121, and including a channel region, and an active layer. An etch stopper 151 formed on a portion including the channel region 141 is branched from the data line (corresponding to “DL” in FIG. 1) on the gate insulating layer 130 and formed on the active layer 141. A source electrode 161 formed to be in contact with one side, and a drain electrode formed to be in contact with the other side on the active layer 141 by being spaced apart from the source electrode 161 with a channel region therebetween on the gate insulating layer 130 ( 162).

The active layer 141 is formed of an oxide semiconductor of AxByCzO (x, y, z? 0), which is known to have higher charge mobility and stable electrostatic characteristics than silicon semiconductor. In this case, each of A, B, and C is selected from Zn, Cd, Ga, In, Sn, Hf, and Zr. In particular, the first and second active layers 141 and 142 may be any one of ZnO, InGaZnO ₄ , ZnInO, ZnSnO, InZnHfO, SnInO, and SnO, but the present invention is not limited thereto.

The gate insulating layer 130 includes a first gate insulating layer 131 made of a nitride-based insulating material on the entire surface of the substrate 110 and a second gate insulating layer 132 made of an oxide-based insulating material on the entire surface of the first gate insulating layer 131. It includes.

Representative examples of the nitride-based insulating material may be silicon nitride (SiNx). Silicon nitride (SiNx) has a relatively high dielectric constant, and has the advantage of ensuring an appropriate level of capacitance even at a relatively thin thickness, while the composition ratio of nitrogen and silicon at the time of lamination cannot be kept constant, and thus the dielectric constant of each region is different. There is a drawback to this.

That is, when the gate insulating film 130 is made of only a single layer of silicon nitride (SiNx) or includes the second gate insulating film 132 of silicon nitride (SiNx), nitrogen (N) and silicon (SiNx) constituting silicon nitride (SiNx) ( Since the composition ratio of Si) is difficult to be kept constant in each region, there is a problem in that oxygen of the oxide semiconductor constituting the active layer 141 is captured with nitrogen supplements insufficient in some regions.

Accordingly, oxygen of the oxide semiconductor is concentrated at the interface between the active layer 141 and the gate insulating film 130, and the crystallinity of the active layer 141 is lowered due to lack of oxygen, thereby lowering the charge mobility. .

Accordingly, in consideration of the characteristics of the oxide semiconductor that reacts sensitively to the dielectric constant of the surroundings, the second gate insulating layer 132 and the protective layer 170 disposed adjacent to the upper and lower portions of the active layer 141 may be nitride-based insulating materials. It is selected as an oxide-based insulating material that can be laminated at a more stable composition ratio. In this case, a representative example of the oxide-based insulating material may be silicon oxide (SiO ₂ ).

That is, according to the exemplary embodiment of the present invention, the gate insulating layer 130 is formed on the first gate insulating layer 131 of SiNx formed on the entire surface of the substrate 110, and SiO ₂ formed on the entire surface of the first gate insulating layer 131. The second gate insulating film 132 is laminated. In addition, the passivation layer 170 may be formed of SiO ₂ . As described above, the second gate insulating film 132 and the protective film 170 are formed of SiO ₂ , which can maintain the composition ratio of silicon (Si) and oxygen (O) more stably than the nitride-based insulating material, thereby changing the dielectric constant of each region. It can minimize the oxygen escape problem of the oxide semiconductor. As a result, the electrostatic characteristic of the TFT may be further stabilized, and the uniformity of the characteristic may be increased, and thus, the TFT may be suitably applied to a transistor array substrate of a high resolution or a large flat panel display.

The thin film transistor TFT configured as described above is covered with the passivation layer 170 formed on the entire surface of the gate insulating layer 130.

The pixel electrode 181 (corresponding to “PE” in FIG. 1) is formed in each pixel area on the passivation layer 170.

The storage capacitor Cst is insulated from the gate line (which corresponds to “GL” in FIG. 1) and the gate electrode 121 on the substrate 110, and the storage lower electrode 122 formed as part of the common line CL, In response to the storage lower electrode 122, the storage hole H_st penetrating through the second gate insulating layer 132 and the drain electrode 162 extend between the first gate insulating layer 131 through the storage hole H_st. At least partially overlapping the storage lower electrode 122, and extending from the pixel electrode 181 (“PE” in FIG. 1) on the passivation layer 170 including the storage hole H_st. Storage at least partially overlapping the storage extension electrode 163 with the passivation layer 170 interposed therebetween, and at least partially overlapping the storage lower electrode 122 with the passivation layer 170 and the first gate insulating layer 131 interposed therebetween. The upper electrode 182 is included.

In this case, the storage capacitor Cst includes an overlap region of the storage lower electrode 122 and the storage extension electrode 163 with the first gate insulating layer 131 interposed therebetween, and the first gate insulating layer 131 and the passivation layer 170. The storage lower electrode 122 and the storage upper electrode 182 interposed therebetween are generated in each of the regions.

The contact hole H_PE is formed to penetrate the passivation layer 170 in correspondence to a portion of the storage extension electrode 163. Through the contact hole H_PE, the storage upper electrode 182 is connected to the storage extension electrode 163. Accordingly, the pixel electrode 181 which is connected to the storage upper electrode 182 is connected to the drain electrode 162 which is connected to the storage extension electrode 163. That is, the pixel electrode 181 and the drain electrode 162 are electrically connected to each other through the contact hole H_PE.

Accordingly, the thin film transistor TFT turned on in response to the gate signal of the gate line (corresponding to “GL” of FIG. 1) transfers the data signal of the data line (corresponding to “DL” of FIG. 1) to the pixel electrode 181. Is authorized.

As described above, the transistor array substrate according to the embodiment of the present invention has a gate insulating film 130 having a stacked structure of a first gate insulating film 131 of a nitride insulating material and a second gate insulating film 132 of an oxide insulating material. It includes.

Accordingly, the active layer 141 of the TFT and the source / drain electrodes 161 and 162 overlap the gate electrode 121 with the gate insulating layer 130 having a double layer structure including a nitride-based insulating material interposed therebetween. . Therefore, unlike the conventional gate insulation layer 130 made of only an oxide-based insulating material, the gate insulating layer 130 has a relatively high dielectric constant in the overlap region between the active layer 141, the source / drain electrodes 161 and 162, and the gate electrode 121. Since the nitride-based insulating material is disposed, the parasitic capacitance of the TFT may be lowered.

In addition, the storage capacitor Cst further includes a storage hole H_st penetrating through the second gate insulating layer 132 to correspond to the storage lower electrode 122. The storage lower electrode 122 and the storage upper electrode 182 disposed between the gate insulating layer 131 and the passivation layer 170 are generated in the overlap region. That is, since the storage capacitor Cst is generated at an interval thinner than the conventional thickness by the thickness of the second gate insulating layer 132 removed by the storage hole H_st, the capacity compared to the same area may be higher than that of the conventional art.

Accordingly, the transistor array substrate according to the embodiment of the present invention may include a gate insulating layer 130 having a double layer structure including a nitride insulating material and an oxide insulating material, and a storage hole H_st passing through the second gate insulating film 132. As it includes, it is possible to prevent the parasitic capacitance of the thin film transistor TFT and increase the capacity of the storage capacitor Cst. In this case, since the capacity of the storage capacitor Cst is increased compared to the conventional area, the area of the storage capacitor Cst can be reduced, and thus the image quality can be improved as the pixel area becomes wider.

3, 4, 5, 6a to 6c, 7, 7, 8a, 9a to 9i, 10a to 10i, 11a to 11d, 12, 13a and 13b, and A method of manufacturing a transistor array substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 14A to 14D.

3 is a flowchart illustrating a method of manufacturing a transistor array substrate according to an embodiment of the present invention. 4 is a flow chart of the first embodiment showing "step of forming an active layer, an etch stopper and a storage hole" shown in FIG. 3, and FIG. 5 is a "active layer, an etch stopper and a storage hole shown in FIG. Is a flow chart of a second embodiment showing " Steps to Form a Form. &Quot; 6A to 6C, 7, 8, 9A to 9I, 10A to 10I, 11A to 10D, 12, 13A and 13B, and 14A to 14D are FIGS. In the method of manufacturing the transistor array substrate shown in Fig. 5, it is a process cross-sectional view showing I-I 'for each step.

As shown in FIG. 3, in the method of manufacturing a transistor array substrate according to an exemplary embodiment of the present invention, a first metal film on the substrate is patterned to form a gate line in the first direction, a gate electrode branched from the gate line, a gate line and a gate. Forming a common line in a first direction insulated from the electrode and a storage lower electrode which is a part of the common line (S100), and using a nitride based insulating material on the entire surface of the substrate, the gate line, the gate electrode, the common line, and the storage lower electrode; Forming a covering first gate insulating film (S200), forming a second gate insulating film with an oxide insulating material on an entire surface of the first gate insulating film (S300), and at least a portion of the gate electrode on the second gate insulating film A second gate insulating film corresponding to the active layer overlapping the portion of the active layer, an etch stopper on a portion of the active layer including the channel region, and a portion on the storage lower electrode. Forming a through-hole storage hole (S400), patterning a second metal layer on the second gate insulating layer, and defining a pixel region corresponding to each pixel together with the gate line to form a data line in a second direction perpendicular to the first direction A source electrode branched from the data line and in contact with one side on the active layer, a drain electrode spaced apart from the source electrode with a channel region interposed therebetween, and a drain electrode extending from the drain electrode and overlapping at least a portion of the storage lower electrode. And forming a storage extension electrode (S500).

Subsequently, forming a passivation layer covering the data line, the source electrode, the drain electrode, and the storage extension electrode on the entire surface of the second gate insulating layer (S600), and forming a contact hole penetrating the passivation layer corresponding to a portion of the storage extension electrode. Step S700, and patterning the third metal layer on the passivation layer to form a storage upper electrode extending from the pixel electrode and the pixel electrode of the pixel region and connected to the storage extension electrode through a contact hole, and overlapping the storage lower electrode. It further includes (S800).

As shown in FIG. 4, according to the first embodiment of the present invention, the forming of the active layer, the etch stopper and the storage hole (S400) forms the storage hole in the same mask process as the active layer.

That is, in the forming of the active layer, the etch stopper and the storage hole according to the first embodiment of the present invention (S400), sequentially forming the first material layer and the first photoresist layer on the entire surface of the second gate insulating film. In operation S410, the method may include forming a first pattern by patterning the first photoresist layer. In this case, the first pattern includes a hole passing through the first photoresist layer in a first region corresponding to a portion on the storage lower electrode, and a first photoresist having a first thickness in a second region corresponding to a portion on the gate electrode. And a first photoresist layer having a second thickness thinner than the first thickness in the remaining third regions except for the first and second regions.

Subsequently, a portion of the second gate insulating layer exposed to the hole in the first region is removed while the first pattern is used as a mask to form a storage hole (S412), and ashing treatment of the first pattern is performed. Removing the first photoresist layer in the first and third regions, and forming a second pattern including the first photoresist layer having a third thickness thinner than the first thickness in the second region ( S413), in the state using the second pattern as a mask, removing the first material layer to form an active layer with the first material layer remaining in the second region (S414), and remaining second on the active layer. Removing the pattern (S415), sequentially forming a second material layer and a second photoresist layer on the entire surface of the second gate insulating layer including the active layer and the storage hole (S416), and patterning the second photoresist layer. Channel area of the active layer Forming a third pattern including a second photoresist layer having a fourth thickness in a fourth region corresponding to the included portion (S417), and removing the second material layer while using the third pattern as a mask; Forming an etch stopper with the second material layer remaining in the fourth region (S418); and removing the third pattern remaining on the etch stopper (S419).

Alternatively, as shown in FIG. 5, according to the second embodiment of the present invention, the forming of the active layer, the etch stopper and the storage hole (S400) is performed by using the same mask process as the etch stopper instead of the active layer. Form.

That is, in the forming of the active layer, the etch stopper and the storage hole according to the first embodiment of the present invention (S400), sequentially forming the first material layer and the first photoresist layer on the entire surface of the second gate insulating film. (S420) patterning the first photoresist layer to form a fourth pattern including a first photoresist layer having a fifth thickness in a second region corresponding to a portion of the gate electrode (S421), and a fourth pattern. Using the mask as a mask, removing the first material layer to form an active layer with the first material layer remaining in the second region (S422), and removing the fourth pattern remaining on the active layer ( S423), forming a second material layer and a second photoresist layer on the entire surface of the second gate insulating layer including the active layer (S424), and patterning the second photoresist layer to form a fifth pattern (S425). ). In this case, the fifth pattern includes a hole penetrating through the second photoresist layer in a first region corresponding to a portion of the storage lower electrode, and a sixth thickness in a fourth region corresponding to a portion of the active layer including a channel region. And a second photoresist layer having a seventh thickness thinner than the sixth thickness in the remaining fifth regions except for the first and fourth regions.

Subsequently, a portion of the second gate insulating layer that is exposed to the holes in the first area is exposed while the fifth pattern is used as a mask to form a storage hole (S426), and ashing treatment to the fifth pattern. Removing the second photoresist layer in the first and fifth regions, and forming a sixth pattern including the second photoresist layer having an eighth thickness thinner than the sixth thickness in the fourth region ( S427), by using the sixth pattern as a mask, removing the second material layer to form an active layer with the second material layer remaining in the fourth region (S428), and the remaining agent on the etch stopper. 6, step S429 is removed.

Hereinafter, shown in FIGS. 6A to 6C, 7, 8, 9A to 9I, 10A to 10I, 11A to 10D, 12, 13A and 13B, and 14A to 14D. With reference to the process cross-sectional view, a method of manufacturing a transistor array substrate according to an embodiment of the present invention will be described in more detail.

As shown in FIG. 6A, the first metal film 120 is stacked on the entire surface of the substrate 110, and the first metal film pattern 211 is formed on the first metal film 120 by a first mask process. do. Next, as shown in FIG. 6B, the first metal film 120 is patterned using the first metal film pattern 211 as a mask. Accordingly, the gate line (not shown, corresponding to “GL” in FIG. 1), the gate electrode 121 branched from the gate line GL, and the common line insulated from the gate line GL and the gate electrode 121 (not shown) 1, and a storage lower electrode 122 formed as part of a common line (S100).

In this case, the first metal film 120 on the substrate 110 may be a single layer of at least one of Al, Cu, Mo, Nd, Ti, Pt, Ag, Nb, Cr, W, and Ta, or at least two or more layers, or May be selected as the alloy.

Thereafter, as illustrated in FIG. 6C, the first metal film pattern 211 of FIG. 6B remaining on the gate line GL, the common line CL, the gate line 121, and the storage lower electrode 122, respectively. ).

As illustrated in FIG. 7, a nitride-based insulating material is stacked on the entire surface of the substrate 110 to form a first gate insulating film 131 (S200). As a result, the gate line GL, the common line CL, the gate line 121, and the storage lower electrode 122 formed on the substrate 110 are covered with the first gate insulating layer 131 thereon.

The nitride-based insulating material has a composition including nitrogen (N) and is selected as an insulating material having a higher dielectric constant than the oxide-based insulating material, in particular, may be selected as silicon nitride (SiNx).

As shown in FIG. 8, an oxide-based insulating material is stacked on the entire surface of the first gate insulating film to form a second gate insulating film 132 (S300).

The oxide insulating material may be selected as an insulating material having a composition including oxygen (O) and capable of maintaining a stable composition ratio than the nitride based insulating material, in particular, silicon oxide (SiOx), more preferably SiO ₂ . .

As a result, the gate insulating layer 130 including the first and second gate insulating layers 131 and 132 is formed. In particular, the gate insulating film 130 according to the embodiment of the present invention is not limited to the double layer structure illustrated in FIG. 8, but the uppermost layer of the oxide-based insulating material (corresponding to the second gate insulating film 132 in FIG. 2). It may be formed of two or more layers, including.

Subsequently, on the second gate insulating layer 132, the active layer 141 overlapping at least a portion of the gate electrode, an etch stopper 151 on a portion including the channel region of the active layer, and a portion on the storage lower electrode. A storage hole H_st penetrating the second gate insulating layer is formed (S400).

In this case, according to the first embodiment of the present invention, as shown in FIG. 4, in the step of forming the active layer, the etch stopper and the storage hole (S400), the storage hole H_st corresponds to the active layer 141. It is formed by one mask process.

That is, as shown in FIG. 9A, the first material layer 140 and the first photoresist layer 220 are sequentially formed on the entire surface of the second gate insulating film 132 (S410).

In this case, the first material layer 140 is selected as an oxide semiconductor having higher charge mobility and stable electrostatic characteristics than silicon semiconductor. At this time, the oxide semiconductor is AxByCzO (x, y, z ≥ 0), wherein A, B and C are each selected from Zn, Cd, Ga, In, Sn, Hf and Zr. In particular, the oxide semiconductor may be any one of ZnO, InGaZnO ₄ , ZnInO, ZnSnO, InZnHfO, SnInO, and SnO.

The first photoresist layer 220 is selected as a photosensitive material which is a polymer material whose physical properties change with light in a specific wavelength region. The photosensitive material is classified into a positive type in which an area exposed to light is dissolved in a solvent and a negative type in which an area exposed to light is not dissolved in a solvent, the first type according to an embodiment of the present invention. The photoresist layer 220 may be selected as a negative photosensitive material.

As shown in FIG. 9B, light is selectively irradiated onto the first photoresist layer 220, developed, and patterned to form the first photoresist layer 220, thereby forming the first pattern 221. (S411).

In this case, the first pattern 221 includes a hole passing through the first photoresist layer in the first region P1 corresponding to the storage lower electrode 122, and the second pattern 221 corresponds to a portion of the gate electrode 121. A second thickness thinner than the first thickness TH1 in the third region P3 including the first photoresist layer having the first thickness TH1 in the region P2, except for the first and second regions. TH2) first photoresist layer.

Here, the forming of the first pattern 221 (S411) uses a halftone mask (not shown). For example, when the first photoresist layer 220 is a negative photosensitive material, the halftone mask may correspond to the shielding portion blocking the light corresponding to the first region P1 and the second region P2. The first transmission part may transmit light at a first transmittance and the second transmission part transmit light at a second transmittance lower than the first transmittance corresponding to the third region P3. By such a halftone mask, the amount of light may be differentially irradiated onto the first photoresist layer, so that a first pattern 221 divided into three regions may be formed.

However, the above description is merely an example of the step of forming the first pattern 221 by patterning the first photoresist layer 220 to include three regions, and thus embodiments of the present invention are not limited thereto. Of course not. For example, when the first photoresist layer 220 is a positive type, another halftone mask may be applied, and the patterning of the first photoresist layer 220 may be performed in other manners.

Next, as shown in FIG. 9C, a portion of the first material layer 140 exposed through the hole in the first region P1 and the second gate insulating film subsequent thereto, using the first pattern 221 as a mask. The storage hole H_st is formed by removing a portion of the portion 132 (S412).

At this time, in the formation of the storage hole (H_st) (S412), the etching of the second gate insulating layer 132 is a process that can be etched SiO ₂ with a high etching ratio, in particular, a wet etching process using an etchant of HF And, or may be carried out in a dry etching process using an etching gas of any one of SF ₆ + H ₂ and CF ₄ + H ₂ .

In addition, in the forming of the storage hole H_st (S412), the first material layer 140 and the second gate insulating layer 132 of the first region P1 may be collectively removed.

As illustrated in FIG. 9D, an ashing treatment is performed on the first pattern 221 of FIG. 9C to form a second pattern 252 (S413).

That is, through the ashing process, the thickness of the first pattern 221 is reduced as a whole, so that the first photoresist layer is removed from the first and third regions P1 and P3, so that the first region in the second region P2 is removed. The second pattern 222 including the first photoresist layer having a third thickness TH3 lower than the thickness is formed.

As shown in FIG. 9E, by using the second pattern 222 as a mask, the first material layer 140 exposed in the first and third regions P1 and P3 is removed to thereby remove the second region P2. The active layer 141 is formed of the remaining first material layer (S414), and as shown in FIG. 9F, the second pattern 222 remaining on the active layer 141 is removed (S415). .

Next, as shown in FIG. 9G, the second material layer 150 and the second photoresist layer 230 are disposed on the entire surface of the second gate insulating layer 132 including the active layer 141 and the storage hole H_st. Formed sequentially (S416).

In this case, the second material layer 150 is selected as a material having a relatively high etching ratio to the etching liquid or etching gas used in the step S500 for forming the source / drain electrodes. For example, the second material layer 150 may be selected from at least one inorganic material of SiOx, SiNx, SiOCx, and SiONx, or at least one of an organic material and a polymer organic material, and in particular, SiOx.

In addition, like the first photoresist layer 220, the second photoresist layer 230 is selected as a photosensitive material, which is a polymer material whose physical properties change with light in a specific wavelength region.

As shown in FIG. 9H, light is selectively irradiated onto the second photoresist layer 230, developed, and patterned to form the second photoresist layer 230, thereby forming a channel region of the active layer 141. A third pattern 231 including a second photoresist layer having a fourth thickness TH4 is formed in the corresponding portion of the fourth region P4 (S417). In the state where the third pattern 231 is used as a mask, the second material layer 150 exposed in the remaining regions other than the fourth region P4 is removed, thereby remaining second in the fourth region P4. An etch stopper 151 is formed of a material layer (S418).

Thereafter, as shown in FIG. 9I, the third pattern (231 of FIG. 9H) remaining on the etch stopper 151 is removed (S419).

Alternatively, according to the second embodiment of the present invention, as shown in FIG. 5, in the step S400 of forming the active layer, the etch stopper and the storage hole, the storage hole H_st is formed in the etch stopper rather than the active layer. It is formed by a corresponding mask process.

That is, as shown in FIG. 10A, the first material layer 140 and the first photoresist layer 220 are sequentially formed on the entire surface of the second gate insulating film 132 (S420).

As shown in FIG. 10B, light is selectively irradiated onto the first photoresist layer 220 and developed to pattern the first photoresist layer 220. As a result, a fourth pattern 223 including the first photoresist layer having the fifth thickness TH5 is formed in the second region P2 corresponding to a portion of the gate electrode 121 (S421). In the state where the fourth pattern 223 is used as a mask, the first material layer 140 exposed in the remaining regions other than the second region P2 is removed, thereby remaining the first region remaining in the second region P2. The active layer 141 is formed of a material layer (S422).

Thereafter, as shown in FIG. 10C, the fourth pattern (223 of FIG. 10B) remaining on the active layer 141 is removed (S423).

Next, as shown in FIG. 10D, the second material layer 150 and the second photoresist layer 230 are sequentially formed on the entire surface of the second gate insulating film 132 including the active layer 141 (S424). ).

As shown in FIG. 10E, light is selectively irradiated onto the second photoresist layer 230, and then developed, thereby patterning the second photoresist layer 230 to form a fifth pattern 232. (S425).

In this case, the fifth pattern 232 includes a hole passing through the second photoresist layer in the first region P1 corresponding to the storage lower electrode 122, and includes a portion of the active layer 141 including the channel region. A second photoresist layer having a sixth thickness TH6 is included in the fourth region P4 corresponding to, and is larger than the sixth thickness TH6 in the remaining fifth regions P5 except for the first and fourth regions. A second photoresist layer having a thin seventh thickness TH7 is included.

Here, the forming of the fifth pattern 232 (S425) uses a halftone mask (not shown). For example, when the second photoresist layer 230 is a negative photosensitive material, the halftone mask may correspond to the shielding portion blocking the light corresponding to the first region P1 and the fourth region P4. The first transmission part may transmit light at a first transmittance and the second transmission part may transmit light at a second transmittance lower than the first transmittance corresponding to the fifth region P5. By the halftone mask, the second photoresist layer may be differentially irradiated with a light amount, so that a fifth pattern 232 divided into three regions may be formed.

However, since the above description merely illustrates an example of forming the sixth pattern 232 by patterning the second photoresist layer 230 to include three regions, the embodiment of the present invention is not limited thereto. Of course not.

Next, as shown in FIG. 10F, a portion of the second material layer 150 exposed through the hole in the first region P1 and the second gate insulating film subsequent thereto, using the fifth pattern 232 as a mask. The storage hole H_st is formed by removing a portion of the portion 132 (S426).

In this case, the forming of the storage hole H_st (S426) may be performed by collectively removing the second material layer 150 and the second gate insulating layer 132 in the first region P1 using a wet etching process. Can be.

As shown in FIG. 10G, the fifth pattern (232 of FIG. 10F) is subjected to ashing treatment to form a sixth pattern 233 (S413).

That is, through the ashing process, the thickness of the fifth pattern 232 is reduced as a whole, so that the second photoresist layer is removed from the first and fifth regions P1 and P5, so that the sixth region in the fourth region P4 may be reduced. A sixth pattern 233 including a second photoresist layer having an eighth thickness TH8 that is lower than the thickness TH6 is formed.

As shown in FIG. 10H, the fourth region P4 is removed by removing the second material layer 150 exposed in the first and fifth regions P1 and P5 using the sixth pattern 233 as a mask. The etch stopper 151 is formed of the remaining second layer of material (S428), and as shown in FIG. 10I, the sixth pattern 233 remaining on the etch stopper 151 is removed (S429). .

Referring to FIG. 3 again, as shown in FIG. 11A, a second metal film (or a second metal film) is formed on the entire surface of the second gate insulating film 132 including the active layer 141, the etch stopper 151, and the storage hole H_st. 160 is formed, and as shown in FIG. 11B, a second metal film pattern 241 is formed on the second metal film 160. As shown in FIG. 11C, the second metal film 160 is patterned using the second metal film pattern 241 as a mask to extend the source electrode 161, the drain electrode 162, and the storage. The electrode 163 is formed. (S500)

In this case, the source electrode 161 and the drain electrode 162 are spaced apart from each other with the channel region interposed therebetween, and disposed on both sides of the active layer 141. Accordingly, the upper surface of the active layer 141 is covered by both the etch stopper 151 and the source / drain electrodes 161 and 162.

The storage extension electrode 163 is connected to the drain electrode 162 and at least partially overlaps the storage lower electrode 122 with the second gate insulating layer 132 interposed therebetween.

In addition, like the first metal film 120, the second metal film 160 on the gate insulating film 130 may have at least one of Al, Cu, Mo, Nd, Ti, Pt, Ag, Nb, Cr, W, and Ta. It may be selected as one single layer, or at least two or more layers or alloys.

Thereafter, as shown in FIG. 11D, the second metal film pattern 241 of FIG. 11C remaining on the source / drain electrodes 161 and 162 and the storage extension electrode 163 is removed.

In this case, a thin film transistor TFT including the gate electrode 121, the active layer 141, the etch stopper 151, and the source / drain electrodes 161 and 162 is formed.

Next, as shown in FIG. 12, the passivation layer 170 is formed on the entire surface of the second gate insulating layer 132 (S600). In this case, the thin film transistor TFT and the storage extension electrode 163 formed on the gate insulating layer 130 are covered with the passivation layer 170.

As shown in FIG. 13A, the photoresist on the passivation layer 170 is patterned to form a hole pattern 251 including corresponding holes on a portion of the storage extension electrode 163 adjacent to the pixel area, and the hole pattern is formed. In a state in which 251 is used as a mask, a portion of the exposed passivation layer 170 is removed to form a contact hole H_PE (S700).

Thereafter, as shown in FIG. 13B, the hole pattern (251 of FIG. 13A) remaining on the passivation layer 170 including the contact hole H_PE is removed.

As shown in FIG. 14A, a third metal film 180 is formed on the entire surface of the protective film 170 including the contact hole H_PE, and as shown in FIG. 14B, a photo on the third metal film 180 is formed. The resist layer is patterned to form a third metal film pattern 261 corresponding to the pixel region including the contact hole H_PE. As shown in FIG. 14C, the third metal film 180 is patterned using the third metal film pattern 241 as a mask to form the pixel electrode 181 and the storage upper electrode 182. (S800).

In this case, the pixel electrode 181 is formed in the pixel area on the passivation layer 170, and the storage upper electrode 182 extends from the pixel electrode 181 to extend the passivation layer 170 and the first gate insulating layer through the storage hole H_st. At least a portion of the lower electrode 122 overlaps the storage lower electrode 122 with the 130 interposed therebetween.

Thereafter, as shown in FIG. 14D, the third metal film pattern 261 of FIG. 14C remaining on the pixel electrode 181 and the storage upper electrode 182 is removed.

As described above, according to the first and second embodiments of the present invention, the forming of the storage hole H_st is not performed in a separate mask process, but rather, the formation of the active layer 141 or the etch stopper 151 is performed. Since it is carried out together in the mask process, it is possible to prevent the increase in the number of mask process, it is possible to reduce the process time and manufacturing cost.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes may be made without departing from the technical spirit of the present invention.

GL: Gate Line CL: Common Line
DL: data line TFT: thin film transistor
Cst: storage capacitor PE, 181: pixel electrode
121: gate electrode 122: storage lower electrode
130: gate insulating film 131: first gate insulating film
132: second gate insulating film H_st: storage hole
141: active layer 151: etch stopper
161: source electrode 162: drain electrode
163: storage extension electrode 170: protective film
H_PE: contact hole 182: upper storage electrode

Claims

Board;
A gate line in a first direction formed on the substrate;
A common line formed on the substrate and insulated from the gate line;
A storage lower electrode formed as part of the common line;
A first gate insulating layer formed of a nitride based insulating material on an entire surface of the substrate to cover the gate line, the common line, and the storage lower electrode;
A second gate insulating film formed of an oxide insulating material on an entire surface of the first gate insulating film;
A storage hole penetrating the second gate insulating layer corresponding to the storage lower electrode;
A data line in a second direction perpendicular to the first direction on the second gate insulating film to define a pixel area corresponding to each pixel together with the gate line;
A thin film transistor connected to the gate line and the data line;
A passivation layer formed on an entire surface of the second gate insulating layer to cover the second data line and the thin film transistor;
A pixel electrode formed in the pixel area on the passivation layer; And
And a storage upper electrode formed on the passivation layer and extending from the pixel electrode, and at least partially overlapping the storage lower electrode with the passivation layer and the first gate insulating layer therebetween through the storage hole.

The method of claim 1,
The thin film transistor is
A gate electrode formed on the substrate and branched from the gate line;
An active layer formed of an oxide semiconductor on the second gate insulating layer, overlapping at least a portion of the gate electrode, and including a channel region;
An etch stopper formed on a portion of the active layer including the channel region;
A source electrode branched from the data line on the second gate insulating layer and formed to be in contact with one side of the active layer; And
And a drain electrode on the second gate insulating layer, the drain electrode being spaced apart from the source electrode with the channel region therebetween and in contact with the other side of the active layer.

The method of claim 2,
A storage extension electrode extending from the drain electrode and at least partially overlapping each of the storage lower electrode and the storage upper electrode with the first gate insulating layer therebetween through the storage hole;
A contact hole penetrating through the passivation layer corresponding to a portion of the storage extension electrode;
The storage upper electrode is connected to the storage extension electrode through the contact hole,
And the pixel electrode connected to the storage upper electrode is connected to the drain electrode connected to the storage extension electrode.

The method of claim 2,
The oxide semiconductor is AxByCzO (x, y, z ≥ 0), and each of A, B, and C is selected from Zn, Cd, Ga, In, Sn, Hf, and Zr.

5. The method of claim 4,
The oxide semiconductor is any one of ZnO, InGaZnO ₄ , ZnInO, ZnSnO, InZnHfO, SnInO and SnO.

5. The method of claim 4,
The protective layer is a transistor array substrate selected from an oxide-based insulating material.

Patterning a first metal layer on the substrate to form a gate line in a first direction, a gate electrode branched from the gate line, a common line in a first direction insulated from the gate line and the gate electrode, and a lower portion of the common line Forming an electrode;
Forming a first gate insulating film on the entire surface of the substrate, the nitride insulating material covering the gate line, the common line, the gate electrode, and the storage lower electrode;
Forming a second gate insulating film on an entire surface of the first gate insulating film by using an oxide insulating material;
An active layer overlapping at least a portion of the gate electrode on the second gate insulating layer, an etch stopper on a portion including a channel region of the active layer, and a portion of the storage lower electrode penetrating through the second gate insulating layer; Forming a storage hole;
Patterning a second metal layer on the second gate insulating layer to define a pixel region corresponding to each pixel together with the gate line; a data line in a second direction perpendicular to the first direction; A source electrode in contact with one side on the layer, a drain electrode in contact with the other side on the active layer spaced apart from the source electrode with the channel region therebetween, and an extension of the drain electrode to extend the first gate insulating layer through the storage hole. Forming a storage extension electrode overlapping at least a portion of the storage lower electrode in between;
Forming a passivation layer on an entire surface of the second gate insulating layer to cover the data line, the source electrode, the drain electrode, and the storage extension electrode;
Forming a contact hole penetrating the passivation layer corresponding to a portion of the storage extension electrode;
The third metal layer on the passivation layer is patterned to extend the pixel electrode of the pixel region and the pixel electrode and to be connected to the storage extension electrode through the contact hole, and to pass through the storage hole to the passivation layer and the first gate insulating layer. Forming a storage upper electrode at least partially overlapping the storage lower electrode in between.

The method of claim 7, wherein
Forming the active layer, the etch stopper and the storage hole
Sequentially forming a first material layer and a first photoresist layer on the entire surface of the second gate insulating film;
Patterning the first photoresist layer to include a hole penetrating through the first photoresist layer in a first region corresponding to a portion on the storage lower electrode, and in a second region corresponding to a portion on the gate electrode. A first pattern including a first photoresist layer having a thickness of one, and including a first photoresist layer having a second thickness that is thinner than the first thickness in the remaining third regions except for the first and second regions; Making;
Forming a storage hole by removing a portion of the second gate insulating layer that is connected to the hole in the first region while using the first pattern as a mask;
An ashing treatment is performed on the first pattern to remove the first photoresist layer in the first and third regions, and a first thickness of a third thickness thinner than the first thickness in the second region. Forming a second pattern comprising a photoresist layer;
Removing the first material layer while using the second pattern as a mask to form the active layer with the first material layer remaining in the second region;
Removing the second pattern remaining on the active layer;
Sequentially forming a second material layer and a second photoresist layer on an entire surface of the second gate insulating layer including the active layer and the storage hole;
Patterning the second photoresist layer to form a third pattern including a second photoresist layer having a fourth thickness in a fourth region corresponding to a portion of the active layer including a channel region;
Removing the second material layer while using the third pattern as a mask to form the etch stopper with a second material layer remaining in the fourth region; And
Removing the third pattern remaining on the etch stopper.

The method of claim 7, wherein
Forming the active layer, the etch stopper and the storage hole
Sequentially forming a first material layer and a first photoresist layer on the entire surface of the second gate insulating film;
Patterning the first photoresist layer to form a first pattern including a first photoresist layer having a first thickness in a first region corresponding to a portion of the gate electrode;
Removing the first material layer while using the first pattern as a mask to form the active layer with the first material layer remaining in the first region;
Removing the first pattern remaining on the active layer;
Sequentially forming a second material layer and a second photoresist layer on the entire surface of the second gate insulating layer including the active layer;
Patterning the second photoresist layer, the second photoresist layer including a hole passing through the second photoresist layer in a second region corresponding to a portion of the storage lower electrode, and corresponding to a portion of the active layer including a channel region; A second photoresist layer having a second thickness in three regions, and including a second photoresist layer having a third thickness thinner than the second thickness in the remaining fourth regions except for the second and third regions. Forming a pattern;
Forming a storage hole by removing a portion of the second gate insulating layer that is connected to the hole in the second region while using the second pattern as a mask;
An ashing treatment is performed on the second pattern to remove the second photoresist layer in the second and fourth regions, and a second thickness having a fourth thickness lower than the second thickness in the third region. Forming a third pattern comprising a photoresist layer;
Removing the second material layer while using the third pattern as a mask to form the etch stopper with the second material layer remaining in the third region;
Removing the third pattern remaining on the etch stopper.

10. The method according to claim 8 or 9,
Forming the active layer, the etch stopper and the storage hole
A shield for blocking light corresponding to the first region, a first transmitting portion transmitting light at a first transmittance corresponding to the second region, and a second transmittance lower than the first transmittance corresponding to the third region A method of manufacturing a transistor array substrate using a halftone mask comprising a second transmission portion through which light is transmitted.

10. The method according to claim 8 or 9,
In the forming of the first material layer and the first photoresist layer,
The first material layer is an oxide semiconductor of AxByCzO (x, y, z ≥ 0), and each of A, B, and C is Zn, Cd, Ga, In, Sn, Hf, and Zr. Way.

The method of claim 11,
And the first material layer is selected from ZnO, InGaZnO ₄ , ZnInO, ZnSnO, InZnHfO, SnInO, and SnO.

10. The method according to claim 8 or 9,
In the forming of the second material layer and the second photoresist layer,
And the second material layer is selected from an oxide-based insulating material.

The method of claim 7, wherein
And forming the passivation layer, wherein the passivation layer is selected from an oxide insulating material.