KR20130000361A - 공통 컬럼 멀티플렉서 및 감지 증폭기 하드웨어를 구비하는 랜덤 액세스 메모리 제어기 - Google Patents

공통 컬럼 멀티플렉서 및 감지 증폭기 하드웨어를 구비하는 랜덤 액세스 메모리 제어기 Download PDF

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Publication number
KR20130000361A
KR20130000361A KR1020120067616A KR20120067616A KR20130000361A KR 20130000361 A KR20130000361 A KR 20130000361A KR 1020120067616 A KR1020120067616 A KR 1020120067616A KR 20120067616 A KR20120067616 A KR 20120067616A KR 20130000361 A KR20130000361 A KR 20130000361A
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KR
South Korea
Prior art keywords
sense amplifier
column
data
common
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
KR1020120067616A
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English (en)
Korean (ko)
Inventor
메니 야니
Original Assignee
마벨 이스라엘 (엠.아이.에스.엘) 리미티드
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Application filed by 마벨 이스라엘 (엠.아이.에스.엘) 리미티드 filed Critical 마벨 이스라엘 (엠.아이.에스.엘) 리미티드
Publication of KR20130000361A publication Critical patent/KR20130000361A/ko
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/065—Differential amplifiers of latching type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)
KR1020120067616A 2011-06-22 2012-06-22 공통 컬럼 멀티플렉서 및 감지 증폭기 하드웨어를 구비하는 랜덤 액세스 메모리 제어기 Ceased KR20130000361A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161499959P 2011-06-22 2011-06-22
US61/499,959 2011-06-22

Publications (1)

Publication Number Publication Date
KR20130000361A true KR20130000361A (ko) 2013-01-02

Family

ID=47361722

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020120067616A Ceased KR20130000361A (ko) 2011-06-22 2012-06-22 공통 컬럼 멀티플렉서 및 감지 증폭기 하드웨어를 구비하는 랜덤 액세스 메모리 제어기

Country Status (3)

Country Link
US (1) US8913420B2 (cg-RX-API-DMAC10.html)
JP (1) JP2013041657A (cg-RX-API-DMAC10.html)
KR (1) KR20130000361A (cg-RX-API-DMAC10.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11011238B2 (en) * 2018-06-28 2021-05-18 Taiwan Semiconductor Manufacturing Company, Ltd. Floating data line circuits and methods
US10705984B1 (en) * 2018-09-26 2020-07-07 Cadence Design Systems, Inc. High-speed low VT drift receiver
US10978139B2 (en) 2019-06-04 2021-04-13 Qualcomm Incorporated Dual-mode high-bandwidth SRAM with self-timed clock circuit
US12159664B2 (en) * 2019-10-14 2024-12-03 Arm Limited Concurrent memory access operations

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60136991A (ja) * 1983-12-26 1985-07-20 Matsushita Electric Ind Co Ltd 半導体メモリ
JP3112117B2 (ja) * 1992-04-17 2000-11-27 松下電器産業株式会社 差動伝送回路
JP3560266B2 (ja) * 1995-08-31 2004-09-02 株式会社ルネサステクノロジ 半導体装置及び半導体データ装置
JPH1166858A (ja) * 1997-08-12 1999-03-09 Mitsubishi Electric Corp 半導体記憶装置
JP2002230980A (ja) * 2001-01-31 2002-08-16 Mitsubishi Electric Corp 半導体記憶装置
US6456521B1 (en) * 2001-03-21 2002-09-24 International Business Machines Corporation Hierarchical bitline DRAM architecture system
US6631093B2 (en) * 2001-06-29 2003-10-07 Intel Corporation Low power precharge scheme for memory bit lines
US6707707B2 (en) * 2001-12-21 2004-03-16 Micron Technology, Inc. SRAM power-up system and method
US6925025B2 (en) * 2003-11-05 2005-08-02 Texas Instruments Incorporated SRAM device and a method of powering-down the same
US8027218B2 (en) * 2006-10-13 2011-09-27 Marvell World Trade Ltd. Processor instruction cache with dual-read modes
JP5178182B2 (ja) * 2007-12-25 2013-04-10 株式会社東芝 半導体記憶装置
US7843725B2 (en) * 2008-06-11 2010-11-30 Micron Technology, Inc. M+L bit read column architecture for M bit memory cells
US20110149667A1 (en) * 2009-12-23 2011-06-23 Fatih Hamzaoglu Reduced area memory array by using sense amplifier as write driver

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Publication number Publication date
JP2013041657A (ja) 2013-02-28
US20120327703A1 (en) 2012-12-27
US8913420B2 (en) 2014-12-16

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