KR20120126723A - Semiconductor device and method for forming the same - Google Patents

Semiconductor device and method for forming the same Download PDF

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Publication number
KR20120126723A
KR20120126723A KR1020110044741A KR20110044741A KR20120126723A KR 20120126723 A KR20120126723 A KR 20120126723A KR 1020110044741 A KR1020110044741 A KR 1020110044741A KR 20110044741 A KR20110044741 A KR 20110044741A KR 20120126723 A KR20120126723 A KR 20120126723A
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KR
South Korea
Prior art keywords
die
insulating film
silicon vias
substrate
forming
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KR1020110044741A
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Korean (ko)
Inventor
이동렬
Original Assignee
에스케이하이닉스 주식회사
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Priority to KR1020110044741A priority Critical patent/KR20120126723A/en
Publication of KR20120126723A publication Critical patent/KR20120126723A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/073—Apertured devices mounted on one or more rods passed through the apertures

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A semiconductor device and a method for forming the same are provided to prevent reliability reduction of a penetration silicone via due to mechanical thermal stress by omitting a bump or a solder ball for laminating a die. CONSTITUTION: A first die(50a) is formed on a substrate(100). A first insulating layer(40) is formed on the sidewall of the first die and the substrate. A second die(50b) is formed on the upper side of the first insulating layer. A second insulating layer(60) is formed on the sidewall of the second die. A third die(50c) is formed on the upper side of the second insulating layer. A penetration silicone via(30) is formed on the end of the first die, the second die, and the third die.

Description

Semiconductor device and method for forming the same

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device including a through silicon via and a method for forming the same.

Three-dimensional lamination technology among packaging technologies of semiconductor integrated circuits has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance. A plurality of stacked packages, which are commonly referred to as stack chip packages.

The technology of the multilayer chip package can reduce the manufacturing cost of the package by a simplified process, and also has advantages such as mass production, while insufficient wiring space for the electrical connection inside the package according to the increase in the number and size of the stacked chips. The disadvantage is that.

That is, the existing laminated chip package is manufactured in a structure in which a plurality of chips are attached to the chip attaching region of the substrate so as to be electrically connected between the bonding pads of the chips and the conductive circuit patterns of the substrate so as to be electrically energized. Space is needed for the circuit pattern area of the substrate to which the wire is connected, and thus the size of the semiconductor package is increased.

In view of this, a structure using a through silicon via (TSV) has been proposed as an example of a stack package. The through silicon via is formed in a chip, and the physical and electrical inter-chips are vertically formed by the through silicon via. The structure is such that the connection is made, and the conventional through-silicon via and the chip stacking method using the same are briefly described as follows.

First, holes are formed in adjacent portions of the bonding pads of each chip of the wafer, and conductive silicon is embedded in the holes to form through silicon vias. The backside of the wafer is then back ground to expose the through silicon vias. Subsequently, the wafer is sawed and separated into individual chips, and then at least two or more chips are stacked and stacked vertically on the substrate for signal exchange through the through silicon vias.

More specifically, in the electrical connection structure between the upper chip and the lower chip stacked on each other, the metal exposed to the bottom through the through silicon via of the upper chip and the metal exposed to the top through the through silicon via of the lower chip are conductive. The bumps are electrically connected to each other.

Subsequently, the stacked upper and lower chips are mounted on a substrate, wire bonding is performed between the substrate and the upper chip, molded with a molding compound resin, and solder balls are mounted on the lower surface of the substrate to complete the stack package. However, as the lamination thickness of the wafer increases, mechanical and thermal stresses increase, so that there is a limit in that a problem of electrical insulation occurs.

The present invention is to solve the problem of electrical insulation by increasing the mechanical and thermal stress as the stack thickness of the wafer increases.

The semiconductor device of the present invention includes a first die provided on a substrate, a sidewall of the first die, a first insulating film provided on the substrate, a second die provided on the first insulating film, and a second die A second insulating film provided on the sidewall and provided on the first die, a third die provided on the second insulating film, and a through hole provided at ends of the first die, the second die, and the third die, respectively. And silicon vias.

The first die, the second die, and the third die are electrically connected by the through silicon vias.

In addition, the through silicon via may have a shape stacked in a zigzag form.

The height of the first insulating layer is lower than that of the first die, and the height of the second insulating layer is lower than the second die.

A method of forming a semiconductor device of the present invention includes forming a first die on a substrate, forming a first insulating film on the sidewalls of the first die and the substrate, and forming a second die on the first insulating film. Forming a second insulating film on the sidewalls of the second die and the first die, and forming a third die on the second insulating film, wherein the first die, End portions of the second die and the third die are provided with through silicon vias, respectively.

The first die, the second die, and the third die are electrically connected by the through silicon vias.

In addition, the through silicon via may have a shape stacked in a zigzag form.

The height of the first insulating layer is lower than that of the first die, and the height of the second insulating layer is lower than the second die.

The present invention improves the reliability of the silicon via by connecting the sidewalls of the through silicon via while the dies are stacked, and provides the effect of providing a large-capacity semiconductor device by stacking the stack in a larger stack structure.

1 is a plan view of a plurality of die including through silicon vias in accordance with the present invention;
2 is a plan view of one die including through silicon vias cut in accordance with the present invention.
3 is a cross-sectional view of a semiconductor device including through silicon vias in accordance with the present invention.
4A to 4E are cross-sectional views illustrating a method of forming a semiconductor device including through silicon vias according to the present invention.

Hereinafter, with reference to the accompanying drawings in accordance with an embodiment of the present invention will be described in detail.

1 is a plan view of a plurality of die including through silicon vias in accordance with the present invention. Referring to FIG. 1, a plurality of dies 20 provided on the wafer 10 and through silicon vias 30 provided at both ends of the plurality of dies 20 are illustrated. In this case, the through silicon via 30 is preferably provided on a cutting line (shown in dashed lines) provided to separate the plurality of dies into one die. Although not shown, it is preferable that a plurality of transistors and a plurality of storage units for forming a semiconductor device are integrated in the die 20.

Figure 2 is a plan view of one die including through silicon vias cut in accordance with the present invention. Referring to FIG. 2, one die 50 is shown after being cut from multiple dies provided on top of the wafer 10. At this time, since the through silicon via 30 is provided on the cutting line of the die 20, the through silicon via 30 is cut together while the die 20 is cut. Accordingly, sidewalls of the through silicon vias 30 are exposed at both ends of one die 50. At this time, the region where the through silicon via 30 is cut and removed is preferably 1/4 of the total area of the through silicon via 30.

3 is a cross-sectional view illustrating a semiconductor device including a through silicon via according to the present invention. The semiconductor device according to the present invention includes a substrate 100, a first die 50a stacked on the substrate 100, and a first die provided on the sidewall of the first die 50a and provided on the substrate 100. The insulating film 40, the second die 50b provided on the first insulating film 40, and the second insulating film 60 provided on the sidewall of the second die 50b and provided on the first die 50a. And a third die 50c provided on the second insulating film 60.

Here, it is preferable that both ends of the first die 50a, the second die 50b, and the third die 50c are provided to expose the through silicon vias 30. The through silicon via 30 of the second die 50b is connected to the upper sidewall of the through silicon via 30 of the first die 50a and the upper sidewall of the through silicon via 30 of the second die 50b is connected to the upper sidewall. The through silicon via 30 of the third die 50c is connected. That is, as the first die 50a, the second die 50b, and the third die 50c are stacked, the through silicon vias 30 have a zigzag stacked shape. It is preferable that the thickness of the first insulating film 40 is 3/4 of the first die 50a, and the thickness of the second insulating film 60 is preferably 1/2 of the second die 50b.

The present invention can be easily stacked without the configuration of bumps and solder balls because the through silicon vias provided at the end of the die are electrically connected while being stacked in a zigzag while dies are stacked as described above. This prevents the degradation of the through-silicon vias caused by bumps and solder balls, and can be stacked in more layers for greater integration.

The formation method of the semiconductor element of this invention which has the structure mentioned above is as follows. 4A to 4E are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

As shown in FIG. 4A, the first die 50a is stacked on the substrate 100. Here, it is preferable that the first die 50a has the shape of a die as shown in FIG. See FIG. 2 for a detailed description. Here, both ends of the first die 50a may be provided so that the through silicon vias 30 are exposed. However, in this drawing, the through silicon vias 30 are exposed only at one end thereof.

As shown in FIG. 4B, after depositing the first insulating layer 40 on the substrate 100 including the first die 50a, the surface is planarized by performing a planarization etching process.

As shown in FIG. 4C, after etching the first insulating film 40 so that the surface of the first die 50a is exposed, an additional etching process may be performed to have a thickness lower than that of the first die 50a, so that the first insulating film ( Etch 40). At this time, the first insulating film 40 preferably has a thickness of 3/4 of the thickness of the first die 50a. Subsequently, a second die 50b is laminated on the first insulating film 40. At this time, both ends of the second die 50b may be provided so that the through silicon vias 30 are exposed, but in this drawing, the through silicon vias 30 are exposed only at the other end.

The second die 50b is preferably stacked over the first insulating film 40 so that the through silicon vias 30 of the second die 50b are connected to the through silicon vias 30 of the first die 50a. . This can omit configurations such as bumps and solder balls, which are required in the prior art for stacking dies, thereby preventing poor reliability of through silicon vias due to mechanical thermal stress.

As shown in FIG. 4D, after depositing the second insulating layer 60 on the first die 50a and the second die 50b, the surface is planarized by performing a planarization etching process.

As shown in FIG. 4E, the second insulating film 60 is etched to expose the surface of the second die 50b and then an additional etching process is performed to have a thickness lower than that of the second die 50a. The insulating film 60 is etched. At this time, the second insulating film 60 preferably has a thickness of 1/2 of the second die 50b. Subsequently, a third die 50c is laminated on the second insulating film 60. At this time, both ends of the third die 50c may be provided so that the through silicon vias 30 are exposed. However, in this drawing, the through silicon vias 30 are exposed only at one end thereof.

The third die 50c is preferably stacked on the second insulating film 60 so that the through silicon vias 30 of the third die 50c are connected to the through silicon vias 30 of the second die 50b. . This makes it possible to omit configurations such as bumps and solder balls, which are required in the prior art for stacking dies, thereby preventing poor reliability of through silicon vias due to mechanical thermal stress.

In the present invention, a plurality of dies are spaced apart by an insulating film on a substrate and electrically connected by through silicon vias provided at the ends of the dies. In this case, the through silicon vias are spaced apart by an insulating layer and are provided at end portions of the stacked dies, and thus have a zigzag stacked shape. Since the through-silicon vias are zigzag, stacked, and electrically connected, configuration such as bumps and solder balls can be omitted, thereby preventing poor reliability of the through-silicon vias.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Of the present invention.

Claims (8)

A first die provided on the substrate;
A first insulating film provided on the sidewall of the first die and the substrate;
A second die provided on the first insulating layer;
A second insulating film provided on sidewalls of the second die and provided on the first die;
A third die provided on the second insulating layer;
And through-silicon vias provided at end portions of the first die, the second die, and the third die, respectively. The method according to claim 1,
And wherein the first die, the second die and the third die are electrically connected by the through silicon vias. The method according to claim 1,
The through silicon via has a zigzag stacked shape. The method according to claim 1,
The height of the first insulating film is lower than the first die, the height of the second insulating film is a semiconductor device, characterized in that lower than the second die. Forming a first die on the substrate;
Forming a first insulating film on sidewalls of the first die and on the substrate;
Forming a second die on the first insulating film;
Forming a second insulating film on sidewalls of the second die and on the first die; And
Forming a third die on the second insulating layer,
A through silicon via is formed in each of the end portions of the first die, the second die and the third die. The method according to claim 5,
And wherein the first die, the second die, and the third die are electrically connected by the through silicon vias. The method according to claim 5,
The through silicon via has a zigzag stacked shape. The method according to claim 5,
And the height of the first insulating film is lower than that of the first die, and the height of the second insulating film is lower than the second die.
KR1020110044741A 2011-05-12 2011-05-12 Semiconductor device and method for forming the same KR20120126723A (en)

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KR1020110044741A KR20120126723A (en) 2011-05-12 2011-05-12 Semiconductor device and method for forming the same

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Application Number Priority Date Filing Date Title
KR1020110044741A KR20120126723A (en) 2011-05-12 2011-05-12 Semiconductor device and method for forming the same

Publications (1)

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KR20120126723A true KR20120126723A (en) 2012-11-21

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