KR20110135077A - Method for forming semiconductor device - Google Patents

Method for forming semiconductor device Download PDF

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Publication number
KR20110135077A
KR20110135077A KR1020100054800A KR20100054800A KR20110135077A KR 20110135077 A KR20110135077 A KR 20110135077A KR 1020100054800 A KR1020100054800 A KR 1020100054800A KR 20100054800 A KR20100054800 A KR 20100054800A KR 20110135077 A KR20110135077 A KR 20110135077A
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KR
South Korea
Prior art keywords
forming
insulating film
interlayer insulating
layer
trench
Prior art date
Application number
KR1020100054800A
Other languages
Korean (ko)
Inventor
김재운
Original Assignee
주식회사 하이닉스반도체
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Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100054800A priority Critical patent/KR20110135077A/en
Publication of KR20110135077A publication Critical patent/KR20110135077A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for forming a semiconductor device is provided to improve the reliability of a semiconductor device by forming a metal wire after forming a penetration silicon via and reducing a failure which is generated in a semiconductor device. CONSTITUTION: In a method for forming a semiconductor device, a first interlayer insulating film(102) and an etch stopper film are formed in a semiconductor substrate(100). A first trench is formed by etching an etch stopping layer and the first interlayer insulating film through a mask pattern as a mask. A spacer insulating film(108) is formed in the first trench surface and the etch stopping layer. The conductive layer is formed in the spacer insulating film and the top side of the first interlayer insulating film.

Description

Method for forming semiconductor device

The present invention relates to a method for forming a semiconductor device, and more particularly, to a method for forming a semiconductor device including through silicon vias.

Three-dimensional lamination technology among packaging technologies of semiconductor integrated circuits has been developed with the goal of reducing the size of electronic devices, increasing the mounting density and improving the performance, and the three-dimensional lamination package has a plurality of chips having the same storage capacity. This is a stacked package, which is commonly referred to as a stacked chip package.

The technology of the multilayer chip package can reduce the manufacturing cost of the package by a simplified process, and also has advantages such as mass production, while lacking wiring space for the electrical connection inside the package due to the increase in the number and size of the stacked chips. The disadvantage is that.

That is, the conventional laminated chip package is manufactured in a structure in which a plurality of chips are attached to the chip attaching region of the substrate, so that the bonding pads of the chips and the conductive circuit patterns of the substrate are electrically connected to each other by wire, so that the wire bonding is possible. Space is needed for the circuit pattern area of the substrate to which the wire is connected, and thus the size of the semiconductor package is increased.

In view of this, a structure using a through silicon via (TSV) has been proposed as an example of a stack package. The through silicon via is formed in a chip, and the physical and electrical inter-chips are vertically formed by the through silicon via. The structure is such that the connection is made, and the conventional through-silicon via and the chip stacking method using the same are briefly described as follows.

First, holes are formed in adjacent portions of the bonding pads of each chip of the wafer, and conductive silicon is embedded in the holes to form through silicon vias. The backside of the wafer is then back ground to expose the through silicon vias. Subsequently, the wafer is sawed and separated into individual chips, and then at least two or more chips are stacked and stacked vertically on the substrate for signal exchange through the through silicon vias.

More specifically, in the electrical connection structure between the upper chip and the lower chip stacked on each other, the conductive metal 14 exposed to the bottom through the through silicon vias of the upper chip and the through silicon vias of the lower chip are exposed upward. The conductive intermetallics are electrically connected to each other by conductive bumps.

Subsequently, the stacked upper and lower chips are mounted on a substrate, wire bonding is performed between the substrate and the upper chip, molded with a molding compound resin, and solder balls are mounted on the lower surface of the substrate to complete the stack package.

Such through silicon vias are generally formed after forming bit lines and metal interconnections. Since the width of through silicon vias is much larger than those of bit lines and metal interconnections, the periphery when forming holes for forming through silicon vias is formed. It causes a loss of metal wiring in the circuit area. This causes a problem in metal wiring, which lowers the reliability of the semiconductor device.

The present invention is to solve the problem of reducing the reliability of the semiconductor device by causing a loss in the metal wiring when forming the through-silicon via.

A method of forming a semiconductor device according to the present invention includes forming a first through silicon via embedded in a semiconductor substrate and penetrating a first interlayer insulating layer formed on the semiconductor substrate, and forming a first insulating film on the first through silicon via. And forming a second interlayer insulating film formed on the first insulating film, a metal wiring penetrating the first insulating film, and a second through silicon via connected to the first through silicon via. It features.

The forming of the first through silicon via may include forming an etch stop layer on the first interlayer insulating layer, forming a first mask pattern on the etch stop layer, and forming the first mask pattern. Forming a first trench by etching the etch stop layer, the first interlayer dielectric layer and the semiconductor substrate using an etch mask, and forming a spacer insulating layer on the first interlayer dielectric layer including the first trench surface; Performing a planarization etching process on the spacer insulating layer to expose the etch stop layer, removing the etch stop layer, and forming a conductive layer on the first interlayer insulating layer including the first trench; And performing a planarization etching process on the conductive layer to expose the first interlayer insulating layer. .

The method may further include forming an etch stop layer on the first interlayer insulating layer.

The planarization etching process may be performed on the spacer insulating layer to expose the etch stop layer.

The method may further include removing the etch stop layer after performing the planarization etching process.

The etch stop film is characterized in that it comprises a nitride film.

The conductive layer is characterized by containing copper.

The first insulating film may include a nitride film.

The forming of the metal interconnection and the second through silicon via may include forming a second interlayer insulating layer on the first insulating layer, forming a second mask pattern on the second interlayer insulating layer, Etching the second interlayer insulating layer and the first insulating layer using the second mask pattern as a mask to form a metal wiring trench and a second trench, and a second interlayer insulating layer including the metal wiring trench and the second trench. And forming a conductive layer on the conductive layer, and performing a planarization etching process on the conductive layer to expose the second interlayer insulating layer.

And forming a second insulating film on the second interlayer insulating film including the metal wiring and the second through silicon via after the forming of the metal wiring and the second through silicon via. do.

The second insulating film includes a nitride film.

According to the present invention, after the through silicon via is formed, the metal wiring is formed to reduce defects caused by the semiconductor device, thereby providing an effect of improving the reliability of the semiconductor device.

1A to 1L show a method of forming a semiconductor device according to the present invention, (i) is a sectional view showing a cell region and a peripheral circuit region, and (ii) is a sectional view showing a through silicon via (TSV) region.

Hereinafter, with reference to the accompanying drawings in accordance with an embodiment of the present invention will be described in detail.

As shown in FIGS. 1A and 1B, a first interlayer insulating film 102 and a semiconductor layer 100 are formed on a semiconductor substrate 100 including a cell region and a peripheral circuit region, and a through silicon via (TSV) region (ii). An etch stop film 104 is formed (FIG. 1A). For details of the etch stop layer 104, refer to the description of FIGS. 1D and 1E.

The first interlayer insulating film 102 may have a height in which gates, bit lines, lower electrodes, and upper electrodes of a cell region are stacked, and have a height of a metal contact connected to bit lines of a peripheral circuit region. In other words, the above-described configuration is formed in the cell region and the peripheral circuit region. Thereafter, a mask pattern 106 is formed on the nitride film 104 to define a trench in the TSV region (FIG. 1B).

As illustrated in FIG. 1C, the etch stop layer 104, the first interlayer insulating layer 102, and the semiconductor substrate 100 are etched using the mask pattern 106 as a mask to form a first trench T1. Here, the first trench T preferably defines a region where first through silicon vias formed in the TSV region are formed.

As shown in FIGS. 1D and 1E, a spacer insulating layer 108 is formed on the surface of the first trench T1 and the etch stop layer 104 (FIG. 1D). Subsequently, the spacer insulating film 108 formed on the etch stop film 104 is etched, and then the etch stop film 104 is removed (FIG. 1E). Etching the spacer insulating film 108 is preferably performed by a planarization etching process.

That is, the etch stop layer 104 serves as a barrier for removing the spacer insulating layer 108 formed on the portion except the surface of the first trench T1 so as to form the spacer insulating layer 108 only on the surface of the first trench T1. do. Therefore, since the etch stop layer 104 has a different characteristic from the spacer insulating layer 108, and in particular, the present invention uses the planar etching process as a method of removing the insulating layer, the etch stop layer 104 is performed even if the etch stop layer 104 is performed. ) Is preferably a material having a property of not being planarized.

As shown in FIGS. 1F and 1G, a conductive layer 110 is formed over the spacer insulating film 108 and the first interlayer insulating film 102 (FIG. 1F). Subsequently, the planarization etching process is performed on the conductive layer 110 to form the first through silicon vias 112 embedded in the first trenches T1, and then the first insulating layer 114 is formed on the entire upper portion of the conductive layer 110 (FIG. 2g). Here, the conductive layer 110 is preferably copper, and the first insulating film 114 is preferably a nitride film. In this case, the first insulating layer 114 serves to prevent the first through-silicon via 110 from being oxidized and to prevent migration.

As shown in FIGS. 1H and 1I, a second interlayer insulating film 116 is formed over the first insulating film 114 (FIG. 1H). Then, a photosensitive film pattern 118 is formed on the second interlayer insulating film 116 (FIG. 1I). In this case, the photoresist pattern 118 defines a metal wiring and a second through silicon via of the TSV region ii.

As illustrated in FIG. 1J, the second interlayer insulating layer 116 is etched using the photoresist pattern 118 (FIG. 1I) as a mask to form the trench T2 for metal wiring in the cell region. In addition, the second trenches T3 are formed by etching the second interlayer insulating layer 116 to expose the first through silicon vias 112 using the photoresist pattern 118 (FIG. 1I) as a mask. That is, the second trench T3 is formed on the same layer as the trench for metal wiring T2 formed in the cell region and the peripheral circuit region ii, and is formed to expose the first through silicon via 112 formed in the previous process. . This is because the first through-silicon vias 112 larger than the width of the metallization trench T2 are first formed before the metallization trench T2 is formed, so that the metallization is formed by being embedded in the metallization trench T2 in a subsequent process. The loss can be prevented.

As shown in FIGS. 1K and 1L, a conductive layer 120 is formed on the second interlayer insulating layer 116 including the trench T2 and the second trench T3 for metal wiring (FIG. 1K). Here, it is preferable that the conductive layer 120 contains copper. The planarization process is performed on the conductive layer 120 to expose the interlayer insulating film 114, thereby forming metal wirings 122 in the cell region and the peripheral circuit region, and second through silicon in the TSV region ii. Vias 124 are formed. Subsequently, the second insulating film 126 is formed over the entirety (FIG. 1L). Here, the second insulating film 126 is preferably a nitride film. Here, the second insulating layer 126 prevents the second through silicon via 120 from being oxidized and prevents it from moving.

As described above, the method of forming a semiconductor device of the present invention may include forming a second through silicon via connected to an upper portion of the first through silicon via at the same time as the metal wiring forming process after forming the first through silicon via before the metal wiring forming process. By forming, the problem that the metal wiring is lost in the process of forming the through-silicon via is fundamentally solved, thereby solving the problem of deterioration of the characteristics of the semiconductor device.

Claims (11)

Forming a first through silicon via embedded in the semiconductor substrate and penetrating through the first interlayer insulating layer formed on the semiconductor substrate;
Forming a first insulating layer on the first through silicon via; And
Forming a second interlayer insulating film formed over the first insulating film, a metal wiring penetrating the first insulating film, and a second through silicon via connected to the first through silicon via. Forming method. The method according to claim 1,
Forming the first through silicon via
Forming a first mask pattern on the first interlayer insulating film;
Etching the first interlayer insulating layer and the semiconductor substrate using the first mask pattern as an etch mask to form a first trench;
Forming a spacer insulating film on the first interlayer insulating film including the first trench surface;
Performing a planarization etching process on the spacer insulating layer to expose the first interlayer insulating layer;
Forming a conductive layer on the first interlayer insulating film including the first trench; And
And performing a planarization etching process on the conductive layer to expose the first interlayer insulating layer. The method according to claim 2,
And forming an etch stop film on the first interlayer insulating film. The method according to claim 3,
The planarization etching process may be performed on the spacer insulating layer.
The method of claim 1, wherein the etch stop layer is exposed. The method according to claim 3,
After performing the planarization etching process
Removing the etch stop layer. The method according to claim 3,
The etch stop layer is
A method of forming a semiconductor device comprising a nitride film. The method according to claim 2,
The conductive layer is
A method for forming a semiconductor device comprising copper. The method according to claim 1,
The first insulating film is
A method of forming a semiconductor device comprising a nitride film. The method according to claim 1,
Forming the metallization and the second through silicon via is
Forming a second interlayer insulating film on the first insulating film;
Forming a second mask pattern on the second interlayer insulating film;
Etching the second interlayer insulating layer and the first insulating layer using the second mask pattern as a mask to form a metal wiring trench and a second trench;
Forming a conductive layer on the second interlayer insulating layer including the metal wiring trench and the second trench; And
And performing a planarization etching process on the conductive layer to expose the second interlayer insulating layer. The method according to claim 1,
After forming the metallization and the second through silicon via,
And forming a second insulating film on the second interlayer insulating film including the metal wiring and the second through silicon via. The method according to claim 10,
The second insulating film is
A method of forming a semiconductor device comprising a nitride film.
KR1020100054800A 2010-06-10 2010-06-10 Method for forming semiconductor device KR20110135077A (en)

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KR1020100054800A KR20110135077A (en) 2010-06-10 2010-06-10 Method for forming semiconductor device

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Application Number Priority Date Filing Date Title
KR1020100054800A KR20110135077A (en) 2010-06-10 2010-06-10 Method for forming semiconductor device

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