KR20120119546A - Mother of oganic electro-luminesence display device substate and manufactucring metod of the same - Google Patents

Abstract

PURPOSE: A motherboard of an organic electroluminescence display device and a manufacturing method thereof are provided to prevent static electricity generated by a third shorting bar from being inserted to a display area of the panel and to reduce probability to generate a bad pixel. CONSTITUTION: A first shorting bar(110) is formed on a plurality of organic electroluminescence display panels. The first shorting bar is formed in the same material as both electrodes of the organic electroluminescence display device. A second shorting bar covers a display area of the organic electroluminescence display panels. The second shorting bar is formed as a gate line. A third shorting bar(116) is formed in a mesh shape. The third shorting bar is formed as a data line.

Description

Mother board of organic electroluminescent display panel and manufacturing method thereof {MOTHER OF OGANIC ELECTRO-LUMINESENCE DISPLAY DEVICE SUBSTATE AND MANUFACTUCRING METOD OF THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an organic light emitting display device and a method of manufacturing the organic light emitting display device. In particular, the organic light emitting display panel may prevent the static electricity by forming the shorting bars and the elements of the display area spaced apart from each other until the thin film transistor process is completed. It relates to a mother substrate and a method for producing the same.

The image display device that realizes various information on the screen is a core technology of the information communication age and it is becoming thinner, lighter, more portable and higher performance. Accordingly, an organic light emitting display panel that displays an image by controlling the amount of light emitted from the organic light emitting diode has been spotlighted as a flat panel display that can reduce weight and volume, which is a disadvantage of a cathode ray tube (CRT). The organic electroluminescent device is a self-luminous device using a thin light emitting layer between the electrodes has the advantage that it can be thinned like a paper.

In the organic light emitting display panel, pixels including three color (R, G, B) sub-pixels are arranged in a matrix to display an image. Each sub-pixel includes an organic electroluminescent element and a cell driver for driving the organic electroluminescent element. The cell driver includes at least two thin film transistors and a storage capacitor connected between a gate line for supplying a scan signal, a data line for supplying a video data signal, and a common power line for supplying a common power signal. Drive the anode.

The organic light emitting display panel is formed by forming a plurality of organic light emitting display panels on one mother substrate and then separating them by a scribing process. In this case, a shorting bar is formed on the mother substrate to prevent static electricity generated during the process of the organic light emitting display panel. The shorting bar is connected to both the gate line or the data line to distribute the static electricity generated during the manufacturing process to each line to create an equipotential, and is formed of the gate line or the data line.

However, the gate line, the data line, and the insulating film are formed by the sputtering method or the CVD method. Since the sputtering method or the CVD method is formed in the plasma state, positive or negative charges are generated. As such, due to the large charges in the plasma state, static electricity is generated, and thus static electricity flows into the gate line or the data line through the shorting bar, thereby causing pixel defects in the display area.

The present invention has been made to solve the above problems, and the mother substrate of the organic light emitting display panel which can prevent the static electricity by forming the shorting bars and the elements of the display area spaced apart from each other until the process of the thin film transistor process is completed and It is to provide a method for producing the same.

To this end, according to the present invention, a plurality of organic light emitting displays including pixels connected to a gate line, a data line, a power line, a reference voltage line, and an emission line are arranged in a matrix form, and each of the pixels includes an organic electroluminescent element. Panels, a plurality of shorting bars to prevent static electricity by distributing static electricity generated during the manufacturing process of the organic light emitting panels in each line to equipotential, and a screen for cutting each organic light emitting display panel In the mother substrate of the organic light emitting display panel including an ice line, the plurality of shorting bars are formed in the outer region of the plurality of organic light emitting display panels, the same layer of the same material as the anode of the organic light emitting display device A first shorting bar formed on the display panel and surrounding the display area of the organic light emitting display panel; Second shorting bar is formed of the second shorting is connected so as to intersect to occur as described mesh (Mesh) type, characterized in that it comprises a third shorting bar formed from the second data line.

The organic light emitting display panel may include a display area including the plurality of pixels, a plurality of antistatic patterns for preventing static electricity generated during the process, the gate line, And a non-display area in which the test pad unit and the shorting bars are formed to test the lighting of the devices of the display area by applying a test signal to the data line and the emission line.

The display device may further include connection lines connected to the third shorting bar, wherein the connection lines are connected to each of the gate line, the data line, and the emission line through a connection electrode pattern part.

The connection electrode pattern part may include first to third connection electrode pattern parts, and the first connection electrode pattern part includes a first connection electrode connected by the connection line and the emission line, the connection line and the gate line; And a second connection electrode for connecting, wherein the second connection electrode pattern portion includes a first connection electrode for connecting the connection line and the data line, and the third connection electrode pattern portion includes the second shorting bar and the third connection electrode. And a second connection electrode connected to each other at a point where the shorting bars cross each other, and a second connection electrode connected to each other at a point where the second shorting bar and the third shorting bar are parallel to each other.

The antistatic patterns may be formed of a plurality of zener diodes in each connection line.

The antistatic patterns may be formed of a plurality of diodes on each of the gate line, the data line, and the emission line.

The present invention relates to a plurality of organic light emitting display panels including pixels connected to a gate line, a data line, a power line, a reference voltage line, and an emission line in a matrix form, each pixel including an organic electroluminescent element. And a first shorting bar formed in an outer region of the plurality of organic light emitting display panels, a second shorting bar formed to surround a display area of the organic light emitting display panel, and a second shorting bar and a mesh type. A method of manufacturing a mother substrate of an organic light emitting display panel including a third shorting bar formed to cross each other, the plurality of thin film transistors being formed in pixels of the organic light emitting display panel of the mother substrate, wherein the gate line is formed. A second shorting bar of the same material as the material, a third shorting bar of the same material as the data line, the gate line or the data line. Forming a connection line, forming a passivation layer including a plurality of contact holes on the thin film transistor, the second shorting bar, the third shorting bar, and the mother substrate on which the connection lines are formed; Connecting the anode of the EL device, the first shorting bar, the connection lines, the gate line, the data line, and the emission line, and forming the connection electrode pattern parts between the second shorting bar and the third shorting bar. It is characterized by including.

The first shorting bar and the second shorting bar may be formed to be spaced apart from each other until a process before the first shorting bar is formed.

The connection electrode pattern part may include first to third connection electrode pattern parts, and the first connection electrode pattern part includes a first connection electrode connected by the connection line and the emission line, the connection line and the gate line; And a second connection electrode for connecting, wherein the second connection electrode pattern portion includes a first connection electrode for connecting the connection line and the data line, and the third connection electrode pattern portion includes the second shorting bar and the third connection electrode. And a second connection electrode connected to each other at a point where the shorting bars cross each other, and a second connection electrode connected to each other at a point where the second shorting bar and the third shorting bar are parallel to each other.

According to the present invention, a first shorting bar formed in an outer region of a plurality of organic light emitting display panels, a second shorting bar formed to surround a display area of an organic light emitting display panel, and a third crossing the second shorting bar to have a mesh shape are provided. It includes a shorting bar. In this case, the first to third shorting bars are formed in a layout that is not connected to each other until the thin film transistor process of the display area is completed. When the anode of the organic light emitting diode is formed, the first shorting bars are formed. The first to third shorting bars are connected via the connecting electrode.

Accordingly, since the static electricity generated by the first to third shorting bars is prevented from flowing into the display area of the organic light emitting display panel, the probability of generating defective pixels is reduced, thereby improving display quality and reliability of the organic light emitting display panel. Can be.

1 is a plan view illustrating a mother substrate of an organic light emitting display panel according to the present invention.
FIG. 2 is an enlarged plan view of a mother substrate of the organic light emitting display panel illustrated in FIG. 1.
3 is an enlarged plan view of a region A and a region B illustrated in FIG. 2.
4 is a cross-sectional view of the organic light emitting display panel illustrated in FIG. 3 taken along lines II ′ and II-II ′.
5 is a circuit diagram of one pixel.
6A to 9 are plan views and cross-sectional views illustrating a method of manufacturing a mother substrate of an organic light emitting display panel according to an exemplary embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The configuration of the present invention and the operation and effect thereof will be clearly understood through the following detailed description. Before describing the present invention in detail, the same components are denoted by the same reference symbols as possible even if they are displayed on different drawings. In the case where it is judged that the gist of the present invention may be blurred to a known configuration, do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 1 to 9.

1 is a plan view illustrating a mother substrate of an organic electroluminescent display panel according to the present invention, and FIG. 2 is an enlarged plan view of a part of the mother substrate of the organic electroluminescent display panel illustrated in FIG. 1. 3 is an enlarged plan view of region A and region B shown in FIG. 2, and FIG. 4 is a cross-sectional view of the organic light emitting display panel illustrated in FIG. 3 taken along lines II ′ and II-II ′. to be. 5 is a circuit diagram of one pixel.

As shown in FIGS. 1 and 2, the mother substrate 100 of the organic light emitting display panel according to the exemplary embodiment of the present invention includes a plurality of organic light emitting display panels arranged in a matrix type, and a plurality of organic light emitting display panels. A plurality of shorting bars 110, 114a, 114, and 116 for preventing static electricity by distributing static electricity generated during the manufacturing process of the panels in each line to equipotential, and a scribing line 112 for cutting each organic electroluminescent display panel. ).

Each organic light emitting display panel includes a display area 102 for displaying an image, a plurality of antistatic pattern parts, and a non-display area in which test pad parts 120 and 122 and shorting bars 114a, 114 and 116 are formed.

In the active area of the organic light emitting display panel, pixels connected to the gate line GL, the data line DL, the power line PL, the reference voltage line Vref, and the emission line EML are arranged in a matrix. It is arranged in the form. The power supply line PL supplies a high potential driving voltage Vdd to each of the pixels, and the reference voltage line VLref supplies a reference voltage Vref to each of the pixels. Each of the pixels includes a plurality of switching transistors T1 to T5, a driving transistor DT, and an organic light emitting diode formed in an intersection region of the signal lines.

The gate electrode of the driving transistor DT is connected to the switching circuit through the first node N1, the source electrode of the driving transistor DT is connected to the power supply line PL, and the drain electrode of the driving transistor DT is It is connected to a switch circuit via the 6th node N6. The driving transistor DT controls the amount of current flowing through the organic EL device according to the difference voltage between the gate electrode and the source electrode.

The organic light emitting diode includes an anode 222 connected to the drain electrode 210 of the fourth transistor T4, a bank insulating film 230 having a bank hole 235 exposing the anode 222, and a bank hole 235. And an organic layer 232 formed on the anode 222 exposed through), and a cathode 234 formed on the organic layer 232. The organic layer 232 includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, and an electron injection layer stacked from the anode 222. The organic layer 232 emits light according to the amount of current supplied to the anode 222. Depending on the material of the cathode 234 and the anode 222, the front light emitting to the front of the substrate, the rear light emitting to the rear of the substrate or the double-sided light emitting to the front and rear of the substrate can be. In this case, the anode 222 is formed of a transparent electrode material, and materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and antimony tin oxide (ATO) may be used as the transparent electrode material. It can be formed as.

The plurality of switching transistors include first to fifth switching transistors T1 to T5.

A gate electrode of the first switching transistor T1 is connected to the second node N2, a source electrode of the first switching transistor T1 is connected to the data line DL, and a drain of the first switching transistor T1. The electrode is connected to the third node N3.

The gate electrode of the second switching transistor T2 is connected to the emission line EML, the source electrode of the second switching transistor T2 is connected to the third node N3, and the gate electrode of the second switching transistor T2 The drain electrode is connected to the reference voltage line VLref.

A gate electrode of the third switching transistor T3 is connected to the gate line GL, a source electrode of the third switching transistor T3 is connected to the first node N1, and a drain of the third switching transistor T3. The electrode is connected to the sixth node N6.

A gate electrode of the fourth switching transistor T4 is connected to the emission line EML, a source electrode of the fourth switching transistor T4 is connected to the sixth node N6, and a gate electrode of the fourth switching transistor T4 is connected. The drain electrode is connected to the anode of the organic electroluminescent element. In contrast, as shown in FIG. 4, in the fourth transistor T4, the buffer layer 216 and the active layer 214 are formed on the lower substrate, and the gate electrode 206 is formed in the channel region 214C of the active layer. And the gate insulating film 212 are interposed therebetween. The source electrode 208 and the drain electrode 210 are formed to be insulated with the gate electrode 206 and the interlayer insulating film 226 interposed therebetween. The source electrode 208 and the drain electrode 210 are active layers in which n + impurities are injected through the source contact hole 224S and the drain contact hole 224D, which pass through the interlayer insulating film 226 and the gate insulating film 212. It is connected to each of the source region 214S and the drain region 214D of 214. Also, the active layer 214 (LDD) region (not shown) in which n- impurity is implanted between the channel region 214C and the source and drain regions 214S and 214D to reduce the off current. ) It is also equipped with more. A passivation layer is formed to cover the fifth transistor, and the passivation layer includes a pixel contact hole exposing the drain electrode.

A gate electrode of the fifth switching transistor T5 is connected to the gate line GL, a source electrode of the fifth switching transistor T5 is connected to the reference voltage line VLref, and a drain of the fifth switching transistor T5. The electrode is connected to the seventh node N7.

The non-display area of the organic light emitting display panel includes antistatic pattern parts 130, 132, 134, 136, 138, 150, 152, 154 and 156, test pattern parts 120 and 122, and a plurality of shorting bars 114a, 114, and 116. Here, a detailed description of the shorting bar will be described later.

The test pattern unit includes first and second test pattern units 120 and 122 and inspects an electrical lighting test performed after various signal lines and transistors of the organic light emitting display panel are formed and defects of each pixel. Specifically, the plurality of lighting test pads formed in each of the first and second test pattern units 120 and 122 are electrically contacted with the pins of the auto probe device to receive a signal. The lighting of the organic light emitting display panel is checked by signals applied to the plurality of lighting test pads.

The first test pattern unit 120 includes first to third inspection pads 120a, 120b and 120c, and the first inspection pad 120c supplies a test signal to the emission line EML. The second test pad 120b supplies the test signal to the gate line GL, and the third test pad 120c supplies the test signal to the first switching line SWL1. Each of the first to third inspection pads 120a, 120b, and 120c of the first test pattern unit 120 is connected to an upper electrode formed through the third shorting bar 116, and an upper electrode and a contact hole. The lower electrode extends from the connection lines CL1, CL2 and CL3.

The second test pattern unit 122 includes first and second test pads 122a and 112b, and the first test pad 122b supplies a test signal to the data line DL and a second test. The pad 122a supplies a test signal to the second switching line SWL2. Each of the first and second inspection pads of the second test pattern unit 122 is not illustrated as shown in FIG. 3, but like the first test pattern unit 120, the upper electrode is formed to extend from the third shorting bar 116. And a lower electrode extending from the connection lines CL4 and CL4 connected through the upper electrode and the contact hole.

The antistatic pattern portion includes first to tenth antistatic patterns 130, 132, 134, 136, 138, 150, 152, 154, and 156 so that static electricity is transmitted to the transistors in the display area so as not to be damaged. The first to tenth antistatic patterns 130, 132, 134, 136, 138, 150, 152, 154 and 156 are formed of a plurality of diodes in each signal line, and when static electricity is generated, the first to tenth antistatic patterns 130, 132, 134, 136, 138, 150, 154, 156 are discharged through the plurality of diodes so as not to affect the elements of the display area. As such, the static electricity is prevented through shorting bars other than the plurality of antistatic patterns to prevent static electricity. The shorting bars are connected to all of the gate line, the data line, and the emission line of the display area. The shorting bar prevents static electricity by distributing static electricity in each line to equipotential, but static electricity is generated as the third shorting bar 116 of the shorting bars is scribed during the scribing process. In addition, since the static electricity is often introduced through the shorting bar during the panel manufacturing process, a plurality of antistatic patterns are formed to prevent the static electricity.

Specifically, the first to fifth antistatic patterns 130, 132, 134, 150, and 154 are formed between the gate line GL, the emission line EML, and the first switching line SWL1 to form the gate line GL and the emission line EML. ), The static electricity flowing into the first switching line SWL1 is discharged to prevent static electricity from flowing into the elements of the display area. The first antistatic pattern 130 may generate static electricity even when it is electrically connected to the test pads 120a, 120b and 102c of the first test pattern unit 120 and the pins of the auto probe device. In order to prevent the inflow, the first test pattern unit 120 and the connection lines CL1 to CL3 are formed. In addition, the first antistatic pattern 130 is formed of a plurality of zener diodes ZDn in each connection line as shown in FIGS. 2 and 3. When static electricity flows in, when a static voltage of several KV or more is applied to the zener diode regardless of the polarity of the current, the zener diode is turned on to dissipate the static electricity. That is, the zener diode ZD is conducted at a predetermined voltage or higher regardless of the polarity of the constant voltage to prevent static electricity.

The second antistatic pattern 132 is formed of a plurality of diodes Dn in each signal line so as to prevent static electricity when the static electricity is not prevented through the first antistatic pattern 130. Specifically, as shown in FIG. 3, the second antistatic pattern 132 is formed of a plurality of diodes in the emission line EML to prevent static electricity flowing into the emission line EML, and the gate line GL ) Is formed of a plurality of diodes to prevent static electricity flowing into the gate line GL, and is formed of a plurality of diodes in the first switching line SWL1 to prevent static electricity flowing into the first switching line SWL1. Since the third antistatic pattern 134 is formed of a plurality of diodes in each line in the same manner as the second antistatic pattern 132, it will be omitted. The fourth and fifth antistatic patterns 150 and 154 may be formed adjacent to the display area 102 to prevent static electricity. As such, the first to fifth antistatic patterns 130, 132, 134, 150, and 154 are connected to the gate line GL, the emission line EML, and the first switching line SWL1 to prevent static electricity flowing into each signal line. Pattern 130-> second antistatic pattern 132-> third antistatic pattern 134-> fourth antistatic pattern 154-> fifth antistatic pattern 150 By discharging in a step, inflow of static electricity to the devices of the display area may be prevented.

In addition, the sixth to tenth antistatic patterns 135, 136, 138, 152 and 156 are formed between the data line DL and the second switching line SWL2 to discharge static electricity flowing into the data line DL and the second switching line SWL2. This prevents static electricity from flowing into the elements of the display area. The sixth antistatic pattern 138 may generate static electricity even when the sixth antistatic pattern 138 is electrically connected to the test pads 122a and 122b of the second test pattern unit 122 and the pin of the auto probe device. It is formed between the first test pattern portion 122 and the connection lines CL4 and CL5 to prevent it. In addition, like the first antistatic pattern, the sixth antistatic pattern 138 is formed of a plurality of zener diodes ZDn in each connection line. When static electricity flows in, when a static voltage of several KV or more is applied to the zener diode regardless of the polarity of the current, the zener diode is turned on to dissipate the static electricity. That is, the zener diode ZD is conducted at a predetermined voltage or higher regardless of the polarity of the constant voltage to prevent static electricity.

The seventh antistatic pattern 136 is formed of a plurality of diodes Dn in each signal line so as to prevent static electricity when the electrostatic charge is not prevented through the sixth antistatic pattern 138. In detail, the seventh antistatic pattern 136 is formed of a plurality of diodes on the data line DL, like the second antistatic pattern, to prevent static electricity flowing into the data line DL, and the second switching line SWL2. ) Is formed of a plurality of diodes to prevent static electricity flowing into the second switching line SWL2. Since the eighth antistatic pattern 135 is formed of a plurality of diodes in each line in the same manner as the seventh antistatic pattern 136, it will be omitted. The ninth and tenth antistatic patterns 152 and 156 may be formed adjacent to the display area 102 to prevent static electricity. As such, the sixth to tenth antistatic patterns 135, 136, 138, 152, and 156 are connected to the data line DL and the second switching line SWL2 to prevent static electricity flowing into each signal line. The seventh antistatic pattern 136-> the eighth antistatic pattern 135-> the ninth antistatic pattern 156-> the tenth antistatic pattern 152 may be discharged in five steps. The device can prevent static electricity from entering.

The shorting bars include first to third shorting bars 110, 114a, 114, and 116, and the first to third shorting bars 110, 114a, 114, and 116 are connected to each other after the thin film transistor process is completed. The shorting bars 110, 114a, 114, and 116 disperse static electricity generated during the manufacturing process of the plurality of organic electroluminescent panels in each line to equipotential to prevent static electricity.

In detail, the first shorting bar 110 is formed at an outer region of the plurality of organic light emitting display panels formed on the mother substrate 100, and is simultaneously formed when the anode 222 of the organic light emitting diode is formed. That is, the first shorting bar 110 is formed of a transparent electrode, and as the transparent electrode material, indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and antimony tin oxide (ATO) It can be formed from the material of. Conventionally, although the first shorting bar is formed of the same material at the same time when forming the gate line or the data line, the present invention is formed when the anode 222 is formed after the thin film transistor process formed in the display area is completed.

In other words, when the gate line or the data line is formed, it is deposited by the sputtering method. Since the sputtering method is formed in the plasma state, positive or negative charges are generated. In this plasma state, a lot of charges are rather generated static electricity. That is, when the first shorting bar is formed as a gate line or a data line, static electricity generated when the first shorting bar is formed is introduced into each panel through the gate line or the data line. Accordingly, after the thin film transistor process in the display area is completed, the first shorting bar 110 is formed when the anode 222 of the organic light emitting diode is formed.

As described above, since the first shorting bar 110 is not formed until the thin film transistor process of the display area 102 is completed, the first to third shorting bars of each of the organic light emitting display panels formed on the mother substrate ( 110, 114a, 114, and 116 are not connected to each other. Accordingly, the second shorting bars 114a and 114 and the third shorting bar 116 between adjacent organic light emitting display panels are spaced apart from each other. In addition, after the thin film transistor of the display area 102 is completed, the first shorting bar 110 is formed when the anode 222 is formed, and the first to third shorting bars 110, 114a, 114, and 116 are connected to each other. As such, after the first to third shorting bars 110, 114a, 114, and 116 are connected, the static electricity generated during the thin film transistor process of the display area is dispersed in each line to be equipotential to prevent static electricity.

The second shorting bars 114a and 114 are formed to surround the display area 102 of the organic light emitting display panel, and are simultaneously formed when the gate line GL is formed. The second shorting bars 114a and 114 are formed to surround the display area in a U shape and are connected to the first shorting bar 110 through the contact hole 110a. To this end, the second shorting bar 114a is formed in an area adjacent to the test pattern parts 2120 and 122, and the first line 114 connected to the first shorting bar 110 through the contact hole 110a. The second line 114a may be formed to surround the display area 102. The second line 114a may have a width wider than that of the first line 114 to reduce line resistance.

The third shorting bars 116 are connected to intersect the second shorting bars 116 in a mesh shape, and are simultaneously formed when the data lines DL are formed. The third shorting bar 116 is connected to the second shorting bar 116 through the third connection electrode pattern parts 144 and 146, and the test pads 120a to 120c, 122a and 122b of the test pattern parts 120 and 122. Is connected to the upper electrode.

The connection electrode pattern parts 140, 142, 144, and 146 may be connected to the plurality of connection lines CL1 to CL3, the gate lines GL, the emission lines EML, and the first switching line SWL1. And a second connection electrode pattern part 142 connecting the plurality of connection lines CL4 and CL5, the data line DL, and the second switching line SWL2, and the second shorting bars 114 and 114a and the third connection electrode. And third connection electrode pattern parts 144 and 146 connecting the shorting bar 116. The connection electrode pattern parts 140, 142, 144, and 146 are simultaneously formed when the anode 222 of the organic light emitting diode is formed, and are formed of a transparent electrode material.

As shown in FIG. 3, the first connection electrode pattern part 140 includes a first connection electrode 140c and a second connection line CL2 that connect the first connection line CL1 and the emission line EML. And a second connection electrode 140b connected to the gate line GL, and a third connection electrode 140c connected to the third connection line CL3 and the first switching line SWL1. As described above, since the connection electrode pattern part is formed during the formation of the anode, the first to third connection lines CL1 to CL3, the gate line GL, the emission line EML, and the first switching line are formed until the anode formation process. SWL1 is spaced apart from each other.

The second connection electrode pattern part 142 includes a first connection electrode 142a connecting the fourth connection line CL4 and the data line DL, a fifth connection line CL5 and the second switching line SWL2. And a fifth connection electrode 142b which connects with the second connection electrode. As described above, since the connection electrode pattern part is formed when the anode is formed, the fourth and fifth connection lines CL4 and CL5, the data line DL, and the second switching line SWL2 are not formed until the process of forming the anode 222. Spaced apart from each other.

The third connection electrode pattern parts 144 and 146 may include a first connection electrode 144a connecting to each other at a point where the first line 114 and the third shorting bar 116 of the second shorting bar cross each other, and the second show. The second line 114a of the putting bar and the third shorting bar 116 include a second connection electrode 144b connected to each other at a point parallel to each other. As such, since the connection electrode pattern part is formed when the anode 222 is formed, the second shorting bars 114 and 114a and the third shorting bar 116 are not connected to each other until the formation of the anode. As such, when the anode is formed, the second shorting bars 114 and 114a and the third shorting bar 116 are connected, and when the anode is formed, the first shorting bar 110 is also formed to be connected to the second shorting bars 114a and 114. Therefore, the static electricity generated during the thin film transistor process in the display area is dispersed in each line to become an equipotential to prevent static electricity.

6A through 9 are cross-sectional views and plan views illustrating a method of manufacturing a mother substrate of an organic light emitting display panel according to an exemplary embodiment of the present invention.

6A and 6B, a plurality of thin film transistors are formed in a display area of an organic light emitting display panel of a mother substrate 100, a plurality of connection lines CL1 to CL5, and second and third shorting bars. 114a, 114, and 116 are formed, and a protective film 219 is formed.

Specifically, the buffer layer 216 and the active layer 214 are formed in the display area of the organic light emitting display panel of the mother substrate 100, and the gate electrode 206 is formed of the channel region 214C and the gate insulating layer of the active layer. 212 is formed to overlap each other. The source electrode 208 and the drain electrode 210 are formed to be insulated with the gate electrode 206 and the interlayer insulating film 226 interposed therebetween. The source electrode 208 and the drain electrode 210 are active layers in which n + impurities are injected through the source contact hole 224S and the drain contact hole 224D, which pass through the interlayer insulating film 226 and the gate insulating film 212. It is connected to each of the source region 214S and the drain region 214D of 214. In this case, the gate line GL, the emission line EML, the first switching line SWL1, the first to third connection lines CL1 to CL3, and the second shorting bars 114a and 114 are gate electrodes 206. ) Formed on the same layer with the same material. The emission line EML and the first connection line CL1 are formed to be spaced apart from each other, the gate line GL and the second connection line CL2 are formed to be spaced apart from each other, and the first switching line SWL1 and the third connection line CL3 are formed to be spaced apart from each other.

The data line DL, the second switching line SWL2, the fourth and fifth connection lines CL4 and CL5, and the third shorting bar 116 are formed when the source electrode 208 and the drain electrode 210 are formed. The same material is formed on the same layer. The data line DL and the fourth connection line CL4 are formed to be spaced apart from each other, and the second switching line SWL2 and the fifth connection line CL5 are formed to be spaced apart from each other.

In addition, the second shorting bars 114a and 114 and the third shorting bar 116 are formed to cross each other in a mesh form with the interlayer insulating layer 226 interposed therebetween, and are not connected to each other.

On the other hand, the gate electrode 206, the source and drain electrodes 208, 210 are formed of a metal material, it is formed by a sputtering method. The active layer 214, the gate insulating film 212, the interlayer insulating film 226, and the buffer layer 216 are deposited by a method such as PECVD or CVD. As such, the sputtering method, the PECVD, and the CVD method may be formed in a plasma state, and thus a lot of charges may be generated to accumulate charges, thereby generating static electricity. The first to fifth connection lines CL1 to CL5 and the signal lines (gate line, emission line, first switching line, data line, and second switching line) are spaced apart from each other. 3 Static electricity generated from the shorting bars 114a, 114, and 116 does not flow.

7A and 7B, a plurality of contact holes 220, 160, 162, 164, 166 and 110a penetrating through the passivation layer 219 formed on the mother substrate 100 are formed.

In detail, the passivation layer 219 formed on the mother substrate 100 may include the pixel contact hole 220 to expose the drain electrode 210 of the thin film transistor and the first connection formed to expose the connection lines CL1 to CL5. A second connection contact formed to expose the contact holes 160, the gate line GL, the emission line EML, the first switching line SWL1, the data line DL, and the second switching line SWL2. The third connection contact hole 164 formed to expose the holes 162, the second shorting bar 114a, and the fourth connection contact hole 166 formed to expose the third shorting bar 116 are formed. .

8A and 8B, the anode 222, the connection electrode pattern parts 140, 142, 144, and 146, and the first shorting bar 110 are formed on the mother substrate 100.

In detail, the anode 222 is formed on the pixel contact hole 220 to be connected to the drain electrode 201 of the thin film transistor. A first connection electrode 140c connecting the first connection line CL1 and the emission line EML, a second connection electrode 140b connecting the second connection line CL2 and the gate line GL; The first connection electrode pattern part 140 including the third connection electrode 140a connecting the third connection line CL3 and the first switching line SWL1 is formed. The first connection electrode 142a connecting the fourth connection line CL4 and the data line DL and the second connection electrode connecting the fifth connection line CL5 and the second switching line SWL2 ( A second connection electrode pattern portion 142 including 142b is formed. In addition, the first connecting electrode 144a and the second shorting bars 114 and 114a and the third shorting bar (114a, 114a, 114) connecting at the point where the second shorting bar (114a, 114) and the third shorting bar (116) cross each other. Third connection electrode pattern parts 144 and 146 including second connection electrodes 144b connecting to each other at points 116 parallel to each other are formed. The first shorting bars 110 connected to the second shorting bars 114 and 114a and the contact holes 110a are formed on the outer sides of the organic light emitting display panels. As such, the anode, the connection electrode pattern part including the first to third connection electrode pattern parts 140, 142, 144, and 146, and the first shorting bar 110 are formed of a transparent electrode material on the mother substrate 100. The transparent electrode material may be formed of materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), and antimony tin oxide (ATO).

Referring to FIG. 9, a bank insulating layer 230 is formed on a mother substrate on which an anode 222 is formed, and includes a bank hole 235, an organic layer 232, and a cathode 234 penetrating through the bank insulating layer 230. An organic electroluminescent element is formed. The organic layer includes a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron transport layer.

The foregoing description is merely illustrative of the present invention, and various modifications may be made by those skilled in the art without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the specification of the present invention are not intended to limit the present invention. The scope of the present invention should be construed according to the following claims, and all the techniques within the scope of equivalents should be construed as being included in the scope of the present invention.

100: mother substrate 102: display area
110: first shorting bar 112: scribing line
114a, 114: second shorting bar 116: third shorting bar
130,132,134,136,138,150,152,154,156; Antistatic pattern part
120,122: test pattern part
140,142,144,146: connecting electrode pattern portion

Claims (9)

Pixels connected to gate lines, data lines, power lines, reference voltage lines, and emission lines are arranged in a matrix, and each of the plurality of organic light emitting display panels includes an organic electroluminescent element; The organic light emitting panel includes a plurality of shorting bars for preventing static electricity by distributing static electricity generated during the manufacturing process of the organic light emitting panels of each organic light line to equipotential, and a scribing line for cutting each organic light emitting display panel. In the mother substrate of the electroluminescent display panel,
The plurality of shorting bars
A first shorting bar formed in an outer region of the plurality of organic light emitting display panels and formed on the same layer as the anode of the organic light emitting diode;
A second shorting bar formed to surround the display area of the organic light emitting display panel and formed of the gate line;
And a third shorting bar connected to the second shorting bar so as to have a mesh shape and formed of the data line. The method of claim 1,
Each of the organic light emitting display panels includes: a display area including the plurality of pixels;
The organic light emitting display panels apply a plurality of antistatic patterns to prevent static electricity generated during the process and a test signal applied to the gate line, the data line, and the emission line to test the lighting of the devices of the display area. And a non-display area in which the test pad unit and the shorting bars are formed. The method of claim 2,
And a connection line connected to the third shorting bar, wherein the connection lines are connected to each of the gate line, the data line, and the emission line through a connection electrode pattern unit. The method of claim 3,
The connection electrode pattern part includes first to third connection electrode pattern parts,
The first connection electrode pattern portion includes a first connection electrode connecting the connection line and the emission line, and a second connection electrode connecting the connection line and the gate line.
The second connection electrode pattern part includes a first connection electrode connecting the connection line and the data line.
The third connecting electrode pattern part may be connected to each other at a point where the second shorting bar and the third shorting bar are connected to each other at a point where the second shorting bar and the third shorting bar cross each other. A mother substrate of an organic light emitting display panel comprising two connecting electrodes. The method of claim 3,
And the antistatic patterns are formed of a plurality of zener diodes on each of the connection lines. The method of claim 3,
The antistatic patterns may be formed of a plurality of diodes on each of the gate line, the data line, and the emission line, the mother substrate of the organic light emitting display panel. Pixels connected to gate lines, data lines, power lines, reference voltage lines, and emission lines are arranged in a matrix, and each of the plurality of organic light emitting display panels includes an organic electroluminescent element; A first shorting bar formed in an outer region of the organic light emitting display panels of the organic light emitting display panel, a second shorting bar formed to surround the display area of the organic light emitting display panel, and the second shorting bar and a mesh type. In the manufacturing method of the mother substrate of the organic light emitting display panel comprising a third shorting bar formed so as to,
A plurality of thin film transistors are formed in the pixels of the organic light emitting display panel of the mother substrate, the second shorting bar made of the same material as the gate line, the third shorting bar made of the same material as the data line, the gate line or the Forming connection lines formed of data lines;
Forming a passivation layer including a plurality of contact holes on the thin film transistor, the second shorting bar, the third shorting bar, and the mother substrate on which the connection lines are formed;
Connecting the anode of the organic light emitting diode, the first shorting bar, the connection lines, the gate line, the data line, and the emission line, and forming the connection electrode pattern portions between the second shorting bar and the third shorting bar. A method of manufacturing a mother substrate of an organic light emitting display panel comprising the step of. The method of claim 7, wherein
The first shorting bar and the second shorting bar is formed to be spaced apart from each other until the process before the first shorting bar is formed. The method of claim 7, wherein
The connection electrode pattern part includes first to third connection electrode pattern parts,
The first connection electrode pattern portion includes a first connection electrode connecting the connection line and the emission line, and a second connection electrode connecting the connection line and the gate line.
The second connection electrode pattern part includes a first connection electrode connecting the connection line and the data line.
The third connecting electrode pattern part may be connected to each other at a point where the second shorting bar and the third shorting bar are connected to each other at a point where the second shorting bar and the third shorting bar cross each other. 2. A method of manufacturing a mother substrate of an organic light emitting display panel comprising a connecting electrode.

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