KR102201530B1 - Organic Light Emitting Display Device - Google Patents

Abstract

The present invention provides a pixel formed in a pixel area on a substrate; A power line supplying power to the pixel; A data line supplying a data voltage to the pixel; And an electrostatic discharge unit formed outside the pixel region, wherein the electrostatic discharge unit includes a connection line for discharging static electricity and a thin film transistor connected to the connection line, and the connection line is formed in an island structure. It provides an organic light emitting display device.

Description

Organic Light Emitting Display Device

The present invention relates to an organic light-emitting display device, and more particularly, to an organic light-emitting display device having an electrostatic discharge unit.

An organic light emitting diode display has a structure in which an emission layer is formed between a cathode injecting electrons and an anode injecting holes, and electrons generated at the cathode and holes generated at the anode are the emission layer. When injected into the interior, the injected electrons and holes are combined to generate excitons, and the generated excitons fall from an excited state to a ground state to emit light.

Hereinafter, a conventional organic light emitting display device will be described with reference to the drawings.

1 is a schematic plan view of a conventional organic light emitting display device.

As can be seen from FIG. 1, a pixel area (PA), an electrostatic discharge (ESD), a gate driver 20, and a data driver 30 are formed on the substrate 10.

In the pixel area PA, a plurality of pixels P are arranged in a horizontal direction and a vertical direction. Each of the plurality of pixels P includes a light emitting portion E that emits light and a circuit portion C that controls light emission of the light emitting portion E. Although not specifically shown, the light-emitting unit E includes an anode, a cathode, and an organic layer formed between the anode and the cathode, and the circuit unit C includes a gate line, a data line, a power line, and a switching thin film transistor. , A driving thin film transistor, and a capacitor.

The electrostatic discharge part ESD is formed to surround the pixel area PA. The electrostatic discharge unit ESD prevents damage to the circuit unit C in the pixel P by static electricity generated during the manufacturing process.

The gate driver 20 is formed on the first side of the pixel area PA, for example, on the left side. The gate driving part 20 applies a gate signal to the gate wiring of the circuit part C.

The data driver 30 is formed around the second side, for example, the upper side of the pixel area PA. The data driver 30 applies a data signal to the data line of the circuit unit C.

In such a conventional organic light emitting display device, as can be seen from the enlarged view drawn by an arrow, a pixel P is formed on the lower electrostatic discharge unit ESD. In particular, the pixel P is formed on the lower electrostatic discharge unit ESD. The circuit portion C constituting (P) is formed.

The circuit part (C) includes various wires as described above. When the electrostatic discharge part (ESC) and the circuit part (C) are adjacent, static electricity between the electrostatic discharge part (ESC) and the wires of the circuit part (C) Can occur. As described above, when static electricity is generated between the electrostatic discharge unit ESC and the circuit unit C, there is a problem in that a striped band is visible during image reproduction due to static electricity flowing through the wiring constituting the circuit unit C.

The present invention has been devised to solve the above-described conventional problem, and an object of the present invention is to provide an organic light emitting display device capable of preventing a problem of generating static electricity between an electrostatic discharge unit and a circuit unit.

In order to achieve the above object, the present invention comprises: a pixel formed in a pixel region on a substrate; A power line supplying power to the pixel; A data line supplying a data voltage to the pixel; And an electrostatic discharge unit formed outside the pixel region, wherein the electrostatic discharge unit includes a connection line for discharging static electricity and a thin film transistor connected to the connection line, and the connection line is formed in an island structure It provides an organic light emitting display device.

According to the present invention as described above has the following effects.

According to an embodiment of the present invention, by forming the connection wiring of the electrostatic discharge unit in an island structure, it is possible to reduce the amount of charge in the connection wiring, thereby preventing the generation of static electricity by the connection wiring.

1 is a schematic plan view of a conventional organic light emitting display device.
2 is a schematic plan view of an organic light emitting diode display according to an exemplary embodiment of the present invention.
3 is a plan view illustrating a dummy pixel and an electrostatic discharge unit according to an embodiment of the present invention, which shows four dummy pixels.
4 is a cross-sectional view of the line II of FIG. 3 according to an exemplary embodiment.
5 is a circuit diagram of a pixel P according to an exemplary embodiment of the present invention.

Advantages and features of the present invention, and a method of achieving them will become apparent with reference to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms different from each other, and only these embodiments make the disclosure of the present invention complete, and common knowledge in the technical field to which the present invention pertains. It is provided to completely inform the scope of the invention to those who have it, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and the present invention is not limited to the illustrated matters. The same reference numerals refer to the same components throughout the specification. In addition, in describing the present invention, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When'include','have','consists of' and the like mentioned in the present specification are used, other parts may be added unless'only' is used. In the case of expressing the constituent elements in the singular, it includes the case of including the plural unless specifically stated otherwise.

In interpreting the constituent elements, it is interpreted as including an error range even if there is no explicit description.

In the case of a description of the positional relationship, for example, if the positional relationship of two parts is described as'upper','upper of','lower of','next to','right' Or, unless'direct' is used, one or more other parts may be located between the two parts.

In the case of a description of a temporal relationship, for example, when a temporal predecessor relationship is described as'after','following','after','before', etc.,'right' or'direct' It may also include cases that are not continuous unless this is used.

First, second, etc. are used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one component from another component. Accordingly, the first component mentioned below may be a second component within the technical idea of the present invention.

Each of the features of the various embodiments of the present invention can be partially or entirely combined or combined with each other, technically various interlocking and driving are possible, and each of the embodiments can be implemented independently of each other or can be implemented together in a related relationship. May be.

Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the drawings.

2 is a schematic plan view of an organic light emitting diode display according to an exemplary embodiment of the present invention.

As can be seen from FIG. 2, on the substrate 100, a pixel area (PA), a dummy pixel area (DPA), an electrostatic discharge (ESD), a gate driver 110, and data The driving unit 120 is formed.

In the pixel area PA, a plurality of pixels P are arranged in a horizontal direction and a vertical direction. Each of the plurality of pixels P includes a light emitting portion E that emits light and a circuit portion C that controls light emission of the light emitting portion E.

Although not specifically shown, the light emitting part E includes an anode, a cathode, and an organic layer formed between the anode and the cathode. The organic layer may include a hole injection layer, a hole transport layer, an emission layer, an electron transport layer, and an electron injection layer, but is not limited thereto. Further, the circuit unit C includes a gate wiring, a data wiring, a power wiring, a reference wiring, a switching thin film transistor, a driving thin film transistor, a sense thin film transistor, and a capacitor. The configuration of the circuit unit C may be changed in various forms known in the art.

The dummy pixel area DPA is formed to surround the pixel area PA. That is, as illustrated, the dummy pixel area DPA may be formed on a left outer, right outer, upper outer, and lower outer outer of the pixel area PA, but is not limited thereto.

A plurality of dummy pixels DP are formed in the dummy pixel area DPA. The dummy pixel DP functions to improve the pattern accuracy of the outermost pixel P of the pixel area PA. That is, the plurality of pixels P formed in the pixel area PA are formed by a plurality of pattern forming processes through a plurality of mask processes. In general, the outermost pixel P is formed during the mask process. Since it is difficult to precisely control the exposure amount, etc., it may be difficult to accurately form a pattern unlike other pixels P. Accordingly, by additionally forming the dummy pixel DP around the outermost pixel P in the pixel area PA, the dummy pixel DP becomes the outermost pixel, and accordingly, in the pixel area PA. The pattern precision of the outermost pixel P may be improved.

In addition, the dummy pixel DP also performs a function of minimizing the occurrence of damage in the pixel area PA due to static electricity or the like. That is, when the dummy pixel DP is formed at the outermost part, damage to the pixel P in the pixel area PA is reduced because damage is mainly applied to the dummy pixel DP even if a static electricity problem occurs. Can be.

The dummy pixel DP includes a dummy light emitting part DE and a dummy circuit part DC.

The dummy light-emitting part DE does not emit light unlike the light-emitting part E described above. For example, the dummy light emitting part DE may be configured not to emit light by not including at least one of an anode, a cathode, and an organic layer formed between the anode and the cathode. In particular, the dummy light emitting part DE may be configured not to emit light by not including an emission layer that performs a light emission function among the organic layers. However, it is not necessarily limited thereto, and the dummy light emitting part DE may include an anode, a cathode, and an organic layer formed between the anode and the cathode in the same manner as the light emitting part E. In this case, the dummy circuit part Some configurations have been deleted to prevent (DC) from functioning properly.

The dummy circuit part DC is connected to the dummy light emitting part DE. The dummy circuit unit DC, like the circuit unit C, may include a gate wiring, a data wiring, a power wiring, a reference wiring, a switching thin film transistor, a driving thin film transistor, a sense thin film transistor, and a capacitor, but the above configurations Any one of the configurations may be omitted. For example, the driving thin film transistor may be omitted in the dummy circuit unit DC. Further, the dummy circuit unit DC may not have a partial configuration of the driving thin film transistor, and thus may be configured to prevent the driving thin film transistor from performing its function.

When the pixel P is composed of a light emitting part E and a circuit part C from top to bottom, the dummy pixel P is also directed to a dummy light emitting part DE and a dummy circuit part DC from top to bottom. It is advantageous for controlling the pattern formation process to be configured. That is, in this case, the dummy light emitting part DE is formed between the circuit part C and the dummy circuit part DC.

The electrostatic discharge part ESD is formed to surround the dummy pixel area DPA outside the pixel area PA. That is, the electrostatic discharge unit ESD may be formed on a left outer side, a right outer side, an upper outer side, and a lower outer side of the dummy pixel area DPA, but is not limited thereto.

Such an electrostatic discharge unit (ESD) prevents static electricity from flowing into the pixel area PA by discharging static electricity generated during the manufacturing process, thereby preventing the circuit unit C in the pixel P from being damaged by static electricity. do.

The gate driver 110 is formed on one side of the substrate 100, for example, on the left side. The gate driver 110 may be formed on the left and right sides of the substrate 100, respectively. The gate driver 110 applies a gate signal to a gate line in the pixel area PA.

The gate driving unit 110 may be formed of a COG (Chip On Glass) structure in which a gate driving integrated circuit is mounted on the substrate 100, but is not necessarily limited thereto, and the gate driving integrated circuit is a flexible printed circuit film ( A structure mounted on a flexible printed circuit film) or a gate driving integrated circuit may be formed in a GIP (Gate In Panel) structure formed directly on the substrate 100.

The data driver 120 is formed on the other side of the substrate 100, for example, on the upper side. The data driver 120 may be formed on an upper side and a lower side of the substrate 100, respectively. The data driver 120 applies a data signal to a data line in the pixel area PA.

The data driving unit 120 may be formed of a COG (Chip On Glass) structure in which a data driving integrated circuit is mounted on the substrate 100, but is not limited thereto, and the data driving integrated circuit is a flexible printed circuit film ( Flexible printed circuit film) may be mounted on a structure.

According to the exemplary embodiment of the present invention, damage of the pixel area PA by static electricity is reduced by forming the dummy pixel area DPA between the pixel area PA and the electrostatic discharge unit ESD.

In particular, according to an embodiment of the present invention, since the dummy circuit unit DC is formed between the dummy light emitting unit DE and the electrostatic discharge unit ESD, the dummy circuit unit DC and the electrostatic discharge unit The ESDs are positioned adjacent to each other, and accordingly, static electricity may be generated between the dummy circuit unit DC and the electrostatic discharge unit ESD. However, according to an embodiment of the present invention, static electricity is generated between the dummy circuit unit DC and the electrostatic discharge unit ESD by changing the structure of the wiring that causes the generation of static electricity in the electrostatic discharge unit ESD. It can be prevented from occurring. This will be described in detail as follows.

3 is a plan view showing a dummy pixel and an electrostatic discharge unit according to an exemplary embodiment of the present invention, which shows four dummy pixels.

As can be seen from FIG. 3, in the organic light emitting diode display according to the exemplary embodiment of the present invention, gate wirings GL1 and GL2, data wirings DL1, DL2, DL3, and DL4, power wiring VDD, and reference wiring Ref ), a dummy pixel DP, and an electrostatic discharge unit ESD.

The gate wirings GL1 and GL2 include a first gate wiring GL1 and a second gate wiring GL2 arranged in a first direction, for example, in a horizontal direction. The first gate line GL1 is formed between the dummy light emitting unit DE and the dummy circuit unit DC constituting the dummy pixel DP, and the second gate line GL2 is the dummy pixel DP. It is formed between the dummy circuit part DC and the electrostatic discharge part ESD.

The first gate line GL1 and the second gate line GL2 are electrically connected to the dummy circuit unit DC, respectively. For example, the first gate wiring GL1 may be electrically connected to the switching thin film transistor of the dummy circuit unit DC, and the second gate wiring GL2 may be electrically connected to the sensing thin film transistor of the dummy circuit unit DC. Can be connected to.

The data lines DL1, DL2, DL3, and DL4 include a first data line DL1, a second data line DL2, a third data line DL3, and a third data line DL3 arranged in a second direction, for example, a vertical direction. It includes 4 data lines DL4. The first data line DL1 and the second data line DL2 are arranged adjacent to each other, and the third data line DL3 and the fourth data line DL4 are also arranged adjacent to each other. The data lines DL1, DL2, DL3, and DL4 supply a data voltage to the pixel P.

The first data line DL1, the second data line DL2, the third data line DL3, and the fourth data line DL4 are each electrically connected to the dummy circuit unit DC, specifically, It may be electrically connected to the switching thin film transistor of the dummy circuit part DC.

The power line VDD supplies power to a pixel (P in FIG. 2) and is arranged in the second direction, for example, in a vertical direction, and the second data line DL2 and the third data line DL3 It is formed between.

Since the power wiring VDD supplies power to each of the two pixels on the left and the two pixels on the right, it is electrically connected to a horizontal island-structured wiring (not shown) extending left and right, Such island-structured wiring may be electrically connected to each of the circuit units C, specifically, the driving thin film transistors of each of the circuit units C. The connection configuration between the power wiring VDD and the island-structured wiring may be equally applied to the dummy pixel DP.

The reference wiring Ref is arranged in the second direction, for example, in a vertical direction, and is formed on the left side of the first data line DL1 and on the right side of the fourth data line DL4.

Like the above-described power wiring VDD, the reference wiring Ref can be connected to each of the two pixels on the left and the two pixels on the right. To this end, a wiring of an island structure in a horizontal direction extending left and right (Not shown) is connected to the reference wiring Ref, and the island-structured wiring may be electrically connected to each of the circuit units C, specifically, the sensing thin film transistors of each of the circuit units C. The connection configuration between the reference wiring Ref and the island-structured wiring may be equally applied to the dummy pixel DP.

The sensing thin film transistor is for sensing a threshold voltage deviation of the driving thin film transistor that causes the image quality to deteriorate, and the sensing thin film transistor is in response to a sensing control signal supplied from the second gate line GL2. Current is supplied to the reference wiring Ref.

However, since the dummy pixel DP does not emit light, at least one of a switching thin film transistor, a driving thin film transistor, and a sensing thin film transistor may not be formed.

One dummy pixel DP is provided between the first data line DL1 and the reference line Ref, and another dummy pixel DP is provided between the second data line DL2 and the power line VDD. ) Is provided, another dummy pixel DP is provided between the power line VDD and the third data line DL3, and between the fourth data line DL4 and the reference line Ref Another dummy pixel DP is provided in FIG. According to this configuration, high potential power can be supplied to each of the four pixels P with one power line (VDD), and one reference line (Ref) can be connected to each of the four pixels (P). So that the total number of wirings is reduced.

However, the arrangement of the data lines DL1, DL2, DL3, and DL4, the power line VDD, and the reference line Ref is not necessarily limited to the structure shown in FIG. 3.

The dummy pixel DP includes a dummy light emitting part DE and a dummy circuit part DC. At this time, since the dummy circuit unit DC and the electrostatic discharge unit ESD are adjacent to each other, static electricity may be generated between the dummy circuit unit DC and the electrostatic discharge unit ESD. In particular, since the second gate wiring GL2 constituting the dummy circuit unit DC and the connection wiring 210 constituting the electrostatic discharge unit ESC are adjacent to each other, the second gate wiring GL2 and Static electricity may be generated between the connection wirings 210.

However, according to an embodiment of the present invention, by forming the connection wiring 210 separately from the pad link wiring 220, generation of static electricity between the second gate wiring GL2 and the connection wiring 210 is prevented. Can be reduced. It will be described in detail below.

For reference, in the drawings, the first and second gate wirings GL1 and GL2 and the dummy circuit unit DC are separately shown, but this is for convenience to distinguish the dummy circuit unit DC from the dummy light emitting unit DE. However, the first and second gate wirings GL1 and GL2 are constituent elements constituting the dummy circuit unit DC. The data wirings DL1, DL2, DL3, and DL4, the power wiring VDD, and the reference wiring Ref are similarly components constituting the dummy circuit unit DC.

The electrostatic discharge unit ESD includes a thin film transistor T and a connection wiring 210 connected to the thin film transistor T.

The thin film transistor T formed in the electrostatic discharge part ESD is formed corresponding to each dummy pixel DP. That is, the thin film transistor T is electrically connected to each of the four dummy pixels DP. However, when the dummy pixel DP is not formed, the thin film transistor T of the electrostatic discharge unit ESD is electrically connected to each of the four pixels P.

The thin film transistor T includes a gate electrode G, an active layer (not shown), a source electrode S, and a drain electrode D. The thin film transistor T may be formed in a bottom gate structure in which the gate electrode G is positioned under the active layer (not shown), and the gate electrode G is the active layer ( (Not shown) may be formed in a top gate structure.

The gate electrode G may be formed of the same material on the same layer as the first and second gate wirings GL1 and GL2.

The source electrode S is connected to the data lines DL1, DL2, DL3, and DL4. The source electrode S may be formed of the same material on the same layer as the data lines DL1, DL2, DL3, and DL4.

The drain electrode D is formed to face the source electrode S. The drain electrode D may be formed of the same material on the same layer as the source electrode S. The drain electrode D is electrically connected to the connection wiring 210. Since the drain electrode D and the connection wiring 210 are formed on different layers, the drain electrode D is connected to the connection wiring 210 through a third contact hole CH3.

The connection wiring 210 is for discharging static electricity, and is connected to the thin film transistor T and to the power wiring VDD at the same time. Therefore, static electricity flowing through the data lines DL1, DL2, DL3, and DL4 can escape through the high voltage power supply line VDD through the connection line 210 by switching of the thin film transistor T. have.

As described above, the connection wiring 210 is connected to the drain electrode D of the thin film transistor T through the third contact hole CH3. In addition, the connection wiring 210 is connected to the power wiring VDD through a first contact hole CH1. That is, since the connection wiring 210 and the power wiring VDD are formed on different layers, the connection wiring 210 and the power wiring VDD are electrically connected to each other through the first contact hole CH1. Connected. The connection wiring 210 may be formed of the same material on the same layer as the first and second gate wirings GL1 and GL2. Although only one first contact hole CH1 is shown in the drawing, a plurality of first contact holes CH1 may be formed for electrical connection between the connection line 210 and the power line VDD.

Since the connection wiring 210 serves to connect the drain electrode D of each thin film transistor T and the power wiring VDD, it extends in the left and right direction around the power wiring VDD region. do. Accordingly, as shown, it extends in the first direction, that is, in the horizontal direction parallel to the second gate wiring GL2.

Since the connection wire 210 extends in the horizontal direction, the connection wire 210 intersects a plurality of data wires DL1, DL2, DL3, and DL4 extending in the vertical direction. In this way, since one connection line 210 crosses the plurality of data lines DL1, DL2, DL3, and DL4, one connection line 210 is connected to a plurality of data lines ( It can be connected to DL1, DL2, DL3, and DL4, and accordingly, static electricity generated in the plurality of data lines DL1, DL2, DL3, and DL4 can be discharged through one connection line 210.

Meanwhile, since the connection wire 210 is formed to cross the data wires DL1, DL2, DL3, and DL4, the connection wire 210 and the data wires DL1, DL2, DL3, and DL4 are formed in both cross-regions. ), it is necessary to prevent generation of static electricity, and accordingly, a hole H is formed in an area of the connection line 210 that crosses the data lines DL1, DL2, DL3, and DL4. That is, the overlapping area between the connection wiring 210 and the data wirings DL1, DL2, DL3, and DL4 may be reduced by the hole H, so that generation of static electricity between them may be reduced.

The connection wiring 210 is formed in an island structure. Accordingly, the connection wiring 210 is spaced apart while facing the pad link wiring 220. The pad link wiring 220 serves to connect the power wiring VDD to a power pad (not shown). Accordingly, one end of the pad link wiring 220 is electrically connected to the power wiring VDD, and the other end of the pad link wiring 220 is connected to the power pad (not shown). Since the pad link wiring 220 and the power wiring VDD are formed on different layers, the pad link wiring 220 is electrically connected to the power wiring VDD through a second contact hole CH2. . Although only one second contact hole CH2 is shown in the drawing, a plurality of second contact holes CH2 may be formed for electrical connection between the pad link line 220 and the power line VDD.

The pad link wiring 220 may be formed of the same material on the same layer as the connection wiring 210. Accordingly, the first and second gate wirings GL1 and GL2, the connection wiring 210, and the pad link wiring 220 may all be formed of the same material on the same layer.

The connection wiring 210 and the pad link wiring 220 may be connected to each other. Rather, forming the connection wiring 210 and the pad link wiring 220 as one body may facilitate a pattern process. However, when the connection wiring 210 and the pad link wiring 220 are connected to each other, the charge charging in the connection wiring 210 increases, so that the The possibility of generating static electricity between the connection wiring 210 and the second gate wiring GL2 increases.

Accordingly, according to an embodiment of the present invention, the connection wiring 210 is formed in an island structure to separate the connection wiring 210 and the pad link wiring 220 so as to be spaced apart from each other. The amount of charge in the wiring 210 may be reduced, and accordingly, generation of static electricity may be prevented between the connection wiring 210 and the second gate wiring GL2 facing each other while being arranged side by side.

4 is a cross-sectional view of the line I-I of FIG. 3 according to an exemplary embodiment.

As can be seen in FIG. 4, the connection wiring 210 and the pad link wiring 220 are spaced apart from each other on the substrate 100, and the gate insulating layer 300 is formed on the connection wiring 210 and the pad link wiring 220. Is formed.

An etch stopper layer 400 is formed on the gate insulating layer 300, and the etch stopper layer 400 may be omitted in some cases.

A power line VDD is formed on the etch stopper layer 400. The power wiring VDD is connected to the connection wiring 210 and the pad link wiring 220, respectively. Specifically, the gate insulating layer 300 and the etch stopper layer 400 have a first contact hole CH1 formed therein so that the connection wiring 210 is exposed, and the power wiring VDD Is connected to the connection wiring 210 through the first contact hole CH1. In addition, the gate insulating layer 300 and the etch stopper layer 400 have a second contact hole CH2 formed therein so that the pad link wiring 220 is exposed, and the power wiring VDD is It is connected to the pad link wiring 220 through a second contact hole CH2.

A protective layer 500 is formed on the power line VDD, and a planarization layer 600 is formed on the protective layer 500.

In the above, the case where the dummy pixel DP is formed between the pixel P and the electrostatic discharge unit ESD has been described, but the present invention does not necessarily include the dummy pixel DP. That is, the present invention includes a case in which the dummy pixel DP is omitted so that the electrostatic discharge unit ESD is formed immediately outside the pixel P. In this case, the structure of the pixel P is similar to that of the dummy pixel P described above, except that all configurations necessary for light emission are included.

5 is a circuit diagram of a pixel P according to an exemplary embodiment of the present invention. The pixels described below are the gate wirings GL1 and GL2, the data wirings DL1, DL2, DL3, and DL4, the power wiring VDD, the reference wiring Ref, the switching thin film transistor, the driving thin film transistor, and the sensing thin film. This is an example including both a transistor and a capacitor.

As can be seen from FIG. 5, each pixel P is a first gate line GL1, a second gate line GL2, a data line DL, a power line VDD, a reference line Ref, and a switching thin film. A transistor T1, a driving thin film transistor T2, a sensing thin film transistor T3, a capacitor C, and an organic light emitting diode OLED are included.

The first gate wiring GL1 and the second gate wiring GL2 are arranged side by side in a first direction, for example, a horizontal direction.

The data line DL, the power line VDD, and the reference line Ref are arranged side by side in a second direction, for example, a vertical direction.

The switching thin film transistor T1 is connected to the first gate line GL1 and the data line DL, respectively. The switching thin film transistor T1 is switched according to a gate signal supplied to the first gate line GL1 to supply a data voltage supplied from the data line DL to the driving thin film transistor T2.

The driving thin film transistor T2 is connected to the switching thin film transistor T1 and the power line VDD, respectively. The driving thin film transistor T2 is switched according to the data voltage supplied from the switching thin film transistor T1 to generate a data current from the high potential power supplied from the power wiring VDD to the organic light emitting diode OLED. Supply.

The sensing thin film transistor T3 is connected to the driving thin film transistor T3, the second gate wiring GL2, and the reference wiring Ref, respectively. The sensing thin film transistor T3 is for sensing a threshold voltage deviation of the driving thin film transistor T2 that causes image quality deterioration, and the sensing of the threshold voltage deviation is performed in a sensing mode. The sensing thin film transistor T3 supplies the current of the driving thin film transistor T2 to the reference line Ref in response to a sensing control signal supplied from the second gate line GL2.

The capacitor C is connected to a gate terminal and a source terminal of the driving thin film transistor T2, respectively. The capacitor C maintains the data voltage supplied to the driving thin film transistor T2 for one frame.

The organic light emitting diode OLED is connected to the driving thin film transistor T2 and the low potential power supply VSS, respectively. The organic light emitting diode OLED emits light according to a data current supplied from the driving thin film transistor T2.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not necessarily limited to these embodiments, and various modifications can be made without departing from the spirit of the present invention. Accordingly, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but to explain the technical idea, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not limiting. The scope of protection of the present invention should be interpreted by the claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: substrate 110: gate driver
120: data driver 210: connection wiring
220: pad link wiring 300: gate insulating film
400: etch stopper layer 500: protective film
600: planarization film

Claims (7)

A pixel formed in a pixel area on the substrate;
A power line supplying power to the pixel;
A data line supplying a data voltage to the pixel; And
Comprising an electrostatic discharge unit formed outside the pixel area,
The electrostatic discharge unit includes a connection wiring for discharging static electricity and a thin film transistor connected to the connection wiring,
The connection wiring is formed in an island structure,
The connection wire is connected to the power wire through a first contact hole. delete The method of claim 1,
Further comprising a pad link wiring connected through the power wiring and the second contact hole,
The connection wire is spaced apart from the pad link wire. The method of claim 1,
The connection wiring is formed to cross the data line, and a hole is formed in an area of the connection line crossing the data line. The method of claim 4,
The connection wiring crosses a plurality of data wirings. The method of claim 1,
The thin film transistor includes a source electrode connected to the data line and a drain electrode connected to the connection line through a third contact hole. The method of claim 1,
An organic light-emitting display device in which a dummy pixel is additionally formed between the pixel and the electrostatic discharge part.

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