KR20120087113A - ESD structure for low capacitance and high speed - Google Patents
ESD structure for low capacitance and high speed Download PDFInfo
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- KR20120087113A KR20120087113A KR1020120073213A KR20120073213A KR20120087113A KR 20120087113 A KR20120087113 A KR 20120087113A KR 1020120073213 A KR1020120073213 A KR 1020120073213A KR 20120073213 A KR20120073213 A KR 20120073213A KR 20120087113 A KR20120087113 A KR 20120087113A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
Abstract
Description
본 발명은 반도체 집적회로에 관한 것으로, 특히 정전방전(ESD; Electro static Discharge) 현상으로부터 집적회로의 내부소자를 보호하기 위한 ESD 보호 회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor integrated circuits, and more particularly, to an ESD protection circuit for protecting internal elements of an integrated circuit from an electrostatic discharge (ESD) phenomenon.
반도체 집적회로에서 집적도가 증가할수록 소스와 드레인의 채널길이는 줄어들게 되며, 그에 의한 의도하지 않은 전기적 현상이 발생하는데, 예를 들면 ESD 특성 악화, 핫 캐리어 효과(hot carrier effect), 펀치 쓰루(punch-through) 등이다.In semiconductor integrated circuits, as the degree of integration increases, the channel lengths of the source and drain decrease, resulting in unintended electrical phenomena, such as deterioration of ESD characteristics, hot carrier effects, and punch-through. through).
정전기에 의한 정전방전(Electrostatic Discharge)에는 크게 두가지 종류가 있다. 첫째가 디바이스가 패키지(Package) 형태로 어떠한 테스트 장비 등에 장착될 때 그 장비의 접지 상태가 불안정하여 발생하는 정전기로 전압은 약 200V로 낮으나 임피던스가 작아서 전하량은 상대적으로 많은 경우(Machine Model)이며, 두번째는 디바이스가 사용자의 손에 닿을 때 인체에 유기되어 있던 정전기가 방전되는 형태로 약 2000V의 고전압이나 큰 임피던스를 통해서 방전되어 낮은 전하량을 가지는 경우(Human Body Model)이다.There are two main types of electrostatic discharge. First, when the device is installed in any test equipment in the form of package, the static electricity generated by unstable ground state of the equipment is about 200V but the impedance is small, so the amount of charge is relatively high (Machine Model). The second case is when the device touches the user's body and discharges the static electricity that has been induced in the human body, and discharges it through a high voltage of about 2000V or a large impedance (Human Body Model).
이러한 정전기에 노출되면 MOS 디바이스는 게이트 옥사이드 파괴(gate oxide rupture), 접합 파괴(junction spiking) 등의 현상이 발생하여 디바이스가 완전히 파괴되거나 혹은 미세하게 데미지(damage)를 받아 소자 신뢰도(reliability)에 심각한 영향을 준다.When exposed to such static electricity, MOS devices may experience gate oxide rupture, junction spiking, or the like, resulting in complete device destruction or minor damage, resulting in severe device reliability. affect.
따라서 정전기의 유입에 따른 파괴로부터 집적회로를 보호하기 위하여 집적회로 내부와 외부와의 연결부위에 ESD 보호회로를 삽입한다. 정전기 방전은 ESD 보호회로에 의해 접지선(ground line) 또는 Vcc선을 통해 제거되며, 내부회로는 안전하게 되는 것이다.Therefore, in order to protect the integrated circuit from destruction due to the inflow of static electricity, an ESD protection circuit is inserted at the connection portion between the inside and the outside of the integrated circuit. Electrostatic discharge is removed through the ground line or the Vcc line by the ESD protection circuit, and the internal circuit is safe.
그러나, 종래의 기술로 ESD 보호회로를 구성할 경우, 단위 크기당의 ESD 특성이 좋지 않아, 전체 면적이 커지게 된다.However, when the ESD protection circuit is constructed by the conventional technology, the ESD characteristics per unit size are not good, and the total area becomes large.
위와 같이 많은 면적이 필요한 것을, 적은 면적에서 양호한 특성을 얻는 구조로 변경하여, ESD 에 안전한 집적회로를 공급하는 데 있다.In order to provide a safe integrated circuit for ESD by changing a structure requiring a large area as described above to obtain good characteristics in a small area.
상기 목적을 달성하기 위한 본 발명의 ESD 보호회로는, 자신의 게이트를 가지고, 접지전압단에 한쪽 접합이 연결된 NMOS트랜지스터, 한쪽은 NMOS트랜지스터의 게이트에 다른 출력단은 PMOS트랜지스터의 게이트로 연결이 되는 인버터(Inverter), 게이트의 한쪽은 인버터에 연결이 되고 한쪽은 NMOS에 연결이 되며 다른 한쪽은 패드에 연결이 되는 PMOS 트랜지스터를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the ESD protection circuit of the present invention includes an NMOS transistor having its own gate and one junction connected to the ground voltage terminal, one of which is connected to the gate of the NMOS transistor and the other output terminal to the gate of the PMOS transistor. (Inverter), one side of the gate is connected to the inverter, one side is connected to the NMOS, and the other side is characterized in that it comprises a PMOS transistor connected to the pad.
또한 본 발명의 ESD 보호회로는 P형 기판; 상기 P형 기판 내의 일부영역에 형성된 N웰; 상기 P형 기판에 형성되며, 접지전도라인이 콘택되는 N+ 소스접합, N+ 드레인접합 및 게이트 폴리실리콘을 포함하는 NMOS트랜지스터; 상기 N웰영역의 기판에 형성되며, 상기 NMOS트랜지스터의 N+ 소스접합에 접하여 형성된 P+ 드레인접합, P+ 소스접합 및 게이트 폴리실리콘을 포함하는 PMOS트랜지스터; 상기 PMOS트랜지스터의 P+소스접합에 접하여 형성되며 패드 전도 라인이 콘택되는 N+ 접합; 및 상기 PMOS 및 NMOS 트랜지스터의 각 게이트 폴리실리콘과, 소스/드레인 접합으로 구성되는 것을 특징으로 한다.In addition, the ESD protection circuit of the present invention is a P-type substrate; An N well formed in a portion of the P-type substrate; An NMOS transistor formed on the P-type substrate and including an N + source junction, an N + drain junction, and a gate polysilicon to which a ground conductive line is contacted; A PMOS transistor formed on a substrate of the N well region and including a P + drain junction, a P + source junction, and a gate polysilicon formed in contact with an N + source junction of the NMOS transistor; An N + junction formed in contact with the P + source junction of the PMOS transistor and having a pad conducting line contacted thereto; And each gate polysilicon of the PMOS and NMOS transistors, and a source / drain junction.
상기와 같이 이루어진 본 발명은, ESD 보호 회로를 포함하는 집적회로가 적은 면적을 차지하면서도 좋은 ESD 보호 특성을 얻는 효과가 있다.According to the present invention, the integrated circuit including the ESD protection circuit occupies a small area and has an effect of obtaining good ESD protection characteristics.
또한, ESD보호 트랜지스터인 NMOS트랜지스터의 드레인 영역에 PMOS트랜지스터의 삽입으로 인해, 정상적인 동작상황에서 턴온(Turn-On)된 PMOS트랜지스터의 적은 저항으로 특성저하를 방지하면서도 ESD에 양호한 회로 및 구조를 얻을 수 있다.In addition, due to the insertion of the PMOS transistor into the drain region of the NMOS transistor, which is an ESD protection transistor, a low resistance of the turned-on PMOS transistor under normal operation prevents deterioration of the characteristics and provides a good circuit and structure for ESD. have.
도 1은 일반적인 NMOS트랜지스터를 이용하여 ESD 보호를 하는 하는 종래기술의 회로
도 2는 본 발명에 따른 ESD 보호회로의 구성을 개념적으로 나타낸 도면.
도 3 본 발명에 따른 EDS 보호 회로의 평면도 및 단면도.
도 4 본 발명에 따른 EDS 보호 회로의 평면도 및 단면도.1 is a circuit of the related art for ESD protection using a general NMOS transistor
2 conceptually illustrates a configuration of an ESD protection circuit according to the present invention;
3 is a plan view and a sectional view of an EDS protection circuit according to the present invention.
4 is a plan view and a sectional view of an EDS protection circuit according to the present invention.
본 발명의 EDS 보호회로에서는, PMOS트랜지스터의 게이트는 NMOS트랜지스터의 게이트에서 인버터를 통해서 연결하여, 정상적인 동작시는 PMOS트랜지스터가 턴온(Turn-On)되어 PMOS트랜지스터를 통한 작은 저항을 형성하나, ESD 상황에서는 PMOS트랜지스터가 턴오프(Turn-Off)되어 PMOS트랜지스터 하단의 N웰을 통한 패스(Path)가 형성되어 큰 저항을 얻는 구조이다. 따라서 ESD 상황에서는 외부에서 들어오는 전류가 N웰을 통해서 지나므로, 필요한 저항을 N웰을 통해서 얻을 수 있는 구조이다.In the EDS protection circuit of the present invention, the gate of the PMOS transistor is connected through the inverter at the gate of the NMOS transistor, and during normal operation, the PMOS transistor is turned on to form a small resistance through the PMOS transistor, but in an ESD situation In the PMOS transistor, the PMOS transistor is turned off to form a path through the N well at the bottom of the PMOS transistor, thereby obtaining a large resistance. Therefore, in the ESD situation, since the external current flows through the N well, the necessary resistance can be obtained through the N well.
본 발명의 기술적 사상은 살리사이드 공정에 의해 NMOS 트랜지스터(231)의 드레인영역에서 저항이 낮아지더라도 이를 PMOS트랜지스터(232)에 의해 보상하는 방식이다.The technical idea of the present invention is to compensate for this by the PMOS transistor 232 even if the resistance in the drain region of the NMOS transistor 231 is lowered by the salicide process.
PMOS 트랜지스터는 게이트가 인버터를 통해서 NMOS트랜지스터의 게이트에 접속되어 있는 바, 정상동작에서는 PMOS트랜지스터가 턴온(Turn-On) 되나, ESD 상황하에서는 PMOS트랜지스터가 턴오프(Turn-Off)되어 PMOS트랜지스터의웰을 통한 저항에 의해서 NMOS 트랜지스터의 드레인 저항은 커지게 된다.In the PMOS transistor, the gate is connected to the gate of the NMOS transistor through the inverter. In normal operation, the PMOS transistor is turned on.However, under the ESD situation, the PMOS transistor is turned off and the well of the PMOS transistor is turned off. The resistance through the NMOS transistor increases the drain resistance.
Claims (2)
입력단이 상기 NMOS트랜지스터의 게이트단에 연결되는 인버터(Inverter); 및
상기 NMOS트랜지스터와 외부 접합 패드 사이에 연결되며 게이트가 상기 인버터의 출력단에 연결되는 PMOS트랜지스터를 포함하는 것을 특징으로 하는 반도체 집적회로의 ESD 보호회로.An NMOS transistor having a gate connected to a protected integrated circuit and having one junction connected to a ground voltage terminal;
An inverter having an input terminal connected to the gate terminal of the NMOS transistor; And
And a PMOS transistor connected between the NMOS transistor and an external junction pad and whose gate is connected to an output terminal of the inverter.
상기 PMOS트랜지스터는,기판의 표면 하부에 형성된 N웰;상기 N웰 내의 기판의 표면 하부에 형성된 소스/드레인 접합;상기 N웰의 기판 상부에 형성된 게이트 폴리실리콘; 및 상기 폴리실리콘 및 상기 소스/드레인 접합 상에 형성된 실리사이드층을 포함하여 이루어짐을 특징으로 하는 반도체 집적회로의 ESD 보호회로.The method of claim 1,
The PMOS transistor includes: an N well formed under the surface of the substrate; a source / drain junction formed under the surface of the substrate in the N well; a gate polysilicon formed over the substrate of the N well; And a silicide layer formed on the polysilicon and the source / drain junction.
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| KR1020120073213A KR20120087113A (en) | 2012-07-05 | 2012-07-05 | ESD structure for low capacitance and high speed |
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| KR1020050017927A Division KR101369194B1 (en) | 2005-03-03 | 2005-03-03 | Esd protection circuit for semiconductor integrated circuit |
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