KR20120074572A - Timing controller and its driving method and liquid crystal display using the same - Google Patents

Abstract

PURPOSE: A timing controller and driving method thereof and liquid crystal display using the same is provided to improve quality deterioration due to an abnormal line counter by setting a horizontal blank value between a 1' signal and 1'' signal of a first line of a first frame as a minimum value. CONSTITUTION: A panel(102) includes liquid crystal molecules loaded between two glass substrates. A timing controller(114) generates a controlling signal to control an operation timing of a data driver(106) and gate driver. The timing controller provides digital video data inputted from a system(112) to a data driver. The timing controller includes a receiving unit(114a), image signal array unit(114b) and control signal generating unit(114c). A gate driver is driven by a GIP(Gate In Panel) method formed on panel.

Description

TIMING CONTROLLER AND ITS DRIVING METHOD AND LIQUID CRYSTAL DISPLAY USING THE SAME}

The present invention relates to a timing controller, and more particularly, to a timing controller for generating an internal data enable (Interna DE) signal in a no signal mode and a liquid crystal display using the same.

The liquid crystal display device displays an image by adjusting light transmittance of liquid crystal cells according to a video signal.

1 is an exemplary diagram illustrating an equivalent circuit of a pixel included in a liquid crystal display panel of a general liquid crystal display device.

The active matrix type liquid crystal display device actively converts data by switching data voltages supplied to the liquid crystal cells by using a thin film transistor (TFT) formed for each liquid crystal cell (Clc) as shown in FIG. 1. By controlling, the display quality of a moving image can be improved. In FIG. 1, reference numeral “Cst” denotes a storage capacitor Cst for maintaining the data voltage charged in the liquid crystal cell Clc, “D1” denotes a data line to which a data voltage is supplied, and “G1” denotes Each means a gate line to which a scan voltage is supplied.

Such a liquid crystal display receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and an image signal RGB from the system. The timing controller may include a data control signal DCS for controlling a data driver and a gate control signal for controlling a gate driver using the timing signals (a vertical synchronization signal, a horizontal synchronization signal, and a data enable signal). GCS) is generated and transmitted to the data driver and the gate driver, respectively, and the video signals are rearranged and transmitted to the data driver.

2 is a diagram illustrating waveforms of a vertical synchronization signal and a data enable signal of a general liquid crystal display.

As the signals input to the timing controller of the liquid crystal display, as shown in FIG. 2, the vertical synchronization signal Vsync is inputted in one frame and the horizontal synchronization signal Hsync is provided in one horizontal line (not shown). ) And a data enable signal DE that indicates the input of data.

Here, in the vertical synchronization signal Vsync, a vertical blank period during which data is not applied for a predetermined period of time after the data of the last gate line of the frame is output and before the data of the first gate line of the next frame is output. Occurs, and other sections are called active periods.

The data enable DE signal periodically forms a pulse during the active period of the vertical synchronization signal, and an image signal is input to the data line during one horizontal period 1H according to the data enable signal.

Here, the timing controller does not use the data enable signal transmitted from the system as it is, but processes the data enable signal according to the characteristics of the panel. Able signal (hereinafter, simply referred to as 'internal DE signal') is used.

3 is a waveform diagram illustrating a method of generating an internal DRD DE signal in a no signal mode in a conventional DRD type liquid crystal display.

Recently, as one of the measures to reduce the number of data drive ICs in liquid crystal display devices, the number of data drive ICs required is reduced by halving the number of data lines instead of doubling the number of gate lines compared to the conventional one. A double rate driving (DRD) driving method that implements the same resolution while reducing halving is being developed as shown in FIG. 3.

As described above, the timing controller generates and uses an internal DE signal by using the DE signal transmitted from the system.

Meanwhile, even when the panel is changed from a signal mode to a no signal mode, the timing controller continuously generates an internal DRD DE signal as shown in FIG. 3, thereby causing an abnormality of the panel due to an abnormal line counter. Charging and resulting panel quality deterioration is improving.

First, referring to FIG. 3A, a method of generating a conventional general internal data enable signal when changing from a signal mode to a no signal mode will be described. Hereinafter, a method of determining the horizontal blank value of the internal DRD DE in the first horizontal line of the current frame, which is the first frame after the change to the no signal mode, will be described.

In general, when changing to the no signal mode, the timing controller cannot know the horizontal blank value t2 of the first signal of the internal DE of the current frame. Therefore, when the timing controller changes to the no signal mode, the timing controller temporarily stores the last blank horizontal value t1 of the last frame of the previous frame.

On the other hand, because of the DRD driving, the timing controller sets the blank value t3 between the first 'signal and the first " signal among the internal DRD DE signals to a 1/2 value of t1.

In addition, the remaining value except for the value used for t3 among the horizontal blank value t2 of the internal DE is set as the horizontal blank value t4 between the first and second signals. The horizontal blank value between the second 'signal', the second 'signal', the third 'signal', and the third 'signal generated thereafter is set to an internal value of 1/2 of the horizontal blank value t2.

On the other hand, in the conventional liquid crystal display device, the following problems are applied when changing to the no signal mode by applying the above-described method, that is, when the system mode change, the horizontal blank value between the frames (horizontal) Due to the rapid change in the blank value, the GIP gate clock is broken for one frame.

That is, it can be seen that the video signal source of the timing controller is normal at the time when the mode change occurs, but the GIP gate clock is broken for one frame.

At this time, because the GIP gate clock is broken, red / blue is charged to black and green / blue is charged to white.

Also, due to green / blue charging with white, gray level of (0, 255, 255) is displayed on the LCM.

On the other hand, as described above, the phenomenon that the gate clock for driving the GIP is broken is caused because the timing controller does not normally increase the line counter, as shown in (b) or (c) of FIG. 3.

That is, if the previous frame's horizontal blank value t1 is significantly greater than the current frame's horizontal blank value t2, for example, if the differential value exceeds 32, As shown in FIG. 3 (b), the pulse width of the first '' signal is less than one-half the length of the first signal pulse width, so that it is horizontal between the first '' signal and the second 'signal. The blank is not formed, which may cause a breakage of the gate control signal. In other words, when the horizontal blank value t1 of the immediately preceding frame is considerably larger than the horizontal blank value t2 between the first signal and the second signal, the horizontal blank value between the first 'signal and the first' 'signal is (t3) may be set normally since it is set to 1/2 of t1, but a relatively small value of the horizontal blank value t4 between the first '' signal and the second 'signal having a value of t2-t3 is relatively small. As shown in (b) of FIG. 4, the horizontal blank value between the first " and second " signals is zero or has a very small value, in which case the timing controller has an internal DRD. The DE cannot be counted, so the counter cannot be incremented normally, which causes problems.

In addition, if the previous frame's horizontal blank (t1) is significantly smaller than the current frame's horizontal blank (t2), for example, the differential value is 32. If greater, the area of the horizontal blank value t4 between the first '' and second 'signals is greater than the max value (1366/2 @ LC185) guaranteed by the timing controller, causing the timing controller to make this vertical blank. The gate control signal is broken by recognizing it as a section and resetting the counter.

That is, in the conventional timing controller as described above, the value t3 between the first 'signal and the first " signal of the internal DRD DE is determined as the horizontal blank value of the last-1th of the last frame. If the value of t4 becomes too small by using (Horizontal blank value) t1 and using the value t4 between the first '' signal and the second 'signal as the t2-t3 value, As shown in (b), the gap between the first '' signal and the second 'signal becomes narrow, so that the timing controller cannot count the internal DRD DE, and the value of t4 becomes too large. As shown in c), there is a problem that the distance between the first '' signal and the second 'signal is widened and the timing controller recognizes this as a vertical blank period and resets the internal DRD DE.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and when changing from the DRD driving method to the no signal mode, a horizontal blank between the first 'signal' and the first 'signal of the first line of the first frame of the internal DRD DE It is a technical object of the present invention to provide a timing controller, a method of driving the same, and a liquid crystal display device using the same, which sets the value to the minimum value available as the horizontal blank value.

In accordance with another aspect of the present invention, a timing controller includes: a receiver configured to receive an image signal, a synchronization signal, and a data enable (DE) signal from a system; A data alignment unit for rearranging the video signals and transmitting the data signals to a data driver; A control signal generator for generating a control signal using the synchronization signal and transmitting the generated control signal to a data driver and a gate driver; And the horizontal blank value between the first 'signal' and the first 'signal' of the first line of the first frame among the no-signal mode internal DRD data enable signals when changing from the signal mode to the no signal mode. And an internal DRD data enable signal generator configured to set the minimum value possible.

The liquid crystal display device using the timing controller according to the present invention for achieving the above technical problem, the timing controller; panel; A data driver for controlling a data line formed in the panel according to the control of the timing controller; And a gate driver for controlling the gate line formed in the panel according to the control of the timing controller.

The timing controller driving method according to the present invention for achieving the above-described technical problem, when changing from the signal mode to the no signal mode, the first 'of the first line of the first frame of the first DRD data enable signal of the no signal mode; Setting a horizontal blank value between the signal and the first " " signal to a minimum value available as the horizontal blank value; And a horizontal blank value between the first '' signal and a second 'signal input thereafter, the horizontal blank value between the first signal and the second signal of the no signal mode internal data enable signal, wherein the minimum value is the minimum value. Setting to the value of minus.

According to the above solution, the present invention provides the following effects.

That is, the present invention uses the horizontal blank value between the first 'signal' and the first 'signal' of the first line of the first frame of the internal DRD DE as the horizontal blank value when changing from the DRD driving method to the no signal mode. By setting the minimum value as possible, it can improve the image quality deterioration caused by abnormal line counter caused by changing the panel from signal mode to no signal mode.

1 is an exemplary diagram illustrating an equivalent circuit of a pixel included in a liquid crystal display panel of a general liquid crystal display device.
2 is a diagram illustrating waveforms of a vertical synchronization signal and a data enable signal of a general liquid crystal display.
3 is a waveform diagram illustrating a method of generating an internal DRD DE signal in a no signal mode in a conventional DRD type liquid crystal display.
4 is an exemplary view showing a configuration of a liquid crystal display according to the present invention.
5 is an exemplary view showing a panel configuration of a liquid crystal display according to the present invention, an exemplary view showing a configuration of a panel driven by a DRD method.
6 is a flow diagram of an embodiment of a timing controller driving method according to the present invention;
7 is an exemplary view showing waveforms of a DRD DE signal of a liquid crystal display according to the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

4 is an exemplary view showing a configuration of a liquid crystal display according to the present invention. 5 is an exemplary view showing a panel configuration of a liquid crystal display device according to the present invention, and is an exemplary view showing a configuration of a panel driven by a DRD method.

As shown in FIG. 4, the liquid crystal display according to the present invention includes a panel 102, a timing controller 114, a data driver 106, and a gate driver.

The panel 102 includes liquid crystal molecules dropped between two glass substrates. In this panel, m × n liquid crystal cells Clc are arranged in a matrix by a cross structure of the data lines D1 to Dm and the gate lines G1 to Gn.

The lower glass substrate of the panel includes m data lines D1 to Dm, n gate lines G1 to Gn, TFTs, pixel electrodes of the liquid crystal cell Clc connected to the TFT, and a storage capacitor Cst. Etc. are formed.

The black matrix, the color filter and the common electrode are formed on the upper glass substrate of the panel. The common electrode is formed on the upper glass substrate in a vertical electric field driving method such as twisted nematic (TN) mode and vertical alignment (VA) mode, and a horizontal electric field such as IPS (In Plane Switching) mode and FFS (Fringe Field Switching) mode. The driving method is formed on the lower glass substrate together with the pixel electrode. A polarizing plate having an optical axis orthogonal to each other is attached to the upper glass substrate and the lower glass substrate of the panel, and an alignment layer for setting the pretilt angle of the liquid crystal is formed on the inner surface in contact with the liquid crystal.

Meanwhile, the panel applied to the present invention is configured in a double rate driving (hereinafter, simply referred to as 'DRD') method as illustrated in FIG. 5.

That is, in the liquid crystal display according to the present invention, m (m is a natural number of two or more) liquid crystal cells disposed on one horizontal line of the panel, as shown in FIG. 5, two gate lines and m / 2 data. The DRD method is driven using lines.

In order to minimize flicker and reduce power consumption, the DRD method drives a data driver IC of a data driver in a vertical two-dot inversion method. Thus, two liquid crystal cells adjacent to each other with a data line interposed therebetween. It is connected to the gate lines of each to charge the data voltage of the same polarity supplied through the data line.

For example, in a specific frame, among the liquid crystal cells disposed on the first horizontal line HL1, the R liquid crystal cell and the G liquid crystal cell shared in the first data line DL1 are separated from the gate lines GL1 and GL2. The R liquid crystal cell and the B liquid crystal cell shared in the positive polarity are sequentially charged in synchronization with the scan pulse supply time, and are negative in synchronization with the scan pulse supply time from the gate lines GL1 and GL2. The B liquid crystal cell and the G liquid crystal cell which are sequentially charged with polarity and are shared with the third data line DL3 are sequentially charged with positive polarity in synchronization with the scan pulse supply points from the gate lines GL1 and GL2.

Here, the R liquid crystal cell, the G liquid crystal cell, the G liquid crystal cell, and the B liquid crystal cell shared in the first data line D1 and the second data line among the first horizontal lines are driven by the first 'signal of the internal DRD DE signal. The R positive cell and the B liquid crystal cell shared in the second data line D2 may be driven by the first ″ signal of the internal DRD DE signal.

The timing controller 114 receives timing signals such as vertical / horizontal synchronization signals (Vsync, Hsync), data enable, clock signal CLK, and the like to operate the data driver 106 and the gate driver 104. Generate control signals for controlling timing. These control signals include a gate start pulse (GSP), a gate shift clock signal (GSC), a gate output enable signal (GOE), and a source start pulse (SSP). , A source sampling clock (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like.

In addition, the timing controller rearranges the digital video data RGB (hereinafter, simply referred to as an image signal) input from the system 112 to the panel 102 and supplies the data driver 106 to the data driver 106. To this end, the timing controller includes a receiver 114a for receiving an image signal, a synchronization signal, and a data enable (DE) signal from the system 112, an image signal alignment unit 114b for rearranging the image signals, and transmitting the same to the data driver. An internal DRD DE signal generator for generating a data control signal DCS and a gate control signal GCS, and transmitting the data control signal DCS and the gate driver signal to the data driver and the gate driver, respectively, and the internal DRD DE signal. 114d).

That is, the timing controller according to the present invention includes two internal DRD DE signals generated to drive the first horizontal line among the internal DRD DE signals when the signal mode is changed from the signal mode to the no signal mode. In order to set the horizontal blank value of the first signal and the first signal, the timing controller includes an internal DRD DE generator 114d as illustrated in FIG. 4. The function of the internal DRD DE generator 114d is described in detail below with reference to FIGS. 6 and 7.

The data driver 106 consists of a number of gate drive ICs (not shown) including shift registers, first and second latches, digital-to-analog converters and output buffers that are cascaded between the input and data lines. . The data driver latches data RGB under the control of the timing controller 114 and converts the data into an analog positive / negative gamma compensation voltage to generate a positive / negative data voltage and convert the data voltage to a data line. To Dl to Dm.

Finally, the gate driver includes a shift register, a level shifter for converting the output signal of the shift register into a swing width suitable for TFT driving of the liquid crystal cell, and an output buffer connected between the level shifter and the gate lines GL1 to GLn, respectively. A plurality of gate drive integrated circuits sequentially output scan pulses having a pulse width of approximately one horizontal period to the gate lines.

Meanwhile, as shown in FIG. 4, the gate driver applied to the present invention is driven by a gate in panel (GIP) method.

6 is a flowchart illustrating an embodiment of a timing controller driving method according to the present invention. FIG. 7 is an exemplary diagram illustrating a waveform of a DRD DE signal of the liquid crystal display according to the present invention.

The liquid crystal display according to the present invention utilizes a data enable signal DE (hereinafter, simply referred to as 'DE') received from the system 114 to internally drive an internal DE signal that can actually drive a panel. Create

In addition, the liquid crystal display according to the present invention is driven by the DRD method as described above, and for this purpose, the internal DRD DE signal generator 114d of the timing controller actually drives the DRD method panel using the internal DE signal. Generates an internal DRD DE signal that can be generated.

Meanwhile, when the panel is changed from a signal mode to a no signal mode, the timing controller according to the present invention improves abnormal charging of the panel due to an abnormal line counter and deterioration of image quality of the panel. In this case, the no signal mode means that when a main body and a monitor are connected with a connection cable, such as a desktop computer, a video signal transmitted from the main body to the monitor is suddenly blocked, for example, when the connection cable is disconnected while the main body is being driven. If so, say.

That is, the no signal mode refers to a state in which video signals and various timing signals are not transmitted from the system (main body of the desktop computer).

At this time, the timing controller according to the present invention generates the DRD DE signal inside the no signal mode and drives the panel through the method as shown in FIGS. Image deterioration can be prevented.

First, in FIG. 7, the previous frame shows the waveforms of the internal DE signal and the internal DRD DE signal in the signal mode, and the current frame shows the internal DE signal and the internal DRD DE signal in the no signal mode. It shows the waveform of.

As described above, the internal DRD DE signal generator 114d of the timing controller generates an internal DE signal usable by the panel using the DE signal transmitted from the system. In particular, in the case of the present invention, the DRD method is used. Therefore, the internal DRD DE signal is generated together with the internal DE signal.

That is, the internal DRD DE signal generator 114d of the timing controller generates the signal mode internal DE and the signal mode internal DRD DE while receiving the DE signal and the video signal from the system, and according to the signal mode internal DRD DE Is applied to the corresponding horizontal line of the panel so that the image is output.

Also, the internal DRD DE signal generator generates a no signal mode internal DE signal and a no signal mode internal DRD DE signal even in a no signal mode in which a DE signal and an image signal are not received from the system.

Here, the DE signal in the no signal mode includes a plurality of DE pulses (first signal, second signal ...), as shown in FIG. 7, to drive one data line. The DRD DE signal is one DE pulse of the no signal mode internal DE signal divided into two DRD DE pulses (first 'signal, first' signal).

At this time, for example, the first 'signal' is the R liquid crystal cell and the G liquid crystal cell shared on the first data line D1 on the first line of the panel (hereinafter, simply referred to as 'first horizontal line') in FIG. 5. The first '' signal may be a signal for driving the R positive cell and the B liquid crystal cell shared in the second data line D2 in the first horizontal line.

In addition, the second 'signal is used to drive the R liquid crystal cell and the G liquid crystal cell shared in the first data line D1 on the second line of the panel (hereinafter, simply referred to as' second horizontal line') in FIG. 5. Signal, and the second '' signal may be a signal for driving the R positive cell and the B liquid crystal cell shared in the second data line D2 in the second horizontal line.

On the other hand, if the video signal is not transmitted from the system due to the disconnection of the connection cable and the like is changed to the no signal mode, the timing controller first starts the signal mode immediately before the change to the no signal mode. In step 602, the last-first horizontal blank value (t1 of FIG. 7) of the signal mode internal DE signal is checked and temporarily stored (602).

Next, after the internal DRD DE signal generator 114d is changed to the no signal mode, the internal DRD DE signal generator 114d arbitrarily generates the no signal mode internal DE signal even if the DE is not received from the system. Since the signal mode internal DRD DE signal is generated, the internal DRD DE signal generator determines whether the input no signal mode internal DRD DE signal is the first 'signal to be applied to the first horizontal line (604). ).

This determination may be determined using whether there is a vertical blank period, which is a predetermined time interval between the previous frame and the current frame. That is, the timing controller determines that there is a vertical blank period of the internal DE between the signal mode and the no signal mode, as the first signal, and if there is no vertical blank period, the timing controller determines the second signal or the subsequent signal. You can judge by.

When the determination result 604 determines that the first signal of the DRD DE in the no signal mode is internal, the timing controller determines a horizontal blank value t3 between the first signal and the first signal. The minimum horizontal blank value is set among the available horizontal blank values (606).

For example, if the horizontal blank value of the signal mode internal DE signal varies between 64 and 32, the timing controller may determine a horizontal blank value ((Horizontal blank value) (t3) between the first 'signal and the first' 'signal. Can be set to 32, the minimum horizontal blank value.

In addition, with respect to the first '' signal coming after the first 'signal, the horizontal blank value t4 of the corresponding signal is used in the horizontal blank value t2 between the first signal and the second signal of the DE signal in the no signal mode. The value obtained by subtracting t3 is set to a horizontal blank value t4 of the corresponding signal (608).

When the determination result 604 determines that the signal is not the first 'signal of the no-signal mode internal DRD DE signal, the horizontal blank value t5 of the corresponding signal may be used. A value corresponding to 1/2 of a horizontal blank value of t2 is set (610).

Meanwhile, as the horizontal blank value t3 between the first 'signal and the first " signal is set (606) to the minimum horizontal blank value, the interval between the first " signal and the second " The horizontal blank value t3 may have a significantly large value. The internal DRD DE signal generator according to the present invention may determine a value of the horizontal blank value t3 between the first '' signal and the second 'signal. Even if it is, it is possible to prevent the counter of the no signal mode DRD DE signal from being reset by not judging this as the vertical blank period.

Therefore, since the reset as mentioned in the description of FIG. 3C of the prior art is not performed, the timing controller can normally count the no signal mode DRD DE signal.

Further, the present invention sets the horizontal blank value t3 between the first signal and the first signal 606 as the minimum horizontal blank value, so that the first " There is no case where the horizontal blank value t3 between the signals becomes zero or becomes a value that cannot be counted.

Therefore, the present invention does not cause the problem as mentioned in the description of Figure 3 (b) of the prior art.

The present invention as described above is to remove the abnormal charging (i.e., abnormal line counter) that occurs when changing the mode from the signal mode to the no signal mode when driving the GIP & DRD & TN panel, the previous frame Temporarily stores the Last-1th Horizontal blank value (t1) of the (Previous Frame), while between the first 'and first' 'signals of the no-signal mode internal DRD DE signal. Set the horizontal blank value t3 to the minimum horizontal blank value, set the horizontal blank value between the first and second signals to t2 minus t3, and the remaining horizontal blank value equal to 1 / t of t2. It is characterized by setting two values.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

112: system 114: timing controller
114a: receiving unit 114b: video signal alignment unit
114c: control signal generator 114d: internal DRD DE signal generator

Claims (9)

A receiver for receiving an image signal, a synchronization signal, and a data enable (DE) signal from a system;
A data alignment unit for rearranging the video signals and transmitting the data signals to a data driver;
A control signal generator for generating a control signal using the synchronization signal and transmitting the generated control signal to a data driver and a gate driver; And
When changing from the signal mode to the no signal mode, the horizontal blank value between the first signal and the first signal of the first line of the first frame of the no signal mode internal DRD data enable signal is available as the horizontal blank value. A timing controller including an internal DRD data enable signal generator that sets the minimum value. The method of claim 1,
The internal DRD data enable signal generator,
The horizontal blank value between the second 'signal and the first " signal input after the first "" signal is determined by the horizontal blank value between the first and second signals of the no signal mode internal data enable signal. And setting a value obtained by subtracting the minimum value. The method of claim 1,
The internal DRD data enable signal generator,
And the counter of the no signal mode DRD data enable signal is not reset during the horizontal blank value period between the second 'signal input after the first " signal and the first " signal. The method of claim 1,
The internal DRD data enable signal generator,
The horizontal blank value between the signals input after the first '' signal may include setting a half value of the horizontal blank value between the first signal and the second signal among the no signal mode internal data enable signals. A timing controller characterized by the above-mentioned. The timing controller according to any one of claims 1 to 4;
panel;
A data driver for controlling a data line formed in the panel according to the control of the timing controller; And
And a gate driver for controlling a gate line formed in the panel under the control of the timing controller. When changing from the signal mode to the no signal mode, the horizontal blank value between the first 'signal and the first''signal of the first line of the first frame of the no signal mode internal DRD data enable signal is used as the horizontal blank value. Setting to the lowest possible value; And
The horizontal blank value between the first "" signal and the second 'signal' input thereafter includes the minimum value at the horizontal blank value between the first and second signals of the no signal mode internal data enable signal. And setting the subtracted value. The method according to claim 6,
Setting to the minimum value,
Determining whether the signal input in the no signal mode is the first 'signal, which is the first signal of the no signal mode DRD data enable signal;
Performing the minimum value setting process when the first signal is determined as the determination result; And
And if the result is not the first 'signal, moving to the step of setting a horizontal blank value between the first''signal and the second' signal. The method according to claim 6,
And the counter of the no signal mode DRD data enable signal is not reset between the second 'signal input after the first " signal and the first " signal. The method according to claim 6,
The horizontal blank value between the signals input after the second 'signal further includes setting the horizontal blank value between the first signal and the second signal of the no signal mode internal data enable signal to 1/2 of the horizontal blank value. Timing controller driving method.

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