KR20120064820A - Method of manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A method of manufacturing a semiconductor device is provided to prevent dishing by forming an inter-layer insulating film having a flat upper side for each area on a substrate. CONSTITUTION: A second barrier film is formed on a first interlayer insulating film. A second secondary inter-layer insulating film is formed by etching a part of the first interlayer insulating film and the second barrier film. A part of the second barrier film and the second secondary inter-layer insulating film is primarily ground. The second secondary inter-layer insulating film is secondarily ground in order to expose a first barrier layer pattern and the second barrier film. A second barrier film pattern(20b) and a second inter-layer insulating film(18b) are formed on a substrate in a second region.

Description

Method of manufacturing a semiconductor device

The present invention relates to a method of manufacturing a semiconductor device. More specifically, the present invention relates to a method of manufacturing a vertical semiconductor device in which the flatness of the interlayer insulating film is excellent for each region of the substrate, thereby reducing process defects.

Recently, a technique for stacking cells in a direction perpendicular to a substrate for high integration of semiconductor devices has been developed. In order to fabricate a semiconductor device in which the cells are vertically stacked, thin films are stacked in multiple layers in the cell region, thereby increasing the height of structures formed in the cell region. However, in the ferry region, the height of the thin films constituting the circuits is relatively low. Therefore, the step between the thin films formed in the cell region and the ferry region becomes very large. Due to the step difference between the thin films formed in the cell region and the ferry region, a high step also occurs in the interlayer insulating layer covering the thin films formed in the cell region and the ferry region. Even if the polishing process is performed due to the step between the interlayer insulating layers in the cell region and the ferry region, a residue defect may occur in which the film is not completely removed at the low step region. In addition, dishing may occur in the interlayer insulating film covering the low stepped portion.

An object of the present invention is to provide a method for manufacturing a semiconductor device having an excellent flatness of the upper interlayer insulating film for each region of the substrate.

In a method of manufacturing a semiconductor device according to an embodiment of the present invention for achieving the above object, in a substrate in which the first and second regions are divided, a laminate structure and a first blocking layer pattern are formed on the substrate of the first region. Form. A first interlayer insulating film is formed on the substrates of the first and second regions so that the first blocking layer pattern is covered and the upper surface of the film in the second region is at least the same as or higher than the bottom surface of the first blocking layer pattern. . A second blocking film is formed on the first interlayer insulating film. A portion of the second blocking layer and the first interlayer insulating layer formed in the first region are etched to form a second preliminary interlayer insulating layer. A portion of the second preliminary interlayer insulating layer and the second blocking layer are first polished to remove the protruding portions of the first and second region boundaries from the second preliminary interlayer insulating layer. In addition, the second preliminary interlayer insulating layer is second polished to expose the first and second blocking layers, thereby forming a second blocking layer pattern and a second interlayer insulating layer on the substrate of the second region.

In an embodiment, the upper surface of the first interlayer insulating layer in the second region may have a height difference within 2000 μs from a bottom surface of the first blocking layer pattern.

In one embodiment of the present invention, the side wall of the laminated structure may be formed to have a step shape that becomes narrower from the bottom to the top.

In an embodiment of the present invention, in order to form the stack structure and the first blocking layer pattern, silicon oxide and silicon nitride are repeatedly stacked on the substrate to form a mold layer. A first blocking film is formed on the mold film. The first blocking layer and the mold layer are patterned to form a stack structure and a first blocking layer pattern on the substrate of the first region.

In one embodiment of the present invention, each of the first and second blocking layers may be formed of a material having a polishing selectivity with silicon oxide.

In one embodiment of the present invention, the first blocking layer pattern may be formed of polysilicon, and the second blocking layer may be formed of silicon nitride.

In one embodiment of the present invention, the first blocking layer pattern and the second blocking layer may be formed of different materials.

In one embodiment of the present invention, the first blocking layer pattern and the second blocking layer may be formed of the same material.

In one embodiment of the present invention, the primary polishing and the secondary polishing may be performed in the same polishing facility. The primary polishing and the secondary polishing may be performed under different polishing conditions.

In an embodiment, the method may further include removing the first and second stopper layer patterns.

In one embodiment of the present invention, the stacked structure may be formed over the entire cell area.

In one embodiment of the present invention, the first blocking film pattern and the second blocking film may have a thickness difference of less than 2000Å.

A method of manufacturing a vertical semiconductor device according to an embodiment of the present invention for achieving the above object, and the mold structure and the insulating film pattern stacked on the substrate is divided into a first region and the second region 1 A blocking film pattern is formed. A first interlayer insulating film is formed on the substrates of the first and second regions so that the first blocking layer pattern is covered and the upper surface of the film in the second region is at least the same as or higher than the bottom surface of the first blocking layer pattern. . A second blocking film is formed on the first interlayer insulating film. A portion of the second blocking layer and the first interlayer insulating layer formed in the first region are etched to form a second preliminary interlayer insulating layer. A portion of the second preliminary interlayer insulating layer and the second blocking layer are first polished to remove the protruding portions of the first and second region boundaries from the second preliminary interlayer insulating layer. The second preliminary interlayer insulating layer is second polished to expose the first and second blocking layers, thereby forming a second blocking layer pattern and a second interlayer insulating layer on the substrate of the second region. A thin film structure in which a channel film pattern penetrating the mold structure and a blocking dielectric film, a charge storage film, and a tunnel insulating film are stacked on sidewalls of the channel film pattern. The sacrificial layer patterns included in the mold structure are removed. In addition, a gate electrode is formed on a portion where the sacrificial layer pattern is removed.

In an embodiment, the upper surface of the first interlayer insulating layer in the second region may have a height difference within 2000 μs from a bottom surface of the first blocking layer pattern.

In one embodiment of the present invention, the side wall of the mold structure may have a step shape that becomes narrower from the bottom to the top.

In one embodiment of the present invention, each of the first and second blocking layers may be formed of a material having a polishing selectivity with silicon oxide.

In one embodiment of the present invention, the primary polishing and the secondary polishing may be performed in the same polishing facility.

According to an embodiment of the present invention, after forming the second blocking layer pattern, the step of removing the first and second blocking layer patterns may be performed.

In one embodiment of the present invention, a bit line may be formed in electrical contact with the upper surface of the channel film pattern.

As described, according to the method of the present invention, an interlayer insulating film having a flat top surface may be formed even if the level of mold structures for each region of the substrate is high. Therefore, dishing failure or residue defect caused by the step difference of the upper surface of the interlayer insulating film is reduced.

1 to 7 are cross-sectional views illustrating a planarization method in manufacturing a semiconductor device according to an embodiment of the present invention.
8 to 15 are cross-sectional views illustrating a method of manufacturing a vertical semiconductor device according to an embodiment of the present invention.
16 to 22 are cross-sectional views illustrating a method of manufacturing a vertical semiconductor device according to an embodiment of the present invention.
Figure 23 illustrates another embodiment of the present invention.
24 shows another embodiment.
25 shows another embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the drawings of the present invention, the dimensions of the structures are enlarged to illustrate the present invention in order to clarify the present invention.

In the present invention, the terms first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

In the present invention, it is to be understood that each layer (film), region, electrode, pattern or structure may be formed on, over, or under the object, substrate, layer, Means that each layer (film), region, electrode, pattern or structure is directly formed or positioned below a substrate, each layer (film), region, or pattern, , Other regions, other electrodes, other patterns, or other structures may additionally be formed on the object or substrate.

For the embodiments of the invention disclosed herein, specific structural and functional descriptions are set forth for the purpose of describing an embodiment of the invention only, and it is to be understood that the embodiments of the invention may be practiced in various forms, But should not be construed as limited to the embodiments set forth in the claims.

That is, the present invention may be modified in various ways and may have various forms. Specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

1 to 7 are cross-sectional views illustrating a planarization method in manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor substrate 10 in which a first region and a second region are divided is provided. For example, the first region may be a cell region in which memory cells are formed, and the second region may be a ferry region in which peripheral circuits are formed. The semiconductor substrate 10 may be a single crystal silicon substrate.

Thin films forming the stacked structure 12 are formed on the substrate 10. The thin films may be formed by stacking different kinds of material films. Alternatively, two or more thin films may be alternately laminated. An upper insulating layer and a first blocking layer are formed on the thin films. Thereafter, the thin films, the upper insulating layer, and the first blocking layer are patterned to remove the layers formed on the substrate of the second region, thereby forming the laminate structure 12 and the upper insulating layer pattern on the substrate 10 of the first region. 14) and the first blocking film pattern 16 are formed.

The upper insulating layer pattern 14 may be formed of silicon oxide. The first stopper layer pattern 16 functions as a polishing stopper layer for inhibiting the lower stacked structure 12 from being polished and removed in a subsequent process. Therefore, the first blocking layer pattern 16 is preferably formed of a material having a polishing selectivity with silicon oxide. In the present embodiment, the first blocking layer pattern 16 is made of polysilicon. In another embodiment, the first blocking layer pattern 16 may be formed of silicon nitride.

A first interlayer insulating layer 18 is formed on the substrate 10 to cover the first blocking layer pattern 16. The first interlayer insulating layer 18 may be formed of silicon oxide. In this case, since the stacked structure 12 is provided on the substrate 10 of the first region, the upper surface B of the first interlayer insulating layer 18 formed on the substrate 10 of the first region may be formed. The upper surface A of the first interlayer insulating layer 18 formed on the substrate 10 of the second region is positioned higher.

In the first interlayer insulating layer 18 formed in the second region, an upper surface A of the first interlayer insulating layer 18 is formed to be equal to or higher than a bottom surface of the first blocking layer pattern 16. When the upper surface of the first interlayer insulating layer is lower than the bottom surface of the first blocking layer pattern, the height of the upper surface of the first interlayer insulating layer of the second region is lower than that of the upper insulating layer to cause dishing.

It is preferable that the height difference between the first interlayer insulating film 18 formed in the second region and the bottom surface of the first blocking film pattern is less than 2000 kPa. More preferably, the upper surface A of the first interlayer insulating layer 18 formed in the second region is located on the same plane as the bottom surface of the first blocking layer pattern 16.

A second blocking layer pattern (not shown) is formed on the first interlayer insulating layer 18 formed in the second region through a subsequent process. The second blocking film pattern is a film for preventing polishing of the first interlayer insulating film 18 formed in the second region when the first interlayer insulating film 18 is planarized. For this reason, the second interlayer insulating layer may have a top surface in substantially the same plane as the first blocking layer pattern 16 so that the first interlayer insulating layer is formed in each region by the first and second blocking layer patterns. Polishing of (18) can be prevented. For this purpose, it is preferable that the position of the upper surface of the first interlayer insulating layer 18 is equal to the height of the bottom surface of the first blocking layer pattern 16. On the other hand, when the top surface of the first interlayer insulating film 18 is different from the bottom surface of the first blocking film pattern 16 by a height of 2000 m or more, the first interlayer in the first and second regions may be subjected to a polishing process. It is difficult for the top surface of the insulating film 18 to be flat, and dishing defects may occur.

Referring to FIG. 2, a second blocking layer 20 is formed on the first interlayer insulating layer 18. The second blocking layer 20 may be formed of a material having a high etching selectivity with respect to the first interlayer insulating layer 18. The second blocking layer 20 may be formed of a material different from that of the first blocking layer pattern 16, or may be formed of the same material. In the present exemplary embodiment, the second blocking layer 20 may be connected to the first blocking layer pattern 16 so that process control may be performed on the first blocking layer pattern 16 and the second blocking layer 20, respectively. Form with other materials. Specifically, the first blocking layer pattern 16 is formed of polysilicon, and the second blocking layer 20 is formed of silicon nitride.

The second blocking layer 20 has a thickness difference of less than or equal to 2000 μs from the first blocking layer pattern 16, and preferably, the second blocking layer 20 has the same thickness as that of the first blocking layer pattern 16. To form.

Referring to FIG. 3, a photoresist film is formed on the first interlayer insulating film 18, and the photoresist film is exposed and developed to form a photoresist pattern (not shown) exposing the first interlayer insulating film 18 of the first region. do. The second blocking layer 20 positioned in the cell region is etched using the photoresist pattern as a mask, and then the first interlayer insulating layer 18 is partially etched. As a result, the second preliminary blocking layer pattern 20a and the second preliminary interlayer insulating film 18a are formed, respectively.

In the etching process, the first interlayer insulating layer 18 is etched so that the top surface of the first blocking layer pattern 16 is not exposed. In the second preliminary interlayer insulating layer 18a formed through the etching process, an upper surface level difference between the first and second regions is lower than that of the first interlayer insulating layer 18. In addition, as illustrated, the second preliminary interlayer insulating layer 18a has a shape C protruding from the boundary between the first and second regions.

Referring to FIG. 4, a buffer oxide layer 22 is formed on the second preliminary interlayer insulating layer 18a and the second preliminary blocking layer pattern 20a. The buffer oxide layer 22 may be formed of silicon oxide. The process of forming the buffer oxide film 22 may be omitted to simplify the process.

Referring to FIG. 5, the buffer oxide layer 22 and the second preliminary blocking layer are removed to remove protruding portions (FIGS. 3 and C) of the first and second region boundaries in the second preliminary interlayer insulating layer 18a. A first polishing process is performed on the upper surface of the film pattern 20a and the second preliminary interlayer insulating film 18a. The first polishing process is preferably performed by a process of quickly removing the protruding portion of the thin film. By the first polishing process, a part of the buffer oxide film 22, the second preliminary blocking film pattern 20a, and the second preliminary interlayer insulating film 18a are removed. In addition, the top surface step of the film formed in the first and second regions is alleviated.

Referring to FIG. 6, a second polishing process is performed on the buffer oxide layer 22, the second preliminary barrier layer pattern 20a, and the second preliminary interlayer insulating layer 18a on which the first polishing process is performed, so that an upper surface thereof is formed. Make it flat. That is, the first blocking layer pattern 16 is exposed on the upper surface of the first region, and the second blocking layer pattern 20b is exposed on the upper surface of the second region.

The second polishing process may be performed in a polishing apparatus having the same equipment as the first polishing process. However, the first polishing and the second polishing are polished under different polishing conditions. For example, the second polishing process may be performed using a slurry different from the first polishing process. The second polishing process is performed using a slurry in which polishing is stopped or the polishing rate is slowed in the first and second blocking layer patterns 16 and 20b. When the second polishing process is performed, the second preliminary interlayer insulating film 18a formed in the first region is removed, and the second preliminary interlayer insulating film 18a formed in the second region remains. Therefore, a second interlayer insulating film 18b is formed in the second region. In addition, an upper surface of the second interlayer insulating layer 18b may be positioned on substantially the same plane as an upper surface of the upper insulating layer pattern 14.

Since the second blocking layer pattern 20b is provided to prevent polishing, the second interlayer insulating layer 18b positioned in the second region is polished when the second polishing process is performed to prevent dishing from occurring. have. In addition, since the first blocking film pattern 16 is provided to prevent polishing, a defect in which the laminated structure positioned in the first region is removed during the second polishing process can be prevented.

Referring to FIG. 7, the first and second blocking layer patterns 16 and 20b are removed through an etching process. In order to suppress damage to the upper insulating film pattern 14 and the second interlayer insulating film 18b, the etching process is preferably a wet etching process. When the process is performed, the upper insulating film pattern 14 is exposed in the first region, and the second interlayer insulating film 18b is exposed in the second region. In addition, the upper insulating layer pattern 14 and the second interlayer insulating layer 18b have a flat upper surface.

As described above, according to the present exemplary embodiment, the interlayer insulating layer covering the first region in which the stacked structures are formed and the second region in which the stacked structures are not formed have a flat shape. As described above, since the level difference of the upper surface of the interlayer insulating film formed in each region is hardly generated, dishing defects are reduced, and the residual defects remaining without the film being locally polished at the stepped portions are reduced.

8 to 15 are cross-sectional views illustrating a method of manufacturing a vertical semiconductor device according to an embodiment of the present invention.

Referring to FIG. 8, a substrate 100 in which first and second regions are divided is provided. Memory cells stacked in the vertical direction are formed in the first region of the substrate 100. The substrate 100 may be made of single crystal silicon.

A pad oxide film (not shown) is formed on the substrate 100. The sacrificial films 102a to 102g and the insulating films 104a to 104f are sequentially formed on the pad oxide film. For example, the first to seventh sacrificial layers 102a to 102g and the first to sixth insulating layers 104a to 104f may be alternately stacked on the substrate 100. The insulating layers 104a to 104f may be formed of silicon oxide, and the sacrificial layers 102a to 102g may be formed of silicon nitride.

An upper insulating layer 106 and a first blocking layer 108 are formed on the seventh sacrificial layer 102g. The upper insulating layer 106 has a thicker shape than the insulating layers 104 to 104f disposed below. The first blocking layer 108 may be formed of a material having a polishing selectivity with silicon oxide. In the present embodiment, the first blocking film 108 is formed of polysilicon. In another embodiment, the first blocking layer 108 may be formed of silicon nitride.

Referring to FIG. 9, the first blocking layer 108 is patterned through a photolithography and an etching process to form the first blocking layer pattern 108a. Subsequently, the upper insulating layer 106 is etched to form an upper insulating layer pattern 106a. In addition, by sequentially etching the sacrificial layers 102a to 102g and a portion of the insulating layers 104a to 104f, the sacrificial layer patterns 110a to 110g and the insulating layer patterns are formed on the substrate 100 of the first region. A mold structure 114 in which the layers 112a to 112g are stacked is formed.

The mold structure 114 is formed only on the substrate 100 in the first region. Side edge portions of the sacrificial layer patterns 110a to 110g and the insulating layer patterns 112a to 112f included in the mold structure 114 have a step shape. That is, the sacrificial layer patterns 110a to 110g and the insulating layer patterns 112a to 112g disposed on the lower portion of the sacrificial layer patterns 110a to 110g are more than the sacrificial layer patterns 110a to 110g and the insulating layer patterns 112a to 112g disposed on the upper portion thereof. It has a wide shape. In addition, the side lengths of the sacrificial layer patterns 110a to 110g and the insulating layer patterns 112a to 112g become shorter from the bottom to the top.

Referring to FIG. 10, a first interlayer insulating layer 116 is formed on the substrate 100 to cover the first blocking layer pattern 108a. The first interlayer insulating layer 116 may be formed of silicon oxide. At this time, since the mold structure 114 is stacked on the substrate 100 of the first region, an upper surface of the first interlayer insulating layer 116 formed on the substrate 100 of the first region is the second region. Is positioned higher than an upper surface of the first interlayer insulating layer 116 formed on the substrate 100.

An upper surface of the first interlayer insulating layer 116 formed in the second region is formed to be the same as or higher than a bottom surface of the first blocking layer pattern 108a. A height difference between the top surface of the first interlayer insulating layer 116 and the bottom surface of the first blocking layer pattern 108a formed in the second region may be less than 2000 mm. Since the upper surface of the second blocking layer pattern 118a must be substantially positioned on the same plane as the first blocking layer pattern 108a, the upper surface of the first interlayer insulating layer 116 is positioned at the first blocking layer. It is preferable that the height is equal to the height of the bottom surface of the pattern 108a.

Referring to FIG. 11, a photoresist film is formed on the first interlayer insulating layer 116, and a photoresist pattern (not shown) is formed to expose and develop the photoresist layer 116 to expose the first interlayer insulating layer 116 of the first region. do. The second blocking layer 118 positioned in the cell region is etched using the photoresist pattern as a mask, and then the first interlayer insulating layer 116 is partially etched. By the etching process, the second preliminary blocking layer pattern 118a and the second preliminary interlayer insulating layer 116a are formed, respectively.

As a result of the etching process, an upper surface level difference between the first and second regions of the second preliminary interlayer insulating layer 116a may be lowered. In addition, as shown in the drawing, the second preliminary interlayer insulating layer 116a has a shape protruding from a boundary between the first and second regions.

A buffer oxide layer 119 is formed on the second preliminary interlayer insulating layer 116a and the second preliminary blocking layer pattern 118a.

Referring to FIG. 12, the buffer oxide layer 119, the second preliminary barrier layer pattern 118a, and the second preliminary interlayer insulating layer 116a may be removed to remove protruding portions of the boundary between the first and second regions. A first polishing process is performed on the upper surface of the second preliminary interlayer insulating film 116a. The first polishing process is preferably performed by a process of quickly removing the protruding portion of the thin film. By the said 1st grinding | polishing process, the upper surface level | step difference of the film | membrane formed in the said 1st and 2nd area | region is relaxed.

A second polishing process is performed on the buffer oxide layer 119, the second preliminary barrier layer pattern 118a, and the second preliminary interlayer insulating layer 116a where the first polishing process is performed, so that the top surface is flat. That is, the first blocking layer pattern 108a is exposed on the upper surface of the first region, and the second blocking layer pattern 118b is exposed on the upper surface of the second region. By the polishing process, a second interlayer insulating film 116b having a flat top surface is formed.

The second polishing process may be performed in a polishing apparatus having the same equipment as the first polishing process. However, the polishing conditions of the first and second polishing processes are different from each other. For example, the second polishing process may be performed using a slurry different from the first polishing process. The second polishing process is performed using a slurry in which polishing is stopped or the polishing rate is slowed in the first and second blocking layer patterns 108a and 118a.

An upper surface of the second interlayer insulating layer 116b formed by performing the second polishing process may be positioned on substantially the same plane as the upper surface of the upper insulating layer pattern 106a. Since the second blocking layer pattern 118b is provided, the second interlayer insulating layer 116b positioned in the second region may be polished to perform dishing when the second polishing process is performed.

Referring to FIG. 13, the first and second blocking layer patterns 108a and 118b are removed through an etching process. In order to suppress damage to the upper insulating layer pattern 106a and the second interlayer insulating layer 116b, the etching process may be a wet etching process.

An etch mask pattern (not shown) is formed on the upper insulating layer pattern 106a and the second interlayer insulating layer 116b to form a channel hole. The channel holes are formed in the cell region. Using the etching mask pattern as an etching mask, a plurality of channel holes are formed by sequentially etching lower insulating layers and sacrificial layers. The surface of the substrate 100 is exposed at the bottom of the channel holes. The channel holes are arranged in a line.

A thin film structure 120 in which a blocking dielectric film, a charge storage film, and a tunnel insulating film are stacked on the sidewall surfaces of the channel holes is formed. The blocking dielectric layer, the charge storage layer, and the tunnel insulating layer may be formed of an ONO structure in which silicon oxide, silicon nitride, and silicon oxide are stacked. As another example, the blocking dielectric layer may be formed of a metal oxide having a high dielectric constant, and the charge storage layer and the tunnel insulating layer may be formed of silicon nitride and silicon oxide, respectively.

The semiconductor material film is formed to completely fill the inside of the channel hole in which the blocking dielectric film, the charge storage film, and the tunnel insulating film are formed on the sidewalls. The semiconductor material film may include a polysilicon film. The polysilicon film is in contact with the substrate surface of the bottom of the channel hole. Thereafter, the polysilicon film is polished to expose the top surface of the upper insulating film pattern 106a to form a channel film pattern 122 inside the channel hole.

At this time, the flatness of the upper insulating film and the second interlayer insulating film in the first and second regions is very high and dishing is hardly generated. Therefore, in the process of polishing the polysilicon film, a residue defect in which the polysilicon film remains on the upper surface of the upper insulating film and the second interlayer insulating film does not occur.

Referring to FIG. 14, the opening layer 124 is formed by etching the upper insulating layer pattern 106a and the mold structure 114 between the channel layer patterns 122 arranged in a line. The opening 124 has a trench shape extending in one direction. In addition, the opening 124 is formed by etching the mold structure 114 to expose the surface of the substrate 100.

Referring to FIG. 15, after the openings 124 are formed, the sacrificial layer patterns 110 to 110g exposed on the sidewalls of the openings 124 are removed to form grooves.

A conductive film (not shown) is formed in the groove portion and the opening 124. The conductive film can be deposited using a conductive material having good step coverage properties to suppress the generation of voids. The conductive material may include a metal. Examples of the conductive material include materials having low electrical resistance, such as tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, and platinum. As a specific example, a barrier metal film made of titanium, titanium nitride, tantalum, tantalum nitride, or the like may be formed first, and then a metal film made of tungsten may be formed.

Thereafter, the conductive film formed inside the opening 124 is etched. That is, the control gate electrodes 130a to 130g are formed by leaving only the conductive film inside the groove. The removal process may be performed through a wet etching process. Side edges of the control gate electrodes 130a to 130g have a step shape. Therefore, the lateral edge portion can be used as a pad for connecting a word line.

An N-type impurity is doped into the substrate on the bottom surface of the opening formed by etching the conductive film to form an impurity region (not shown) used as the source line S / L. Specifically, the impurity region can be formed by doping the substrate with N-type impurities. In addition, a metal silicide pattern may be formed on the impurity region to reduce the resistance of the source line S / L.

An insulating film filling the opening is formed, and the insulating film pattern 126 is formed by planarization by a polishing process.

A third interlayer insulating layer 128 is formed to cover structures including the channel layer pattern 126 and the control gate electrodes 130a to 130g. A bit line contact 132 is formed through the third interlayer insulating layer 128 to contact the upper surface of the channel layer pattern 122. In addition, bit lines 134 are formed to contact the upper surface of the bit line contact 132. The bit lines 134 may have a line shape extending in the second direction and may be electrically connected to the channel film patterns 122.

In addition, contact plugs (not shown) and connection lines (not shown) are respectively connected to the control gate electrodes 130a to 130g of the respective layers.

The vertical nonvolatile memory device manufactured according to the present embodiment has a flat shape in which an interlayer insulating film is formed at a portion where a stack structure is formed and a portion where a stack structure is not formed. As described above, since the level difference of the upper surface of the interlayer insulating film formed in each region is hardly generated, dishing defects are reduced. In addition, residual defects that remain without the film to be removed being locally polished are reduced. Therefore, a vertical nonvolatile memory device having high performance can be manufactured.

16 to 22 are cross-sectional views illustrating a method of manufacturing a vertical semiconductor device according to an embodiment of the present invention.

Referring to FIG. 16, a semiconductor substrate 200 having a cell region in which memory cells are formed and a ferry region in which peripheral circuits are formed are provided. The semiconductor substrate 200 may be a single crystal silicon substrate.

Unit devices forming peripheral circuits are formed on the substrate 200 of the ferry region. The unit devices may include a transistor 202 and contact plugs (not shown).

A first interlayer insulating layer 204 is formed on the substrate 200 to cover the unit devices. The first interlayer insulating layer 204 may be formed by depositing silicon oxide. An upper surface of the first interlayer insulating layer 204 may be planarized. The planarization may be performed through a chemical mechanical polishing or etch back process.

A first blocking layer 206 is formed on the first interlayer insulating layer 204. The first blocking layer 206 may be formed of silicon nitride.

An etch mask pattern (not shown) covering only the ferry region is formed on the first blocking layer 206. For example, the etching mask pattern may be formed as a photoresist pattern.

The first blocking layer 206 and the first interlayer insulating layer 204 are sequentially etched using the etching mask pattern to form an opening 207 exposing the surface of the substrate 200 in the cell region. The entire surface of the substrate 200 in the cell region is exposed by the etching process.

Referring to FIG. 17, a pad oxide film (not shown) is formed on the substrate 200. The sacrificial film and the insulating films are sequentially formed on the pad oxide film sequentially. The sacrificial layer and the insulating layer are formed to fill the inside of the opening 207 formed in the cell region. In this case, the height of the sacrificial layer at the top of the cell region may be equal to the height of the first etch stop layer 206. The sacrificial layer may be formed of silicon nitride, and the insulating layer may be formed of silicon oxide.

By sequentially patterning the sacrificial layers and the insulating layers, a first preliminary mold structure in which the sacrificial layer patterns 208a to 208d and the insulating layer patterns 210a to 210c are stacked on the substrate 200 in the cell region. 214).

Side edge portions of the sacrificial layer patterns 208a to 208d and the insulating layer patterns 210a to 210c included in the first preliminary mold structure 214 have a step shape.

An insulating material layer 212 is formed to cover the first preliminary mold structure 214 and fill the opening on the side of the first premold structure. In addition, the insulating material layer 212 may be polished to expose the top surface of the first blocking layer 206 and the fourth sacrificial layer pattern 208d formed on the top thereof. During the polishing process, polishing is stopped or the polishing rate is slowed at the first blocking film 206. Therefore, there is no problem that the circuit pattern formed in the ferry region is damaged by the polishing process.

Referring to FIG. 18, the first blocking layer 206 and the fourth sacrificial layer pattern 208d are removed through an etching process.

Next, the sacrificial film and the insulating film are repeatedly stacked on the third insulating film, the insulating material film, and the first interlayer insulating film to form a second preliminary mold structure. For example, the second preliminary mold structure may have a shape in which fifth to eighth sacrificial layers and fourth to seventh insulating layers are alternately stacked. An upper insulating layer and a second blocking layer are formed on the eighth sacrificial layer. Preferably, the second blocking film is formed of a material having a polishing selectivity with silicon oxide. In this embodiment, the second blocking film is made of polysilicon. In another embodiment, the second blocking layer may be formed of silicon nitride.

The second blocking layer pattern and the upper insulating layer are patterned to form a second blocking layer pattern 224 and an upper insulating layer pattern 222. Subsequently, the second mold structure 219 is formed on the first mold structure 214 by patterning the second preliminary mold structure. Side edge portions of the sacrificial layer patterns 220a to 220d and the insulation layer patterns 218a to 218d included in the second mold structure 219 have a stepped shape. That is, the sacrificial layer patterns positioned on the lower side have a wider shape than the sacrificial layer patterns positioned on the upper side.

In addition, as shown, the side edge portions of the first and second mold structures 214 and 219 have a step shape.

Referring to FIG. 19, a second interlayer insulating layer 226 may be formed to cover the second mold structure 219, the first interlayer insulating layer 204, and the insulating material layer 212. An upper surface of the second interlayer insulating layer 226 positioned on the first interlayer insulating layer 204 should be located at the same plane or higher than the bottom of the second blocking layer pattern. A height difference between an upper surface of the second interlayer insulating layer 226 and the upper surface of the second blocking layer pattern 224 disposed on the first interlayer insulating layer 204 may be less than or equal to 2000 μs. More preferably, an upper surface of the second interlayer insulating layer 226 on the first interlayer insulating layer 204 is disposed on the same plane as the upper surface of the second blocking layer pattern 224.

A third blocking layer 228 is formed on the second interlayer insulating layer 226. The third blocking layer 228 may be formed of a material having a high etching selectivity with respect to the second interlayer insulating layer 226. The third blocking layer 228 may be formed of a material different from that of the second blocking layer pattern 224, or may be formed of the same material. In this embodiment, the third blocking layer 228 is formed of a material different from that of the second blocking layer pattern 224. In detail, the second blocking layer pattern 224 is formed of polysilicon, and the third blocking layer 228 is formed of silicon nitride.

The thickness of the third blocking layer 228 and the second blocking layer pattern 224 is 2000 mm or less. Preferably, the third blocking layer 228 is formed to have the same thickness as the second blocking layer pattern 224.

Referring to FIG. 20, a photoresist pattern (not shown) exposing the second interlayer insulating layer 226 of the cell region is formed on the second interlayer insulating layer 226. The third blocking layer 228 positioned in the cell region is etched using the photoresist pattern as a mask, and then the second interlayer insulating layer 226 is partially etched. As a result, the third preliminary blocking layer pattern 228a and the third preliminary interlayer insulating film 226a are formed, respectively. The third preliminary interlayer insulating layer 226a formed by etching a portion of the second interlayer insulating layer 226 has a shape in which a boundary portion between the cell and the ferry region protrudes. In the etching process, the upper surface of the second blocking layer pattern 224 should not be exposed.

A buffer oxide film 230 is formed on the third interlayer insulating film 226. The buffer oxide layer 230 may be formed of silicon oxide.

Referring to FIG. 21, the buffer oxide layer 230, the third preliminary barrier layer pattern 228a, and the third interlayer insulating layer 226 may be removed to remove protruding portions of the boundary between the first and second regions. A first polishing process is performed on the upper surface of the three interlayer insulating film 226. The first polishing process is preferably performed by a process of quickly removing the protruding portion of the thin film. By the said 1st grinding | polishing process, the upper surface level | step difference of the film | membrane formed in the said 1st and 2nd area | region is relaxed.

A second polishing process is performed on the buffer oxide layer 230, the third preliminary barrier layer pattern 228a, and the third interlayer insulating layer 226 on which the first polishing process is performed, so that the top surface is flat. By the polishing process, a third blocking film pattern 228b is formed on the upper surface of the ferry region. In addition, the second blocking layer pattern 224 is exposed on the upper surface of the cell region, and the third blocking layer pattern 228b is exposed on the upper surface of the ferry region.

The second polishing process may be performed in a polishing apparatus having the same equipment as the first polishing process. However, the first and second polishing processes are different from each other in the polishing process conditions. For example, the second polishing process may be performed by using a slurry in which polishing is stopped or the polishing rate is slowed in the second and third blocking layer patterns 224 and 228b.

When the second polishing process is performed, the upper surface of the third interlayer insulating layer 226 formed in the ferry region is positioned on the same plane as the upper surface of the upper insulating layer 222. By providing the third blocking layer pattern 228b, when the second polishing process is performed, the third interlayer insulating layer 226 positioned in the ferry region may be polished to prevent dishing.

Referring to FIG. 22, the second and third blocking layer patterns 224 and 228b are removed through an etching process. The lower insulating layers and the sacrificial layers are sequentially etched to form a plurality of channel holes through which the substrate surface is exposed. A thin film structure 230 in which a blocking dielectric layer, a charge storage layer, and a tunnel insulation layer are stacked is formed on sidewall surfaces of the channel holes.

A channel material pattern 232 is formed by forming and polishing a semiconductor material film to completely fill the inside of the channel hole in which the thin film structure 230 is formed. However, the flatness of the upper insulating film 222 and the third interlayer insulating film 226 in the first and second regions is very high and dishing is hardly generated. Therefore, in the process of polishing the semiconductor material film, a residue defect in which the semiconductor material film remains on the upper surfaces of the upper insulating film 222 and the third interlayer insulating film 226 does not occur.

The mold structure between the channel layer patterns 232 arranged in a line is etched to form an opening exposing the substrate surface. The sacrificial layer patterns 208a to 208c and 220a to 220d exposed on the sidewalls of the opening are removed to form grooves. Control gate electrodes 209a to 209c and 221a to 221d are formed in the groove. An insulating film filling the opening is formed, and the insulating film pattern 234 is formed by planarization by a polishing process.

A fourth interlayer insulating layer 240 is formed on the channel layer pattern 232, the upper insulating layer 222, and the third interlayer insulating layer 226. Bit line contacts 242 and bit lines 244 are formed through the fourth interlayer insulating layer 240 to be electrically connected to an upper surface of the channel layer pattern 232. In addition, contact plugs (not shown) and connection lines (not shown) connected to the control gate electrodes 209a to 209c and 221a to 221d of the respective layers are formed.

According to the present exemplary embodiment, the ferry circuit may not be damaged in the process of manufacturing the vertical semiconductor device. In addition, it is possible to hardly generate a step difference between the interlayer insulating films in the ferry region and the cell region. In this way, dishing defects are reduced because hardly any step difference in the upper surface of the interlayer insulating film formed in the cell and ferry regions occurs. In addition, residual defects that remain without the film to be removed being locally polished are reduced. Therefore, a vertical nonvolatile memory device having high performance can be manufactured.

In the following, other embodiments according to the invention are shown.

Figure 23 illustrates another embodiment of the present invention.

As shown, the present embodiment includes a memory 510 connected to the memory controller 520. The memory 510 includes a vertical nonvolatile memory device having a structure according to each embodiment of the present invention. The memory controller 520 provides an input signal for controlling the operation of the memory.

24 shows another embodiment.

This embodiment includes a memory 510 coupled to the host system 700. The memory 510 includes a vertical nonvolatile memory device having a structure according to embodiments of the present invention.

The host system 700 includes electronic products such as a personal computer, a camera, a mobile device, a game machine, a communication device, and the like. The host system 700 applies an input signal for controlling and operating the memory 510, and the memory 510 is used as a data storage medium.

25 shows another embodiment. This embodiment shows a portable device 600. The portable device 600 may be an MP3 player, a video player, a multifunction device of video and audio player, or the like. As shown, portable device 600 includes a memory 510 and a memory controller 520. The memory 510 includes a vertical nonvolatile memory device having a structure according to embodiments of the present invention. The portable device 600 may also include an encoder / decoder 610, a display member 620, and an interface 670. Data (audio, video, etc.) is input / output from the memory 510 by the encoder / decoder 610 via the memory controller 520.

As described above, according to the present invention, it is possible to provide a vertical nonvolatile memory device having excellent performance and reduced defects. The vertical nonvolatile memory device can be actively applied to fabrication of highly integrated semiconductor devices.

10, 100, 200: semiconductor substrate 12: laminated structure
14 and 106a: upper insulating film pattern 16: first blocking film pattern
18, 116: 1st interlayer insulation film 18a, 116a: 2nd preliminary interlayer insulation film
18b and 116b: Second interlayer insulating film 20, 118: Second blocking film
20a: second preliminary stopper film pattern 20b, 118a: second stopper film pattern
22: buffer oxide film
102a to 102g: sacrificial film 104a to 104f: insulating film
106: upper insulating film 108: first blocking film
108a: first stopper film pattern 114: mold structure
110a to 110g: sacrificial film pattern 112a to 112g: insulating film pattern
119: buffer oxide film 120: thin film structure
122: channel film pattern 124: opening
126: insulating film pattern 128: third interlayer insulating film
130a ~ 130g: control gate electrode
132: bit line contact 134: bit line

Claims (10)

Forming a laminate structure and a first blocking layer pattern on the substrate in the first region, in the substrate in which the first and second regions are divided;
Forming a first interlayer insulating film on the substrate of the first and second regions so as to cover the first blocking layer pattern and to have an upper surface of the film in the second region at least equal to or higher than a bottom of the first blocking layer pattern; step;
Forming a second blocking film on the first interlayer insulating film;
Etching a portion of the second blocking layer and the first interlayer insulating layer formed in the first region to form a second preliminary interlayer insulating layer;
First polishing a portion of the second preliminary interlayer insulating layer and the second blocking layer to remove protruding portions of the first and second region boundaries from the second preliminary interlayer insulating layer; And
And secondly polishing the second preliminary interlayer insulating layer to expose the first and second blocking layers, thereby forming a second blocking layer pattern and a second interlayer insulating layer on the substrate of the second region. The manufacturing method of the semiconductor element made into. The method of claim 1, wherein an upper surface of the first interlayer insulating layer in the second region has a height difference within 2000 μs from a bottom surface of the first blocking layer pattern. The method of claim 1, wherein the sidewalls of the laminate structure are formed to have a stepped shape that becomes narrower from the bottom to the top thereof. The method of claim 1, wherein the forming of the stacked structure and the first blocking layer pattern comprises:
Repeatedly depositing silicon oxide and silicon nitride on a substrate to form a mold film;
Forming a first blocking film on the mold film; And
And patterning the first blocking layer and the mold layer to form a laminate structure and a first blocking layer pattern on the substrate of the first region. The method of claim 1, wherein the first blocking layer pattern and the second blocking layer are each formed of a material having a polishing selectivity with silicon oxide. The method of claim 1, wherein the first blocking layer pattern and the second blocking layer are formed of different materials. The method of claim 1, wherein the first blocking layer pattern and the second blocking layer are formed of the same material. The method of claim 1, wherein the primary polishing and the secondary polishing are performed in the same polishing facility. The method of claim 8, wherein the first polishing and the second polishing are performed under different polishing conditions. Forming a mold structure on which a sacrificial layer pattern and an insulating layer pattern are stacked and a first blocking layer pattern on a substrate in which the first and second regions are separated;
Forming a first interlayer insulating film on the substrate of the first and second regions so as to cover the first blocking layer pattern and to have an upper surface of the film in the second region at least equal to or higher than a bottom of the first blocking layer pattern; step;
Forming a second blocking film on the first interlayer insulating film;
Etching a portion of the second blocking layer and the first interlayer insulating layer formed in the first region to form a second preliminary interlayer insulating layer;
First polishing a portion of the second preliminary interlayer insulating layer and the second blocking layer to remove protruding portions of the first and second region boundaries from the second preliminary interlayer insulating layer;
Second polishing the second preliminary interlayer insulating layer to expose the first blocking layer pattern and the second blocking layer to form a second blocking layer pattern and a second interlayer insulating layer on the substrate of the second region;
Forming a thin film structure in which a channel film pattern penetrating through the mold structure and a blocking dielectric film, a charge storage film, and a tunnel insulating film are stacked on sidewalls of the channel film pattern;
Removing the sacrificial layer patterns included in the mold structure; And
And forming a gate electrode on a portion from which the sacrificial layer pattern is removed.

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