KR20120087586A - Semiconductor device and method for forming the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a forming method thereof are provided to prevent the generation of a punch by connecting a metal contact plug and a second storage electrode contact plug. CONSTITUTION: A gate electrode(106) is buried within a cell area and a semiconductor substrate. A first barrier layer is included on an upper potion of the gate electrode in the cell area. A first storage electrode contact plug(138a) is included on both upper end portions of an active area. A second storage electrode contact plug(138b) is included on an upper potion of the gate electrode in an edge portion of the cell area. A metal contact plug(144) is included on the upper portion of one storage electrode contact plug from storage electrode contact plugs.

Description

Semiconductor device and method for forming the same

The present invention relates to a semiconductor device and a method for forming the same, and more particularly, to a semiconductor device including a metal contact plug and a method for forming the same.

Recently, most electronic appliances have semiconductor devices. The semiconductor device includes electronic elements such as transistors, resistors, and capacitors, which are designed to perform partial functions of the electronic products and then integrated on the semiconductor substrate. For example, electronic products such as a computer or a digital camera include semiconductor devices such as a memory chip for storing information and a processing chip for controlling information, and the memory chip and the processing chip are semiconductors. And the electronic components integrated on a substrate.

On the other hand, semiconductor devices need to be increasingly integrated to meet consumer demands for superior performance and low cost. As the degree of integration of semiconductor devices increases, the number of design rules decreases and the pattern of semiconductor devices becomes finer. As miniaturization and high integration of a semiconductor device progresses, the overall chip area increases in proportion to an increase in memory capacity, but the area of a cell area where a semiconductor device pattern is formed is actually decreasing. Therefore, in order to secure a desired memory capacity, more patterns must be formed in a limited cell region, so that a fine pattern with a reduced critical dimension of the pattern must be formed.

Among the types of semiconductor devices, a DRAM includes a plurality of unit cells including capacitors and transistors. Among them, a capacitor is used for temporarily storing data, and a transistor is used for transferring data between a bit line and a capacitor corresponding to a control signal (word line) by using the property of a semiconductor whose electrical conductivity changes according to an environment. A transistor consists of three regions: a gate, a source, and a drain. A charge is transferred between the source and the drain in accordance with a control signal input to the gate. The transfer of charge between the source and drain occurs through the channel region, which uses the nature of the semiconductor.

When a conventional transistor is formed on a semiconductor substrate, a gate is formed on a semiconductor substrate and doping is performed on both sides of the gate to form a source and a drain. In this case, the region between the source and the drain under the gate becomes the channel region of the transistor. A transistor having such a horizontal channel region occupies a semiconductor substrate of a certain area. In the case of a complicated semiconductor memory device, it is difficult to reduce the total area due to a plurality of transistors included in the semiconductor memory device.

By reducing the total area of the semiconductor memory device, the number of semiconductor memory devices that can be produced per wafer can be increased and productivity is improved. Various methods have been proposed to reduce the total area of the semiconductor memory device. In place of a conventional planar gate in which one of them has a horizontal channel region, a recess is formed in the substrate and a gate is formed in the recess, thereby forming a recess in which the channel region is formed along the curved surface of the recess A buried gate is formed by embedding the entire gate in the recess in addition to the recessed gate.

The buried gate is connected to the metal contact plug at the edge of the cell mat. As the buried gate is connected to the metal contact plug and the buried gate, the height of the metal contact plug increases and the depth of the metal contact hole also increases.

FIG. 1B is a plan view of a semiconductor device according to the prior art, and FIG. 1B is a cross-sectional view of a semiconductor device taken along the line AA ′ of FIG. 1.

As shown in FIG. 1B, the semiconductor device according to the related art is perpendicular to the gate electrode 14 and the gate electrode 14 embedded in the semiconductor substrate 10 including the device isolation film 12. The metal contact plug 20 includes a bit line 17 arranged to be connected to the gate electrode 14 provided in the cell edge region. In more detail, it demonstrates with reference to FIG. 1 (ii).

As shown in FIG. 1 (ii), the gate electrode 14 embedded in the bottom of the device isolation film 12 of the semiconductor substrate 10 and the gate electrode 14 are disposed on the gate electrode 14 and embedded in the device isolation film 12. The sealing insulating film 16 and the interlayer insulating film 18 provided on the sealing insulating film 16 are formed. Subsequently, a contact hole is formed by etching the interlayer insulating film 18 and the sealing insulating film 16 so that the gate electrode 14 is exposed, and then a metal contact for supplying power to the gate electrode 14 by embedding a conductive layer in the contact hole. The plug 20 is formed.

However, there is no big problem in the case of precisely connecting the gate electrode 14 like the metal contact plug 20c, but the size is increased as in the metal contact plug 20a or the metal contact plug as in the metal contact plug 20b. In the case of misalignment, if the gate electrode 14 is not connected correctly but is connected to the semiconductor substrate 10, a punch may occur to deteriorate the characteristics of the semiconductor device.

The present invention is to solve the problem that when the gate electrode and the metal contact plug is misaligned or the contact plug increases in size, the gate electrode is not connected to the gate electrode and is connected to the semiconductor substrate to deteriorate the characteristics of the semiconductor device.

The semiconductor device of the present invention includes a gate electrode embedded in a semiconductor substrate including a cell region and a cell edge region, a first barrier layer formed on the gate electrode of the cell region, and a second electrode disposed on both ends of the active region. A storage electrode contact plug, a second storage electrode contact plug provided in the gate electrode in the cell edge region, and a metal contact plug provided in an upper portion of the storage electrode contact plug among the adjacent storage electrode contact plugs; It is characterized by including.

And a bit line arranged perpendicular to the gate electrode and connected to a central portion of the active region.

The semiconductor device may further include a first barrier layer formed over the gate electrode of the cell region and a second barrier layer filling the storage electrode contact plug of the cell edge region.

And an interlayer insulating layer disposed on the second barrier layer and the storage electrode contact plug in the cell edge region and filling the gap between the metal contact plugs.

And a third barrier layer connected to one side end of the second barrier layer and parallel to the bit line.

The first barrier film or the second barrier film may include a nitride film.

A method of forming a semiconductor device according to the present invention may include forming a gate electrode embedded in a semiconductor substrate including a cell region and a cell edge region, a first storage electrode contact plug and an upper portion of both ends of the active region in the cell region. Forming a second storage electrode contact plug formed on the gate electrode in a cell edge region, and forming a metal contact plug connected to an upper portion of the storage electrode contact plug of one of the neighboring storage electrode contact plugs; Characterized in that it comprises a,

The forming of the gate electrode may include forming a trench by etching the device isolation layer and the active region, and forming a gate conductive material on the bottom of the trench.

After the forming of the gate electrode, the method may further include forming a sealing insulating layer on the gate electrode to fill the trench.

And forming a bit line connected to the center portion of the active region in the cell region after the forming of the sealing insulating layer.

And forming an interlayer insulating film on the semiconductor substrate after the forming of the bit line, and performing a planarization etching process on the interlayer insulating film to expose the bit line.

After the forming of the bit line, the second barrier layer and the second barrier layer are disposed between the first barrier layer on the gate electrode in the cell region and on the extension line of the first barrier layer in the cell edge region. The method may further include forming a third barrier layer connected to the one end portion.

The forming of the first barrier layer may include forming a first barrier predetermined region by etching the interlayer insulating layer to expose the sealing insulating layer in the cell region, and filling an insulating material in the first barrier predetermined region. Characterized in that it comprises a step.

In the forming of the second barrier layer and the third barrier layer, the interlayer insulating layer may be etched to expose the device isolation layer between the sealing insulating layer in the cell edge region, thereby forming a second barrier predetermined region and the second barrier. Etching the interlayer insulating layer at one end of a predetermined region to be parallel to the bit line to form a third barrier predetermined region, and filling an insulating material in the second barrier predetermined region and the third barrier predetermined region. It is characterized by including.

The forming of the first storage electrode contact plug and the second storage electrode contact plug may include etching the interlayer insulating layers formed on both sides of the first barrier layer and the second barrier layer to form a storage electrode contact hole and the cell edge. And forming a contact hole exposing the gate electrode in the region, and filling a conductive material in the storage electrode contact hole and the contact hole.

The forming of the contact hole may include forming a photoresist pattern covering the cell region and exposing the sealing insulation layer of the cell edge region and exposing the gate electrode with the photoresist pattern as an etch mask. Characterized in that it comprises the step of removing.

The method may further include forming an interlayer insulating layer on the second storage electrode contact plug and the second barrier layer in the cell edge region after the forming of the storage electrode contact plug.

The forming of the metal contact plug may include forming a metal contact hole by etching the interlayer insulating layer to expose an upper portion of the second storage electrode contact plug, and filling a conductive layer in the metal contact hole. It is characterized by including.

The present invention provides an effect of improving the characteristics of the semiconductor device by preventing the problem that the semiconductor substrate and the metal contact plug is connected when the gate metal and the metal contact plug are connected.

FIG. 1B is a plan view showing a semiconductor device according to the prior art, and FIG. 1 (ii) is a cross-sectional view showing a semiconductor device taken along the line A-A 'in FIG.
FIG. 2B is a plan view showing a semiconductor device according to the present invention, and FIG. 2 (ii) is a cross-sectional view showing a semiconductor device taken along the line A-A 'in FIG.
3A to 3I illustrate a method of forming a semiconductor device according to the present invention.
4 is a sectional view showing a semiconductor device according to an embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings in accordance with the present invention will be described in detail.

FIG. 2B is a plan view showing a semiconductor device according to the present invention, and FIG. 2 (ii) is a cross-sectional view showing a semiconductor device taken along the line A-A 'of FIG.

As shown in FIG. 2 (i), the semiconductor device according to the present invention includes an active region 104 defined by an isolation layer 102 in a cell region, and includes a cell edge region. The semiconductor substrate 100 including only the isolation layer 102, the barrier layer 130 provided on the isolation layer 102 and the active region 104, and the bit line 120 perpendicular to the barrier layer 130. ) And a first storage electrode contact plug 138a and a second storage electrode contact plug 138b which fill the gap between the barrier layer 130 and the bit line 120. Here, the barrier layer 130 is formed on the first barrier layer 130a which is arranged perpendicular to the bit line 120 in the cell region and on the extension line of the first barrier layer 130a in the cell edge region. The second barrier layer 130b provided between the first barrier layer 130b and the third barrier layer 130c parallel to the bit line 120 may be included. More specifically, it will be described with reference to Fig. 2 (ii) in Fig. 2 (ii) cut to A-A '.

As shown in FIG. 2 (ii), the gate electrode 106 embedded in the device isolation film 102 in the semiconductor substrate 100 and the second storage electrode contact plug 138b provided on the gate electrode 106 are provided. ), A second barrier layer 130b filling the second storage electrode contact plug 138b, and a metal contact plug 144 provided on the second storage electrode contact plug 138b. . The semiconductor device further includes an interlayer insulating layer 140 disposed on the second barrier layer 130b and the second storage electrode contact plug 138b and filling the metal contact plug 144. Here, the metal contact plug 144 is preferably provided in connection with one of the second storage electrode contact plugs 138b of the second storage electrode contact plugs 138b adjacent to each other.

That is, in the semiconductor device according to the present invention, since the metal contact plug 144 is connected to the second storage electrode contact plug 138b instead of the structure connected to the gate electrode 106, the metal contact plug 144 is connected to the gate electrode ( In the process of connecting with the semiconductor substrate 106, the problem of connecting to the semiconductor substrate 100 due to misalignment or increase in size may be fundamentally solved.

A method of forming a semiconductor device according to the present invention having the above-described configuration is as follows. 3A to 3I illustrate a method of forming a semiconductor device according to the present invention. 3 (a) and 3 (b) show a plan view, and (ii) shows a cross-sectional view taken along line B-B 'of (i). (C) of FIG. 3c-3e and FIG. 3g shows the top view, (ii) shows the sectional drawing which cut BB 'of (iii), and (b) shows A-A' of the top view (iii) The cut section. 3F, 3H, and 3I show a plan view, and (ii) shows a cross-sectional view taken along the line A-A 'of FIG.

As shown in FIG. 3A, a semiconductor substrate including an active region 104 defined by an isolation layer 102 in a cell region and an isolation layer 102 in a cell edge ( After forming the trench in 100, the gate conductive material is embedded in the bottom of the trench to form the gate electrode 106. A sealing insulating layer 108 is formed on the gate electrode 106, and a capping insulating layer 110 is formed on the semiconductor substrate 100 including the sealing insulating layer 108. Subsequently, an interlayer insulating layer 112 is formed on the capping insulating layer 110, and a contact hole is formed by etching the interlayer insulating layer 112 and the capping insulating layer 110 so that the center portion of the active region 104 is exposed. The spacer 113 is formed in the groove. The conductive material is formed to fill the contact hole to form the bit line contact plug 114, and then the bit line electrode 116 and the hard mask layer 118 are formed on the bit line contact plug 114 to form the bit line 120. ). The bit line 120 is preferably arranged perpendicular to the gate electrode 106. Subsequently, a spacer 122 is formed on the sidewall of the bit line 120.

As shown in FIG. 3B, after forming the interlayer insulating layer 124 on the capping insulating layer 110, the planarization etching process is performed on the interlayer insulating layer 124 to expose the hard mask layer 118. Here, the interlayer insulating film 124 preferably includes an oxide film.

As shown in FIG. 3C, after the photoresist pattern 126 is formed on the interlayer insulating layer 124 and the bit line 120, the gate electrode 106 of the cell region is formed using the photoresist pattern 126 as an etch mask. The barrier insulating region 128 is formed by etching the interlayer insulating layer 124 to expose the sealing insulating layer 108 and the device isolation layer 102 at the cell edge.

More specifically, the barrier predetermined region 128 is a first barrier formed by etching the interlayer insulating layer 124 so that the upper portion of the sealing insulating layer 108 is exposed in the cell region as illustrated in (ii) of FIG. 3C. The interlayer insulating film 124 is etched by exposing the device isolation film 102 between the predetermined region 128a and the sealing insulating film 108 in the cell edge region as shown in FIG. 3C. It is preferable to include a second barrier predetermined region 128b and a third barrier predetermined region 128c which is connected to an end of the second barrier predetermined region 128b and etched in parallel with the bit line 120.

As shown in FIG. 3D, an insulating film is embedded in the first barrier predetermined region 128a, the second barrier predetermined region 128b, and the third barrier predetermined region 128c to form a barrier layer 130. For convenience, the insulating film embedded in the first barrier predetermined region 128a is called the first barrier film 130a, and the insulating film embedded in the second barrier predetermined region 128b is called the second barrier film 130b. The insulating film buried in the predetermined region 128c is called a third barrier film 130c. Here, the barrier layer 130 may include a material having an etching selectivity different from that of the interlayer insulating layer 124. Specifically, the barrier film 130 preferably includes a nitride film.

As shown in FIG. 3E, the interlayer insulating layer 124 is exposed such that the interlayer insulating layer 124 and the sealing insulating layer 108 of the cell edge region are exposed to expose both ends of the active region 104 in the cell region. Is etched to form the storage positive electrode contact plug hole 132 and the contact hole 133. The storage electrode contact plug hole 132 may be formed by etching the interlayer insulating layer 124 using a difference in etching selectivity from the barrier layer 130.

As illustrated in FIG. 3F, a photoresist pattern 134 is formed on the second barrier layer 130b so as to cover the cell region and expose the sealing insulation layer 108 of the cell edge region. Here, since the photoresist pattern 134 is used to remove the sealing insulating film 108 of the cell edge region, a cross section of the cell region is omitted and will be described with reference to a cross section of the cell edge region. Subsequently, the sealing insulating layer 108 is removed to expose the gate electrode 106 using the photoresist pattern 134 as an etch mask to form the contact hole 136. After that, the photoresist pattern 134 is preferably removed. Therefore, in this step, the contact hole 136 is formed in the cell edge so that the gate electrode 106 is exposed.

As shown in FIG. 3G, the first storage electrode contact plug 138a is formed by filling a conductive layer in the storage electrode contact plug hole 132 of the cell region and the contact hole 136 of the cell edge region. And a second storage electrode contact plug 138b. Here, the first storage electrode contact plug 138a is formed at both ends of the active region 104 of the cell region as shown in (ii) of FIG. 3G, and is formed on the sealing insulating layer 108. The second storage electrode contact plug 138b is formed on the gate electrode 106 of the cell edge as shown in FIG. 3G. In the cell edge region, after forming the second storage electrode contact plug 138b, it is preferable to form the interlayer insulating layer 140 on the second storage electrode contact plug 138b and the second barrier layer 130b. .

After the formation of the first and second storage electrode contact plugs 138a and 138b, the process is performed around the cell edges. Will be described with reference to the cross-sectional view.

As shown in FIG. 3H, the interlayer insulating layer 140 is etched to expose the upper portion of the second storage electrode contact plug 138b to form the metal contact hole 142. Here, the metal contact hole 142 may be formed to expose one of the second storage electrode contact plugs 138b of the second storage electrode contact plugs 138b adjacent to each other in FIG. 3H (ii).

As shown in FIG. 3I, a conductive material is embedded in the metal contact hole 142 to form a metal contact plug 144. Here, since the metal contact plug 144 is not connected to the gate metal 106 but is connected to the second storage electrode contact plug 138b, the semiconductor contact plug 144 may be misaligned or enlarged in the process of being connected to the gate metal 106. It can fundamentally prevent the short with 100.

As shown in FIG. 4, when the size of the metal contact hole 142 is greatly increased, the metal contact hole 142 is not formed to expose the gate electrode 106 even when the interlayer insulating layer 140 is etched to a large width. Since only the upper portion of the electrode contact plug 138 is formed, the problem that the metal contact plug 144a is connected to the semiconductor substrate 100 may be prevented. In addition, the metal contact plug 144b is connected to the semiconductor substrate 100 because the metal contact hole 142 is misaligned to expose the gate electrode 106 even when only a part of the second storage electrode contact plug 138b is exposed. Can be fundamentally prevented. Accordingly, the metal contact plug 144b in the case of misalignment with the metal contact plug 144a when the size of the metal contact hole 142 is increased is the second storage electrode contact like the metal contact plug 144c formed according to the present invention. It is connected to the plug 138b so as not to be connected to the semiconductor substrate 100.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention as defined by the appended claims. Of the present invention.

Claims (18)

A gate electrode embedded in the semiconductor substrate including the cell region and the cell edge region;
A first barrier layer on the gate electrode of the cell region;
First storage electrode contact plugs disposed on both ends of the active region;
A second storage electrode contact plug provided in the gate electrode dead portion in the cell edge region; And
And a metal contact plug provided on an upper portion of one of the storage electrode contact plugs adjacent to each other. The method according to claim 1,
And a bit line arranged perpendicular to the gate electrode and connected to a central portion of the active region. The method according to claim 1,
A first barrier layer formed over the gate electrode in the cell region; And
And a second barrier layer filling the contact gap between the storage electrode contact plugs of the cell edge region. The method according to claim 3,
And an interlayer insulating layer formed over the second barrier layer and the storage electrode contact plug in the cell edge region and filling the metal contact plug. The method according to claim 2,
And a third barrier layer connected to one end of the second barrier layer and parallel to the bit line. The method according to claim 1,
And the first barrier film or the second barrier film comprises a nitride film. Forming a gate electrode embedded in the semiconductor substrate including the cell region and the cell edge region;
Forming a first storage electrode contact plug on both ends of the active region in the cell region and a second storage electrode contact plug formed on the gate electrode in the cell edge region; And
And forming a metal contact plug connected to an upper portion of one of the storage electrode contact plugs adjacent to each other. The method of claim 7,
Forming the gate electrode
Etching the device isolation layer and the active region to form a trench; And
And forming a gate conductive material on the bottom of the trench. The method according to claim 8,
After forming the gate electrode,
And forming a sealing insulating film over the gate electrode such that the trench is buried. The method according to claim 9,
After forming the sealing insulating film
And forming a bit line in the cell region, the bit line being connected to a central portion of the active region. The method of claim 10,
After forming the bit line
Forming an interlayer insulating film on the semiconductor substrate; And
And performing a planarization etch process on the interlayer insulating layer to expose the bit line. The method of claim 11,
After forming the bit line
Forming a first barrier layer on the gate electrode in the cell region, a second barrier layer provided between the first barrier layer and an extension line of the first barrier layer in the cell edge region, and a third barrier layer connected to one end of the second barrier layer; Method for forming a semiconductor device, characterized in that it further comprises the step. The method of claim 12,
Forming the first barrier film
Etching the interlayer insulating layer to expose the sealing insulating layer in the cell region to form a first barrier predetermined region; And
And embedding an insulating material in the first barrier predetermined region. The method of claim 12,
Forming the second barrier layer and the third barrier layer may include
The interlayer insulating layer is etched to expose the device isolation layer between the sealing insulating layers in the cell edge region, thereby etching the second barrier predetermined region and the interlayer insulating layer at one end of the second barrier predetermined region in parallel with the bit lines. Forming a third barrier predetermined region; And
And embedding an insulating material in the second barrier predetermined region and the third barrier predetermined region. The method of claim 12,
Forming the first storage electrode contact plug and the second storage electrode contact plug
Etching the interlayer insulating layers formed on both sides of the first barrier layer and the second barrier layer to form a contact hole exposing a storage electrode contact hole and the gate electrode of the cell edge region; And
And filling a conductive material in the storage electrode contact hole and the contact hole. The method according to claim 15,
Forming the contact hole
Forming a photoresist pattern covering the cell region and exposing the sealing insulating layer in the cell edge region; And
And removing the sealing insulating layer so that the gate electrode is exposed by using the photoresist pattern as an etch mask. The method of claim 7,
After forming the storage electrode contact plug
And forming an interlayer insulating layer over the second storage electrode contact plug and the second barrier layer in the cell edge region. 18. The method of claim 17,
Forming the metal contact plug
Etching the interlayer insulating layer to expose an upper portion of the second storage electrode contact plug to form a metal contact hole; And
Forming a conductive layer in the metal contact hole.

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