KR20120036927A - Light emitting diode and method of fabricating the same - Google Patents

Abstract

PURPOSE: A light emitting diode and a manufacturing method thereof are provided to improve optical extraction efficiency by differently controlling a tilt angle of a bottom semiconductor layer and a mesa. CONSTITUTION: A plurality of light emitting cells(56) is located on a substrate(51). A transparent electrode layer(61) is located on the upper side of each light emitting cell. A plurality of wires(69) electrically interlinks adjacent light emitting cells. An insulating layer(67) is located between the wires and the light emitting cells. The insulating layer prevents a short circuit within the light emitting cell due to the wires. The light emitting cell comprises a bottom semiconductor layer, an active layer, and a top semiconductor layer. The active layer is placed between the bottom semiconductor layer and the top semiconductor layer.

Description

LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME}

The present invention relates to a light emitting diode and a method of manufacturing the same, and more particularly, to a light emitting diode and a method of manufacturing the light emitting diode connected to each other by wirings on a single substrate, such as a growth substrate.

GaN series LEDs are currently used in a variety of applications, including color LED displays, LED traffic signals, and white LEDs. In recent years, the luminous efficiency of the high efficiency white LED is superior to that of a conventional fluorescent lamp, and thus, it is expected to replace the fluorescent lamp in the general lighting field.

In general, light emitting diodes emit light by forward current and require the supply of direct current. Therefore, when the light emitting diode is directly connected to an AC power source, the LED is repeatedly turned on and off according to the direction of the current. As a result, the light emitting diode does not emit light continuously and is easily damaged by the reverse current.

In order to solve the problem of the light emitting diode, a light emitting diode that can be directly connected to a high voltage AC power source is disclosed in International Publication No. WO 2004/023568 (Al) "Light-Emitting Device Having Light-Emitting Components". EMITTING ELEMENTS, which was disclosed by SAKAI et. Al.

The light emitting diode for alternating current according to WO 2004/023568 (Al) is driven in an AC power source by reversely connecting a plurality of light emitting elements by air bridge wiring. Such air bridge wiring is likely to be disconnected by external pressure, and short circuit is likely to be caused by deformation due to external pressure.

Meanwhile, Korean Patent No. 10-0690323 discloses an AC light emitting diode for preventing disconnection or short circuit of wirings.

1 is a schematic cross-sectional view for explaining the AC light emitting diode of the Republic of Korea Patent No. 10-069023.

Referring to FIG. 1, the light emitting diode includes a substrate 21, a plurality of light emitting cells 26, a transparent electrode layer 31, an insulating layer 37, wires 39, and a protective layer 41. In addition, the light emitting cells 26 include a lower semiconductor layer 25, an active layer 27, and an upper semiconductor layer 29, respectively, and a buffer layer 23 between the substrate 21 and the light emitting cells 26. ) May be intervened.

The light emitting cells 26 are formed by separating the lower semiconductor layer 25, the active layer 27, and the upper semiconductor layer 29 grown on the substrate 21 by using a primary photoresist pattern. In addition, the lower semiconductor layer 25 is exposed in each of the light emitting cell regions using the secondary photoresist pattern, and then the transparent electrode layer 31 is formed on each of the light emitting cells 26 using the tertiary photoresist pattern. do. At this time, by using the primary and secondary photoresist pattern to form a light emitting cells with inclined sidewalls, by forming the wirings 39 thereon, there is provided an AC light emitting diode that can prevent the disconnection or short circuit of the wirings do.

However, since the upper light emitting diode separates the light emitting cell regions by etching the upper semiconductor layer 29, the active layer 27, and the lower semiconductor layer 25 by using the primary photoresist pattern, the sidewalls of the light emitting cell 26 are formed. It usually forms a single slope. Therefore, it is difficult to adjust the inclined surface of the light emitting cell 26, and it is difficult to secure the stability of the wiring 39 formed on the sidewall of the light emitting cell 26. In addition, since a separate photoresist pattern is used to form the transparent electrode layer 31, the transparent electrode layer 31 having a relatively smaller area than the upper surface of the upper semiconductor layer 29 of the light emitting cell 26 is formed. The light emitting region is formed to be substantially narrowed, and the process is complicated and expensive to manufacture.

Patent Document 1: International Publication No. WO 2004/023568 (Al) Patent Document 2: Republic of Korea Patent Publication No. 10-069023

An object of the present invention is to provide a light emitting diode and a method of manufacturing the same, which can improve the stability of the wiring formed on the sidewall of the light emitting cell.

Another object of the present invention is to provide a light emitting diode having a transparent electrode layer providing a relatively wide light emitting region and a method of manufacturing the same.

Another object of the present invention is to provide a light emitting diode and a method of manufacturing the same, which can simplify the process and reduce the manufacturing cost.

In order to solve the above problems, a light emitting diode according to an aspect of the present invention, the light emitting cells are spaced apart from each other on the substrate; A transparent electrode layer on an upper surface of each light emitting cell; Wires for electrically connecting adjacent light emitting cells; And an insulating layer positioned between the wirings and the light emitting cells to prevent a short circuit in the light emitting cell by the wirings. In addition, each of the light emitting cells may include a lower semiconductor layer, an upper semiconductor layer positioned on the lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, wherein the lower semiconductor layer is formed of the light emitting cell. It has a step on its sidewall along the circumference. Since the lower semiconductor layer has a step portion on its sidewall along the circumference of the light emitting cell, it is possible to ensure the stability of the wiring formed on the sidewall of the light emitting cell. In addition, since the inclined surfaces of the lower lower semiconductor layer of the stepped portion and the upper mesas of the stepped portion may be different from each other, light emitting cells having various structures suitable for improving light extraction efficiency may be provided.

An inclination angle between sidewalls of the lower semiconductor layers of each of the light emitting cells and the upper surface of the substrate may be in a range of 15 degrees to 80 degrees. In addition, the inclination angle of the inclined surface of the upper mesa of the stepped portion with the upper surface of the substrate may be in the range of 15 degrees to 80 degrees. Furthermore, the inclination angle of the inclined surfaces of the mesas with the upper surface of the substrate may be different from the inclination angle of the lower semiconductor layer under the mesas.

The transparent electrode layer may be recessed from an edge of the upper semiconductor layer of the light emitting cell and positioned on the upper semiconductor layer. Since the transparent electrode layer is recessed from the edge of the upper semiconductor layer, it is possible to prevent current concentration through the side surface of the light emitting cell. Further, the distance that the transparent electrode layer is recessed from the edge of the upper semiconductor layer may be in the range of 0.01 ~ 5㎛, preferably in the range of 0.5 ~ 2㎛. Therefore, the light emitting area of each light emitting cell can be secured relatively wider than a conventional light emitting diode which forms a transparent electrode layer on the upper semiconductor layer by patterning.

An insulating protective film may cover the wires and the insulating layer. The insulating protective film has an opening that exposes the bonding pads.

A light emitting diode manufacturing method according to another aspect of the present invention includes forming a lower semiconductor layer, an active layer and an upper semiconductor layer on a substrate. A transparent electrode layer is formed on the upper semiconductor layer. Subsequently, a mesa forming process and a cell separation process are performed.

The mesa forming process forms a first photoresist pattern defining mesa regions on the transparent electrode layer, and uses the photoresist pattern as an etching mask to form the lower semiconductor layer together with the transparent electrode layer, the upper semiconductor layer, and the active layer. Etching a portion to form a plurality of mesas.

Meanwhile, the cell separation process may include forming a second photoresist pattern covering the plurality of mesas and defining the light emitting cell regions, and etching the lower semiconductor layer using the second photoresist pattern as an etching mask to electrically interconnect each other. Forming separate light emitting cells.

The first photoresist pattern and the second photoresist pattern are removed after each step of the mesa forming process and the cell separation process is completed.

In particular, after forming the plurality of mesas, the transparent electrode layer may be recessed using a wet etching process while the first photoresist pattern remains. By adjusting the etchant and the etching process time of the wet etching process, the degree of recess of the transparent electrode layer may be adjusted within the range of 0.01 to 5 μm, and preferably within the range of 0.5 to 2 μm.

The mesas may be covered by the second photoresist pattern while etching the lower semiconductor layer using the second photoresist pattern as an etching mask. Therefore, the mesas are not affected by the cell separation process, and the stepped portion is formed along the circumference of the lower semiconductor layer.

In addition, an insulating layer may be continuously formed on the substrate having the light emitting cells, and openings for exposing the lower semiconductor layers by patterning the insulating layer and openings for exposing the upper semiconductor layers may be formed. Wires are formed on the insulating layer to connect adjacent light emitting cells. In addition, an insulating protective film may be formed to cover the wires and the insulating layer.

According to the present invention, it is possible to improve the stability of the wiring by forming a stepped portion along the periphery of the lower semiconductor layer, and by adjusting the inclination angle of the mesa and the lower semiconductor layer below it differently to improve the light extraction efficiency A light emitting diode having light emitting cells having a structure can be provided. Furthermore, in the mesa forming process, the transparent electrode layer and the upper semiconductor layer may be patterned together, thereby reducing the number of mask processes. Furthermore, the transparent electrode layer can be recessed by the wet etching process, so that the degree of recession of the transparent electrode layer can be easily controlled, thereby ensuring a relatively wide light emitting area.

1 is a schematic cross-sectional view for describing a conventional light emitting diode.
2 is a schematic cross-sectional view for describing a light emitting diode according to an embodiment of the present invention.
3 to 8 are schematic cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided as examples to ensure that the spirit of the present invention to those skilled in the art will fully convey. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. In the drawings, the width, length, thickness, and the like of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

2 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 2, the light emitting diode includes a substrate 51, light emitting cells 56, a transparent electrode layer 61, an insulating layer 67, and a wiring 69. In addition, the light emitting diode may include a buffer layer 53 and an insulating protective layer 71.

The substrate 51 may be an insulating or conductive substrate, for example, a sapphire or silicon carbide (SiC) substrate. The plurality of light emitting cells 56 are spaced apart from each other on the single substrate 51. Each of the light emitting cells 56 includes a lower semiconductor layer 55, an upper semiconductor layer 59 positioned on one region of the lower semiconductor layer, and an active layer 57 interposed between the lower semiconductor layer and the upper semiconductor layer. It includes. The lower and upper semiconductor layers are n-type and p-type, or p-type and n-type, respectively.

The lower semiconductor layer 55, the active layer 57, and the upper semiconductor layer 59 may be formed of a gallium nitride-based semiconductor material, that is, (B, Al, In, Ga) N, respectively. The active layer 57 has a composition element and composition ratio determined so as to emit light having a desired wavelength such as ultraviolet light or blue light, and the lower semiconductor layer 55 and the upper semiconductor layer 59 have a bandgap compared to the active layer 57. It is formed of large material.

The lower semiconductor layer 55 or the upper semiconductor layer 59 may be formed as a single layer, as shown, but may be formed in a multilayer structure. In addition, the active layer 57 may have a single quantum well or multiple quantum well structures.

The lower semiconductor layer 55 has a stepped portion formed on a sidewall of the lower semiconductor layer 55. Here, the light emitting cell portion formed above the stepped portion is defined as mesa based on the stepped portion formed in the lower semiconductor layer 55. The mesa sidewall may be inclined such that the width of the mesa becomes narrower as it rises with respect to the upper surface of the substrate 51. The inclination angle of the mesa sidewall with respect to the upper surface of the substrate 51 may be in the range of 15 degrees to 80 degrees. Meanwhile, the lower semiconductor layer 55 positioned below the mesa may also have a sidewall inclined upward from the substrate 51. The inclination angle of the sidewalls of the lower semiconductor layer 55 with respect to the upper surface of the substrate 51 may be in a range of 15 degrees to 80 degrees. Since the lower semiconductor layer 55 has a stepped portion, it helps the continuous deposition of other layers to be formed on the light emitting cells 56, for example, the insulating layer 67 and the wiring 69.

The inclination angle of the mesa sidewall may be the same as the inclination angle of the lower side of the lower semiconductor layer 55, but is not limited thereto. These inclination angles may be adjusted differently. For example, the inclination angle of the mesa sidewall may be smaller than the inclination angle of the sidewall of the lower semiconductor layer 55. Accordingly, light generated in the active layer 57 may be easily emitted through the mesa sidewalls, thereby improving light extraction efficiency and securing a light emitting cell region relatively wide.

Meanwhile, a buffer layer 53 may be interposed between the light emitting cells 56 and the substrate 51. The buffer layer 53 is employed to mitigate lattice mismatch between the substrate 51 and the lower semiconductor layer 55 to be formed thereon when the substrate 51 is a growth substrate.

The transparent electrode layer 61 is positioned on each of the light emitting cells 56. The transparent electrode layer 61 may be located on an upper surface of the upper semiconductor layer 59 and has an area smaller than that of the upper semiconductor layer 59. That is, the transparent electrode layer 61 is recessed from the edge of the upper semiconductor layer 59. Accordingly, it is possible to prevent the current from being concentrated through the sidewalls of the light emitting cells 56 at the edge of the transparent electrode layer 61. Furthermore, the distance that the transparent electrode layer 61 is recessed from the edge of the upper semiconductor layer 59 may be in the range of 0.01 to 5 μm, preferably in the range of 0.5 to 2 μm. In general, in the prior art of forming the transparent electrode layer 61 separately, the distance that the transparent electrode layer 61 is recessed from the edge of the upper semiconductor layer 59 is 5 μm or more due to the limitation of the process margin of the patterning process. In contrast, according to the present invention, the recess distance can be easily adjusted to 5 µm or less, preferably 2 µm or less, thereby increasing the substantial light emitting area as compared with the prior art.

Meanwhile, the insulating layer 67 covers the entire surface of the light emitting cells 56. The insulating layer 67 has openings on the lower semiconductor layers 55 and also has openings on the upper semiconductor layers 59 or the transparent electrode layer 61. Meanwhile, sidewalls of the light emitting cells 56 are covered by the insulating layer 67. The insulating layer 67 may also cover the substrate 51 in the regions between the light emitting cells 56. The insulating layer 67 may be formed of a silicon oxide film (SiO ₂ ) or a silicon nitride film.

Wirings 69 are formed on the insulating layer 67. The wirings 69 are electrically connected to the lower semiconductor layers 55 and the upper semiconductor layers 59 through the openings. The wiring 69 may be electrically connected to the upper semiconductor layer 59 through the transparent electrode layer 61. Meanwhile, the wirings 69 electrically connect the lower semiconductor layers 55 and the upper semiconductor layers 59 of adjacent light emitting cells 56 to form a series array of light emitting cells 56. A plurality of such arrays may be formed, and the plurality of arrays may be connected in reverse parallel to each other and connected to an AC power supply. In addition, a bridge rectifier (not shown) connected to a series array of light emitting cells may be formed, and the light emitting cells may be driven under AC power by the bridge rectifier. The bridge rectifier may be formed by connecting the light emitting cells having the same structure as the light emitting cells 56 using the wirings 69. The wirings may be formed of a conductive material, such as a doped semiconductor material or metal, such as polycrystalline silicon.

Meanwhile, an insulating protective film 71 may cover the wires 69 and the insulating layer 67. The insulating protective film 71 prevents the wires 69 from being contaminated by moisture or the like, and prevents the wires 69 from being damaged by external pressure. The insulating protective film 71 may be formed of a light transmissive material such as a silicon oxide film or a silicon nitride film.

3 to 8 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 3, a lower semiconductor layer 55, an active layer 57, and an upper semiconductor layer 59 are formed on the substrate 51. In addition, before the lower semiconductor layer 55 is formed, the buffer layer 53 may be formed on the substrate 51.

The substrate 51 may include sapphire (Al ₂ O ₃ ), silicon carbide (SiC), zinc oxide (ZnO), silicon (Si), gallium arsenide (GaAs), gallium phosphorus (GaP), and lithium-alumina (LiAl ₂ O). ₃ ), but may be boron nitride (BN), aluminum nitride (AlN) or gallium nitride (GaN) substrate, but is not limited thereto, and may be variously selected according to the material of the semiconductor layer to be formed on the substrate 51. have.

The buffer layer 53 is formed to mitigate lattice mismatch between the substrate 51 and the lower semiconductor layer 55 to be formed thereon, and may be formed of, for example, gallium nitride (GaN) or aluminum nitride (AlN). When the substrate 51 is a conductive substrate, the buffer layer 53 is preferably formed of an insulating layer or a semi-insulating layer, and may be formed of AlN or semi-insulating GaN.

The lower semiconductor layer 55, the active layer 57, and the upper semiconductor layer 59 may be formed of a gallium nitride-based semiconductor material, that is, (B, Al, In, Ga) N, respectively. The lower and upper semiconductor layers 55 and 59 and the active layer 57 use metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy, or hydride vapor phase epitaxy (HVPE) technology. Can be grown intermittently or continuously.

The lower and upper semiconductor layers are n-type and p-type, or p-type and n-type, respectively. In the gallium nitride-based compound semiconductor layer, the n-type semiconductor layer may be formed by doping with silicon (Si) as an impurity, and the p-type semiconductor layer may be formed by doping with magnesium (Mg) as an impurity.

The transparent electrode layer 61 is formed on the upper semiconductor layer 59. The transparent electrode layer 61 may be formed of a conductive oxide such as indium tin oxide (ITO). A first photoresist pattern 63 defining mesa regions is formed on the transparent electrode layer 61. Meanwhile, the photoresist pattern 63 is formed such that sidewalls thereof are inclined with respect to the upper surface of the substrate 51. Such photoresist pattern 63 may be easily formed using positive photoresist, or may be formed by reflowing using negative photoresist. Sidewalls of the photoresist pattern 63 may be formed to have an inclination angle within a range of 15 degrees to 80 degrees with respect to the upper surface of the substrate 51.

Referring to FIG. 4, a portion of the lower semiconductor layer 55 is etched together with the transparent electrode layer 61, the upper semiconductor layer 59, and the active layer 57 using the photoresist pattern 63 as an etching mask. Accordingly, the shape of the photoresist pattern 63 is transferred to the semiconductor layers 59, 57, and 55 to form mesas having sloped sidewalls.

Subsequently, while the first photoresist pattern 63 remains on the mesas, the transparent electrode layer 61 is recessed by a wet etching process. The transparent electrode layer 61 may be recessed within the range of 0.01 to 5 μm, preferably within the range of 0.5 to 2 μm from the edge of the upper semiconductor layer 59 on the mesa by adjusting the etchant and the etching time. Thereafter, the photoresist pattern 63 is removed.

Referring to FIG. 5, a second photoresist pattern 65 is formed to cover the plurality of mesas and define light emitting cell regions. The second photoresist pattern 65 is formed such that the sidewalls thereof are inclined with respect to the upper surface of the substrate 51. The second photoresist pattern 65 may be easily formed using a positive photoresist like the first photoresist pattern 63, or may be formed by reflowing using a negative photoresist. The sidewalls of the photoresist pattern 65 may be formed to have an inclination angle within a range of 15 degrees to 80 degrees with respect to the upper surface of the substrate 51, and may be different from the inclination angle of the sidewalls of the first photoresist pattern 63.

Referring to FIG. 6, light emitting cells 56 are formed by etching the lower semiconductor layer 55 using the second photoresist pattern 65 as an etching mask. In this case, the buffer layer 53 may also be etched together to expose the upper surface of the substrate 51.

Mesas are preferably covered by the second photoresist pattern 65 while the lower semiconductor layer 55 is etched using the second photoresist pattern 65 as an etching mask. Accordingly, it can be prevented from being damaged in the cell separation process of mesas. In addition, as shown in the lower semiconductor layer 55, the stepped portion is generated by the cell separation process. Thereafter, the second photoresist pattern 65 is removed.

Referring to FIG. 7, a continuous insulating layer 67 is formed on a substrate 51 having light emitting cells 56. The insulating layer 67 covers the sidewalls and the top surface of the light emitting cells 56 and covers the upper portion of the substrate 51 in the region between the light emitting cells 56. The insulating layer 67 may be formed of, for example, a silicon oxide film or a silicon nitride film using chemical vapor deposition (CVD) technology.

Since the sidewalls of the light emitting cells 56 are formed to be inclined, and the stepped portion is formed in the lower semiconductor layer 55, the insulating layer 67 may easily cover the sidewalls of the light emitting cells 56.

The insulating layer 67 is patterned by photolithography and etching to form openings 67a exposing the lower semiconductor layer 55 and openings 67b exposing the upper semiconductor layer 59 or the transparent electrode layer 61. Can have

Referring to FIG. 8, wirings 69 are formed on the insulating layer 67 having the openings. The wirings 69 are electrically connected to the lower semiconductor layers 55 and the upper semiconductor layers 59 through the openings 67a and 67b, and the lower semiconductor layers of the adjacent light emitting cells 56. The 55 and the upper semiconductor layers 59 are electrically connected to each other.

The wires 69 may be formed using a vapor deposition technique such as plating technique or electron beam deposition. Since the stepped portions are formed on the sidewalls of the light emitting cells 56, that is, the sidewalls of the lower semiconductor layer 55, the wirings 69 may be stably formed on the sidewalls of the light emitting cells 56. It is possible to prevent disconnection or short circuit of the wiring.

An insulating protective film 71 is formed on the substrate 51 on which the wirings 69 are formed. The protective insulating layer 71 may be formed of a light-transmissive material such as a silicon oxide film or a silicon nitride film by using a chemical vapor deposition technique. As a result, the light emitting diode of FIG. 2 is completed.

51 substrate 56 light emitting cells
61: transparent electrode layer 67: insulating layer
69: wiring

Claims (12)

Light emitting cells spaced apart from each other on a substrate;
Transparent electrode layers on upper surfaces of the light emitting cells;
Wires for electrically connecting adjacent light emitting cells; And
An insulating layer disposed between the wirings and the light emitting cells to prevent a short circuit in the light emitting cell by the wirings;
Each of the light emitting cells includes a lower semiconductor layer, an upper semiconductor layer positioned above the lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, wherein the lower semiconductor layer is formed around the light emitting cell. Along the sidewalls,
The wirings are provided on the stepped portion,
An upper side and a lower side of the light emitting cell have sidewalls based on the stepped portion, and a sidewall of the upper side of the light emitting cell has a smaller inclination angle than a sidewall of the lower side of the light emitting cell. The method according to claim 1,
The side wall of each light emitting cell is formed to be inclined with respect to the upper surface of the substrate so that the width becomes narrower toward the top. The method according to claim 2,
The inclination angle of the sidewalls of the lower semiconductor layer of each of the light emitting cells and the upper surface of the substrate is in the range of 15 degrees to 80 degrees. The method according to claim 1,
The transparent electrode layer is recessed from the edge of the upper semiconductor layer of the light emitting cell is located on the upper semiconductor layer, the distance that the transparent electrode layer is recessed from the edge of the upper semiconductor layer is in the range of 0.5 ~ 2㎛. The method according to claim 1,
The light emitting diode further comprises an insulating protective layer covering the wirings and the insulating layer. Forming a lower semiconductor layer, an active layer and an upper semiconductor layer on the substrate,
Forming a transparent electrode layer on the upper semiconductor layer,
Forming a first photoresist pattern defining mesa regions on the transparent electrode layer,
A portion of the lower semiconductor layer is etched together with the transparent electrode layer, the upper semiconductor layer, and the active layer by using the first photoresist pattern as an etching mask to form a plurality of mesas.
Forming a second photoresist pattern covering the plurality of mesas and defining light emitting cell regions;
The lower semiconductor layer is etched using the second photoresist pattern as an etch mask to form light emitting cells electrically separated from each other.
The lower semiconductor layer has a stepped portion at a sidewall of the lower semiconductor layer,
Wirings are provided on the stepped portion,
The light emitting diode manufacturing method of claim 1, wherein the upper and lower portions of the light emitting cell have sidewalls based on the stepped portions, and the sidewalls of the upper portion of the light emitting cell have smaller inclination angles than the sidewalls of the lower portion of the light emitting cell. The method of claim 6,
After forming the plurality of mesas, further comprising recessing the transparent electrode layer using a wet etching process while the first photoresist pattern remains. The method of claim 6,
Wherein each of the mesas is covered by the second photoresist pattern while etching the lower semiconductor layer using the second photoresist pattern as an etching mask. The method according to claim 8,
Wherein each mesa has an inclination angle within a range of 15 degrees to 80 degrees with respect to the upper surface of the substrate. The method according to claim 9,
The lower semiconductor layer etched using the second photoresist pattern as an etching mask has an inclination angle within a range of 15 degrees to 80 degrees with respect to the upper surface of the substrate. The method of claim 6,
Forming a continuous insulating layer on the substrate having the light emitting cells,
Patterning the insulating layer to form openings exposing the lower semiconductor layers and openings exposing the upper semiconductor layers,
And forming adjacent interconnections on the insulating layer to connect adjacent light emitting cells. The method of claim 11,
And forming an insulating protective film covering the wirings and the insulating layer.

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