KR20130037625A - Light emitting diode and manufacturing method - Google Patents

Abstract

PURPOSE: A light emitting diode and a manufacturing method are provided to prevent the total reflection of the light generated from a light emitting layer by forming a buffer layer including a recess pattern on a light emitting layer, thereby improving optical extraction efficiency. CONSTITUTION: A light emitting layer(110) is formed on a first electrode layer(109). A second electrode layer(113) is formed on the light emitting layer. A buffer layer(108) having a recess pattern(106) is formed. The recess pattern increases the optical extraction efficiency of the light generated from the light emitting layer. The first and the second electrode layer include n-type gallium nitride and p-type gallium nitride. The buffer layer includes anti-polarity gallium nitride.

Description

Light emitting diode and manufacturing method thereof

The present invention relates to a light emitting diode and a method for manufacturing the same, and more particularly to a light emitting diode for producing green light and a method for manufacturing the same.

Recently, gallium nitride (GaN) -based white light emitting diodes (LEDs) have gained attention as next generation lights because they have excellent efficiency over fluorescent lamps. White LEDs for illumination are currently manufactured in various ways, but the most common method is to produce white light by applying a yellow phosphor to a blue LED. Therefore, the research on high efficiency blue LED has developed very much, and its efficiency is also very high. LED is a device that emits light, and when all three primary colors of light are realized, its use is not only general lighting but also emotional lighting, display, medical / bio, and agri-life that realizes various colors. Current technology shows that the external quantum efficiency is over 30% for GaN-based blue LEDs and the external quantum efficiency is over 50% for GaAs-based red LEDs, but the green quantum efficiency is relatively weak and the external quantum efficiency is 10. It is at the level of around%.

1 is a graph showing the external quantum efficiency of each LED of the wavelength.

Referring to FIG. 1, the indium gallium nitride (InGaN) light emitting layer 10 grown on a polar (C-Plane) substrate has a green gap having low efficiency in a wavelength range from 550 nm to 600 nm in the green to yellow wavelength range. (green gap, 12). The green gap 12 is mainly generated by the member of the substrate that is in deep-alignment with the InGaN light emitting layer 10. InGaN light emitting layer 10 of green wavelength is required to have a high indium composition of about 30% or more, and a large amount of strain is likely to occur due to misfit dislocation. Because of this, the lattice mismatch can be minimized when the InGaN light emitting layer 10 is formed on a GaN substrate or a (SiC) substrate. However, large area GaN substrates or SiC substrates are expensive and can reduce productivity. On the other hand, the InGaN light emitting layer 20 grown on the semipolar substrate may have higher efficiency than InGaN grown on the polar substrate without the green gap 12 from the green to the yellow wavelength band of 520 nm to 600 nm. Similarly, the semipolar InGaN light emitting layer 20 has a problem of low productivity because it requires a low-cost, large-area semipolar GaN growth substrate.

The technical problem to be achieved by the present invention is to provide a light emitting diode and a method of manufacturing the same that can maximize the luminous efficiency.

In addition, another technical problem to be achieved by the present invention is to provide a light emitting diode and a manufacturing method thereof that can maximize productivity.

In order to achieve the above technical problem, the light emitting diode of the present invention, the first electrode layer; A light emitting layer on the first electrode layer; A second electrode layer on the light emitting layer; And a buffer layer formed on the second electrode layer and having irregularities that increase extraction efficiency of light generated in the light emitting layer.

According to one embodiment of the invention, the irregularities may have a spacing of less than half each width.

According to another embodiment of the present invention, the irregularities may each have at least one gallium nitride inclined surface.

According to an embodiment of the present invention, the buffer layer may have a semipolar gallium nitride (1-101) flat surface.

According to another embodiment of the present invention, the light emitting layer may include an indium gallium nitride well layer and gallium nitride barrier layers.

According to an embodiment of the present invention, the buffer layer may have a refractive index of 1.22 or more.

According to another exemplary embodiment of the present disclosure, a method of manufacturing a light emitting diode may include forming trenches that partially expose a silicon 111 inclined surface by partially etching a large area silicon 100 substrate; A buffer having a gallium nitride (0001) inclined surface grown on the silicon 111 surfaces in the trenches and a semipolar gallium nitride (1-101) flat surface grown above the upper surface of the silicon 100 substrate. Forming a layer; Forming a first electrode layer on the semipolar gallium nitride (1-101); Forming a light emitting layer on the first electrode layer; Forming a second electrode layer on the light emitting layer; And removing the large area silicon substrate.

According to an embodiment of the present disclosure, the forming of the buffer layer may include forming mask patterns exposing the silicon 111 surfaces of the trenches; Forming semipolar gallium nitride patterns having a gallium nitride inclined surface grown on the silicon (111) surfaces and having the semipolar gallium nitride (1-101) flat surface; And laterally growing the semipolar gallium nitride patterns to connect the semipolar gallium nitride (1-101) flat surface.

According to another embodiment of the present invention, the connecting of the semi-polar gallium nitride (1-101) flat surface may include a metal organic chemical vapor deposition method of the deposition edge overgrowth conditions.

According to an embodiment of the present invention, the silicon 100 substrate may be removed by chemical lift off of the potassium hydroxide solution.

According to another embodiment of the present invention, the forming of the trenches may include forming mask patterns on the large area silicon (100) substrate; Removing portions of the large-area silicon (100) substrate by an etching process using the mask patterns as an etching mask to form the trenches exposing the silicon (111) surface; And removing the mask patterns.

According to one embodiment of the present invention, the etching process may include a wet etching method using a potassium hydroxide solution.

According to another embodiment of the present invention, the mask patterns may include a silicon nitride film.

According to an embodiment of the present invention, the method may further include flip chip bonding the first electrode layer and the second electrode layer to a receptor substrate by means of stud bumps and an ohmic metal layer.

As described above, according to the exemplary embodiment of the present invention, a trench having a silicon 111 inclined plane is formed on the silicon 100 substrate, and the GaN (0001) inclined plane and GaN (1-101) are formed from the silicon 111 inclined plane. A GaN layer having a semipolar plane is grown. Each semipolar GaN layer is switched to a growth mode in which lateral growth is mainly formed to form a buffer layer having a large area of semipolar GaN (1-101) surface covering the entire surface of the silicon substrate. A first electrode layer, a light emitting layer, and a second electrode layer are formed on the buffer layer. Thereafter, the silicon 100 substrate is removed from the buffer layer. GaN irregularities of the buffer layer may increase the light extraction efficiency of the InGaN light emitting layer.

Therefore, the light emitting diode and the manufacturing method thereof according to the embodiment of the present invention can maximize the luminous efficiency and productivity.

1 is a graph showing the external quantum efficiency of each LED of the wavelength.
2 is a cross-sectional view showing a light emitting diode according to an embodiment of the present invention.
3 to 12 are cross-sectional views sequentially illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in different forms. Rather, the embodiments disclosed herein are provided so that the disclosure can be thorough and complete, and will fully convey the concept of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. As used herein, the terms 'comprises' and / or 'comprising' mean that the stated element, step, operation and / or element does not imply the presence of one or more other elements, steps, operations and / Or additions. In addition, since they are in accordance with the preferred embodiment, the reference numerals presented in the order of description are not necessarily limited to the order.

2 is a cross-sectional view showing a light emitting diode according to an embodiment of the present invention.

2, a light emitting diode 100 according to an embodiment of the present invention includes a multi-quantum well light emitting layer 110 between first and second electrode layers 109 and 113 and the first electrode layer 109. It may include a buffer layer 108 having the uneven patterns 106 formed on the (). The uneven patterns 106 of the buffer layer 108 may increase total light extraction efficiency by preventing total reflection of light generated by the multi-quantum well emitting layer 110.

Therefore, the light emitting diode 100 according to the embodiment of the present invention can increase or maximize the luminous efficiency.

The light emitting diodes 100 may be connected on the receptor substrate 117 by stud bumps 119. The receptor substrate 117 mainly uses a silicon substrate. The stud bumps 119 may electrically connect the first electrode layer 109 and the reflective film 116 to the receptor substrate 117. The first ohmic metal layer 115 may be disposed between the first electrode layer 109 and the stud bumps 119. In addition, a base metal layer 118 may be further disposed between the stud bumps 119 and the receptor substrate 117.

The first and second electrode layers 109 and 113 may include n-type gallium nitride (n-GaN) and p-type gallium nitride (p-GaN), respectively. The multi-quantum well emitting layer 110 may include an indium gallium nitride (InGaN) well layer 111 and a gallium nitride (GaN) barrier layer 112 that are alternately stacked. The indium gallium nitride well layer 111 has a lower bandgap than the gallium nitride (GaN) barrier layer 112 and may generate light in the green wavelength band (510 to 560 nm).

The buffer layer 108 may include semipolar gallium nitride (GaN). Semipolar gallium nitride (GaN) may have a refractive index of about 1.22 or more. The buffer layer 108 may include uneven patterns 106 having a semipolar gallium nitride (1-101) flat surface 107 and having a gallium nitride (0001) inclined surface 142. The inclined surface 142 of the gallium nitride (0001) is inclined about 62 degrees with respect to the flat surface 107 of the gallium nitride (1-101). That is, light incident on the flat surface 107 of the semipolar gallium nitride (1-101) can be focused at an angle of about 28 ° or less. In addition, the uneven patterns 106 may emit light incident perpendicularly to the flat surface 107 of the semipolar gallium nitride (1-101) to the outside without total reflection. The uneven patterns 106 may have a distance less than or equal to each half width. For example, the 4 um wide uneven patterns 106 may be spaced at a distance of about 2 um or less. The uneven patterns 106 may increase light extraction efficiency. The uneven patterns 106 are seed layers of the buffer layer 108 and may form a large area semipolar gallium nitride surface.

Therefore, the light emitting diode 100 according to the embodiment of the present invention can maximize the luminous efficiency.

The manufacturing method of the light emitting diode 100 according to the embodiment of the present invention configured as described above is as follows.

3 to 12 are cross-sectional views sequentially illustrating a method of manufacturing a light emitting diode 100 according to an embodiment of the present invention.

Referring to FIG. 3, first, dielectric mask patterns 102 are formed on a large-area Si 100 substrate 101. The dielectric mask patterns 102 may be formed by a patterning process using first photoresist patterns (not shown) as an etching mask. The dielectric mask patterns 102 may include silicon nitride layer (SiNx). The dielectric mask patterns 102 may be formed of stripes. Dielectric mask patterns 102 may cover silicon 100 face 104. The silicon 100 substrate 101 may have a silicon 100 flat surface 104.

Referring to FIG. 4, a trench having an incline side wall of a silicon 111 surface (Si (111) facet, 103) is etched by etching the silicon 100 substrate 101 exposed from the dielectric mask pattern 102. 130 is formed. The silicon 101 substrate 101 may be etched by potassium hydroxide (KOH). For example, potassium hydroxide may be etched with orientation to the silicon 100 surface during etching of the silicon 100 substrate 101. The inclined surface of the silicon 111 may be exposed. In addition, the silicon 100 flat surface 104 may be formed again at the bottom of the trench 130.

Referring to FIG. 5, dielectric mask patterns 102 are removed to form secondary dielectric mask patterns 105 that selectively expose silicon 111 surface 103. The dielectric mask patterns 105 may include (silicon oxide film SiO ₂ ) or silicon nitride film (SiN) formed by chemical vapor deposition (CVD). The dielectric mask patterns 105 may be removed on the silicon 111 surface 103 by an etching process using second photoresist patterns (not shown) formed through a photolithography process as an etching mask.

Referring to FIG. 6, gallium nitride layers (eg, uneven layers 106) having semi-polar surfaces grown from the silicon 111 surfaces 103 are formed. The gallium nitride layers 106 having a semipolar plane may be formed in a triangular shape in the trench 130 by metal organic chemical vapor deposition (MOCVD). Gallium nitride layers 106 having a semipolar plane may be grown on the silicon 111 plane 103 in the <0001> direction. The gallium nitride layers 106 having a semipolar plane are formed of the gallium nitride (0001) inclined plane 142 on the silicon (111) plane 103 and the semipolar gallium nitride (1-101) flat plane 107. Can have

1 and 7, gallium nitride layers 106 having a semipolar plane are laterally grown to form a large area buffer layer 108. The buffer layer 108 may be formed by MOCVD in an epitaxial lateral overgrowth (ELOG) condition. ELOG conditions may include a method of changing growth conditions in MOCVD. The buffer layer 108 may have a large area semipolar gallium nitride (1-101) flat surface 107. In addition, the buffer layer 108 may include uneven patterns 106 of semipolar gallium nitride patterns.

Referring to FIG. 8, a first electrode layer 109, a multi-quantum well emitting layer 110, and a second electrode layer 113 are formed on the buffer layer 108. The first electrode layer 109 may include n-type gallium nitride (n-GaN) formed by a metal organic chemical vapor deposition (MOCVD) method. For example, the first electrode layer 109 may include gallium nitride doped with a first conductive impurity, such as about 3 to 7 x 10 ¹⁸ / cm ³ .

The multi-quantum well emitting layer 110 may include an indium gallium nitride well layer 111 and a gallium nitride barrier layer 112 formed by a MOCVD method. The indium gallium nitride well layer 111 may include indium having a high concentration of about 25% to about 40%. The indium gallium nitride well layer 111 may have a thickness of about 5 nm or less, and the gallium nitride barrier layer 112 may have a thickness of about 10 nm. The multi-quantum well emitting layer 110 may include three to seven pairs of indium gallium nitride well layers 111 and a gallium nitride barrier layer 112.

The second electrode layer 113 may include p-type gallium nitride (p-GaN) formed by MOCVD. For example, the second electrode layer 113 may include gallium nitride doped with a second conductive impurity such as about 5 x 10 ¹⁷ / cm ³ to 1 x 10 ¹⁸ / cm ³ . Although not shown, a stress control layer may be disposed between the first electrode layer 109 and the multi-quantum well emitting layer 110, and between the multi-quantum well emitting layer 110 and the second electrode layer 113. A current blocking layer or an electron blocking layer (EBL) may be disposed.

Referring to FIG. 10, portions of the second electrode layer 113 and the multi-quantum well emitting layer 110 are removed to expose the first electrode layer 109, and the first electrode layer 109 is disposed on the first electrode layer 109. An ohmic metal layer 115 is formed. The first electrode layer 109 may be exposed by contact holes (not shown). Contact holes may be exposed by a dry etching method or a wet etching method of the second electrode layer 113 and the multi-quantum well emitting layer 110 using third photoresist patterns (not shown) as an etching mask. The dry etching method may include an inductive coupled plasma (ICP) method. Contact holes may have a depth of 0.8-1.2 um. In addition, the first ohmic metal layer 115 may be formed by a deposition process of a metal and an etching process of removing metal on the second electrode layer 113 using fourth photoresist patterns (not shown) as an etching mask. It may be formed on the first electrode layer 109 in the contact holes.

Referring to FIG. 11, the reflective layer 116 is formed on the second electrode layer 113. Reflective layer 116 may include a metal layer, such as gold, silver, aluminum, or tungsten. The second electrode layer 116 may be formed by a lift off process of the metal layer deposited on the fifth photoresist patterns (not shown). For example, the lift off process may include forming a metal layer on the first ohmic metal layer 115 and the first electrode layer 109, and forming a metal layer on the second electrode layer 113. It is a process of removing the photoresist patterns and the metal layer formed thereon. In this case, the metal layer may be deposited by a thermal evaporation method, an e-beam evaporation method, a sputter method, or the like. Although not shown, a diffusion barrier may be further formed between the second electrode layer 113 and the reflective film 116.

12, the stud bumps 119, the base electrode layer 118, and the receptor substrate 117 are connected to the reflective layer 116 and the contact electrode layer 115. The receptor substrate 117 may be flipchip bonded to the reflective layer 116 and the contact electrode layer 115 by the stud bumps 119 and the base electrode layer 118. The receptor substrate 117 may include a silicon substrate having high thermal conductivity and high mechanical strength. The stud bumps 110 may include gold (Au) having high ductility.

Referring to FIG. 12, the silicon 100 substrate 101 is removed. The silicon 100 substrate 101 that is opaque to visible light may be removed. The silicon 100 substrate 101 may be removed by a chemical lift-off (CLO) method of potassium hydroxide (KOH) solution. In this case, when the receptor substrate 117 is made of silicon, the receptor substrate 117 may be protected from potassium hydroxide by a photoresist or a protective film. The uneven patterns 106 of the buffer layer 108 may be exposed to the outside by etching the substrate 100 of the silicon 100. The uneven patterns 106 may increase the extraction efficiency of light without performing a separate texturing process on the buffer layer 108.

Therefore, the manufacturing method of the light emitting diodes 100 according to the embodiment of the present invention can maximize productivity.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood. It is therefore to be understood that the above-described embodiments are illustrative and non-restrictive in every respect.

101 silicon substrate 102 dielectric mask patterns
103: silicon 111 inclined surface 104: silicon 100 flat surface
105: dielectric mask patterns 106: semipolar GaN patterns
107: semipolar GaN (1-101) flat surface 108: buffer layer
109: first electrode layers 110: multi-quantum well light emitting layer
111: GaN well layers 112: GaN barrier layer
113: second electrode layer 115: first ohmic metal layer
116: reflective layer 117: receptor substrate
118: base metal layer 119: stud bumps
120: uneven patterns 130: trench
142: semipolar GaN (0001) slope

Claims (14)

A first electrode layer;
A light emitting layer on the first electrode layer;
A second electrode layer on the light emitting layer; And
And a buffer layer formed on the second electrode layer, the buffer layer having irregularities that increase extraction efficiency of light generated in the light emitting layer. The method of claim 1,
The concave-convex light emitting diodes each have an interval of less than half width. The method of claim 2,
The irregularities each have at least one gallium nitride inclined surface. The method of claim 1,
The buffer layer has a semipolar gallium nitride (1-101) flat surface. The method of claim 1,
Wherein the light emitting layer comprises an indium gallium nitride well layer and a gallium nitride barrier layer. The method of claim 1,
The buffer layer has a refractive index of at least 1.22. Partially etching the large area silicon (100) substrate to form trenches exposing the silicon 111 inclined surface;
A buffer having a gallium nitride (0001) inclined surface grown on the silicon 111 surfaces in the trenches and a semipolar gallium nitride (1-101) flat surface grown above the upper surface of the silicon 100 substrate. Forming a layer;
Forming a first electrode layer on the semipolar gallium nitride (1-101);
Forming a light emitting layer on the first electrode layer;
Forming a second electrode layer on the light emitting layer; And
Method of manufacturing a light emitting diode comprising the step of removing the large area silicon (100) substrate. The method of claim 7, wherein
Forming the buffer layer,
Forming mask patterns exposing the silicon (111) surfaces of the trenches;
Forming semipolar gallium nitride patterns having a gallium nitride inclined surface grown on the silicon (111) surfaces and having the semipolar gallium nitride (1-101) flat surface; And
And growing the semipolar gallium nitride patterns laterally to connect the semipolar gallium nitride (1-101) flat surfaces. The method of claim 8,
The connecting step of the semi-polar gallium nitride (1-101) flat surface, the method of manufacturing a light emitting diode comprising a metal organic chemical vapor deposition method of the side growth conditions. The method according to claim 6,
The silicon (100) substrate is a method of manufacturing a light emitting diode is removed by the chemical lift-off of potassium hydroxide solution. The method according to claim 6,
Forming the trenches,
Forming mask patterns on the large area silicon (100) substrate;
Removing portions of the large-area silicon (100) substrate by an etching process using the mask patterns as an etching mask to form the trenches exposing the silicon (111) surface; And
And removing the mask patterns. The method of claim 11,
The etching process is a method of manufacturing a light emitting diode comprising a wet etching method using a potassium hydroxide solution. The method of claim 11,
The mask pattern is a method of manufacturing a light emitting diode comprising a silicon nitride film. The method according to claim 6,
Flip chip bonding the first electrode layer and the second electrode layer to a receptor substrate by means of stud bumps and an ohmic metal layer.

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