KR101272708B1 - Light emitting diode with improved luminous efficiency and method for fabricating the same - Google Patents

Abstract

A light emitting diode having improved luminous efficiency is disclosed. The light emitting diodes include light emitting cells spaced apart from each other on a substrate; A transparent electrode layer on an upper surface of each light emitting cell; Wires for electrically connecting adjacent light emitting cells; An insulating layer disposed between the wirings and the light emitting cells to prevent a short circuit in the light emitting cell by the wirings; And microlenses formed on the light emitting cells and the substrate, wherein each light emitting cell is interposed between a lower semiconductor layer, an upper semiconductor layer positioned above the lower semiconductor layer, and between the lower semiconductor layer and the upper semiconductor layer. An active layer, and the lower semiconductor layer has a stepped portion at a sidewall of the lower semiconductor layer along a circumference of the light emitting cell.

Description

LIGHT EMITTING DIODE WITH IMPROVED LUMINOUS EFFICIENCY AND METHOD FOR FABRICATING THE SAME

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to light emitting diodes, and more particularly, to light emitting diodes having improved luminous efficiency and a method of manufacturing the same.

Since the development of gallium nitride (GaN) -based light emitting diodes, GaN-based LEDs have been used in various applications such as natural color LED display devices, LED traffic signals, and white LEDs.

A gallium nitride-based light emitting diode is generally formed by growing epi layers on a substrate such as sapphire, and includes an N-type semiconductor layer, a P-type semiconductor layer, and an active layer interposed therebetween. Meanwhile, an N-electrode pad is formed on the N-type semiconductor layer, and a P-electrode pad is formed on the P-type semiconductor layer. The light emitting diodes are electrically connected to and driven by an external power source through the electrode pads. At this time, current flows from the P-electrode pad to the N-electrode pad through the semiconductor layers.

In general, since the P-type semiconductor layer has a high specific resistance, current is not evenly distributed in the P-type semiconductor layer, current is concentrated in a portion where the P-electrode pad is formed, and current flows intensively through an edge. Is generated. Current crowing leads to a reduction of the light emitting area, which in turn lowers the light emitting efficiency. In order to solve this problem, a technique of forming a transparent electrode layer having a low specific resistance on the P-type semiconductor layer to achieve current dispersion is used. However, despite the excellent electrical conductivity of the transparent electrode layer, a phenomenon occurs in which current is concentrated around the electrode pad, and the transparent electrode layer may induce a certain amount of light reflection or refraction, but the refractive index difference between the transparent electrode layer and the outside This causes light loss due to total internal reflection.

Since the current flowing from the P-electrode pad is dispersed in the transparent electrode layer and flows into the P-type semiconductor layer, the light emitting area of the light emitting diode can be widened. However, since the transparent electrode layer absorbs light, its thickness is limited, and thus there is a limit in current dispersion. In particular, current dispersion using a transparent electrode layer is limited in a large area light emitting diode of about 1 mm 2 or more used for high power.

To solve this problem, electrode extensions are employed to improve current dispersion in large area light emitting diodes. For example, Korean Patent Publication No. 10-2009-0060271 discloses a light emitting diode having electrode extensions for current dispersion. According to the prior art, the transparent electrode layer is included on the upper surface of the light emitting diode with the structure including the electrode extensions for current dispersion. The transparent electrode layer, along with the electrode extensions, aids in current dissipation.

However, according to the prior art, it is necessary to remove the relatively large area of the active layer and the upper semiconductor layer in order to form the extension and the plurality of n-electrode pads that occupy a relatively large area. Therefore, the light emitting area is considerably reduced and thus the light output is reduced. In addition, although the current can be distributed by adopting a plurality of n- and p-electrode pads, the plurality of electrode pads may reduce the package yield by increasing the number of processes such as a bonding wire process in the future. Furthermore, since the n-electrode pads and the p-electrode pads face each other, it is easy for the current to flow intensively between the electrode pads close to each other, so that light emission in the central region of the light emitting diode may appear uneven.

Meanwhile, a patterned sapphire substrate is generally used to improve light extraction efficiency of a light emitting diode. The pattern on the sapphire substrate reduces the loss of light in the light emitting diode by total internal reflection by scattering or reflecting the light generated in the active layer, thereby improving the light extraction efficiency.

Although light extraction efficiency is expected to be improved by using a pattern on a sapphire substrate, there is still a possibility that light is lost inside the light emitting diode due to total internal reflection because the refractive index of the gallium nitride compound semiconductor is relatively high. Therefore, efforts to improve the light extraction efficiency continue to be demanded.

Korean Patent Publication No. 10-2009-0060271

The problem to be solved by the present invention is to provide a light emitting diode having an improved luminous efficiency and a method of manufacturing the same.

Another object of the present invention is to provide a light emitting diode and a method of manufacturing the same that can improve the light extraction efficiency.

According to an aspect of the invention, the light emitting cells are spaced apart from each other on the substrate; A transparent electrode layer on an upper surface of each light emitting cell; Wires for electrically connecting adjacent light emitting cells; An insulating layer disposed between the wirings and the light emitting cells to prevent a short circuit in the light emitting cell by the wirings; And microlenses formed on the light emitting cells and the substrate, wherein each light emitting cell is interposed between a lower semiconductor layer, an upper semiconductor layer positioned above the lower semiconductor layer, and between the lower semiconductor layer and the upper semiconductor layer. The light emitting diode includes an active layer, and the lower semiconductor layer has a stepped portion at a sidewall of the lower semiconductor layer.

The light emitting diode may further include an insulating protective layer covering the micro lens.

The micro lens may be formed of a material having a refractive index of the transparent electrode layer and an intermediate refractive index of the insulating protective layer.

The micro lens may be formed of a polymer.

The upper semiconductor layer may be a gallium nitride-based semiconductor layer, the transparent electrode layer may be an ITO layer, the microlens may be a polymer, and the insulating protective layer may be formed of SiO ₂ .

The micro lens may have a shape in which the width of the micro lens becomes narrower as the vertical section thereof rises upward from the transparent electrode layer.

The microlens may have a circular, elliptical, hexagonal, rectangular, or triangular cross section at the top of the transparent electrode layer.

The current blocking unit may be SiO ₂ , Al ₂ O ₃ , Si ₃ N _4, or TiO ₂ .

The current blocking unit may be a DBR.

The DBR has a structure in which a low refractive index layer and a high refractive index layer are successively laminated, and the low refractive index layer is SiO ₂ or Al ₂ O ₃ , and the high refractive index layer is Si ₃ N ₄ or TiO ₂ . It may be.

According to another aspect of the present invention, a lower semiconductor layer, an active layer and an upper semiconductor layer are formed on a substrate, a transparent electrode layer is formed on the upper semiconductor layer, and the lower semiconductor is formed together with the transparent electrode layer, the upper semiconductor layer and the active layer. A portion of the layer is etched to form a plurality of mesas, the lower semiconductor layer is etched to form light emitting cells electrically separated from each other, a continuous insulating layer is formed on the substrate having the light emitting cells, and the insulating layer Patterning the openings to expose the lower semiconductor layers and the openings to expose the upper semiconductor layers, and forming wirings on the insulating layer to connect adjacent light emitting cells, and to form a plurality of light emitting cells on the separated light emitting cell and the substrate. Provided is a light emitting diode manufacturing method comprising forming a micro lens of the present invention.

The light emitting diode manufacturing method may further include forming an insulating protective film covering the plurality of micro lenses.

The light emitting diode manufacturing method may further include forming a current blocking layer on a portion of the lower semiconductor layer, the active layer, and / or the upper semiconductor layer.

According to embodiments of the present invention, by forming micro lenses on the transparent electrode layer, it is possible to greatly increase the light extraction efficiency. In addition, the current blocking layer formed on the lower portion of the wiring allows the current to flow uniformly with respect to the entire area of the light emitting diode, thereby providing a current dispersion effect of reducing the current concentration phenomenon in which the current is concentrated around the electrode.

1 is a schematic cross-sectional view for describing a light emitting diode according to an embodiment of the present invention.
2 to 5 are schematic cross-sectional views for describing a light emitting diode manufacturing method according to an embodiment of the present invention.
6 is a plan view for explaining various shapes of a microlens.
7 and 8 are photographs for explaining the shape of the micro lens.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The following embodiments are provided by way of example so that those skilled in the art can fully understand the spirit of the present invention. Therefore, the present invention is not limited to the embodiments described below, but may be embodied in other forms. And in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. Like numbers refer to like elements throughout.

1 is a cross-sectional view illustrating a light emitting diode according to an embodiment of the present invention.

Referring to FIG. 1, the light emitting diode includes a substrate 51, light emitting cells 56, a transparent electrode layer 61, an insulating layer 67, a wiring 69, a micro lens 71, and an insulating protective film 72. ). In addition, the light emitting diode may include a buffer layer 53.

The substrate 51 may be an insulating or conductive substrate, for example, a sapphire or silicon carbide (SiC) substrate. The plurality of light emitting cells 56 are spaced apart from each other on the single substrate 51. Each of the light emitting cells 56 is disposed between the lower semiconductor layer 55, the upper semiconductor layer 59 positioned on one region of the lower semiconductor layer, and the lower semiconductor layer 55 and the upper semiconductor layer 59. And an intervening active layer 57. The lower and upper semiconductor layers are n-type and p-type, or p-type and n-type, respectively.

The lower semiconductor layer 55, the active layer 57, and the upper semiconductor layer 59 may be formed of a gallium nitride-based semiconductor material, that is, (B, Al, In, Ga) N, respectively. The active layer 57 has a composition element and composition ratio determined so as to emit light having a desired wavelength such as ultraviolet light or blue light, and the lower semiconductor layer 55 and the upper semiconductor layer 59 have a bandgap compared to the active layer 57. It is formed of large material.

The lower semiconductor layer 55 and / or the upper semiconductor layer 59 may be formed as a single layer, as shown, but may be formed in a multilayer structure. In addition, the active layer 57 may have a single quantum well or multiple quantum well structures.

The lower semiconductor layer 55 has a stepped portion formed on a sidewall of the lower semiconductor layer 55. Here, the light emitting cell portion formed above the stepped portion is defined as mesa based on the stepped portion formed in the lower semiconductor layer 55. The mesa sidewall may be inclined such that the width of the mesa becomes narrower as it rises with respect to the upper surface of the substrate 51. The inclination angle of the mesa sidewall with respect to the upper surface of the substrate 51 may be in the range of 15 degrees to 80 degrees. Meanwhile, the lower semiconductor layer 55 positioned below the mesa may also have a sidewall inclined upward from the substrate 51. The inclination angle of the sidewalls of the lower semiconductor layer 55 with respect to the upper surface of the substrate 51 may be in a range of 15 degrees to 80 degrees. Since the lower semiconductor layer 55 has a stepped portion, it helps the continuous deposition of other layers to be formed on the light emitting cells 56, for example, the insulating layer 67 and the wiring 69.

The inclination angle of the mesa sidewall may be the same as the inclination angle of the lower side of the lower semiconductor layer 55, but is not limited thereto. These inclination angles may be adjusted differently. For example, the inclination angle of the mesa sidewall may be smaller than the inclination angle of the sidewall of the lower semiconductor layer 55. Accordingly, light generated in the active layer 57 may be easily emitted through the mesa sidewalls, thereby improving light extraction efficiency and securing a light emitting cell region relatively wide.

Meanwhile, each of the light emitting cells 56 may have a current blocking layer 58 under the wiring 69. The current blocking layer 58 may be formed in the lower semiconductor layer 55, the active layer 57, or the upper semiconductor layer 59. The current blocking layer 58 blocks current flowing directly from the wiring 69 formed on the upper semiconductor layer 59 to enable wide current diffusion in the transparent electrode layer 61. As the current blocking layer 58, an insulating material such as SiO ₂ , Al ₂ O ₃ , Si ₃ N _4, or TiO ₂ may be used, and the distributed bragg reflector formed by alternately stacking materials having different refractive indices. May be). The DBR may have a structure in which a low refractive index layer and a high refractive index layer are successively stacked, for example, the low refractive index layer is SiO ₂ or Al ₂ O ₃ is used, the high refractive index layer is Si ₃ N ₄ or TiO ₂ can be used.

Meanwhile, a buffer layer 53 may be interposed between the light emitting cells 56 and the substrate 51. The buffer layer 53 is employed to mitigate lattice mismatch between the substrate 51 and the lower semiconductor layer 55 to be formed thereon when the substrate 51 is a growth substrate.

The transparent electrode layer 61 is positioned on each light emitting cell 56. The transparent electrode layer 61 may be located on an upper surface of the upper semiconductor layer 59 and has an area smaller than that of the upper semiconductor layer 59. That is, the transparent electrode layer 61 may be recessed from the edge of the upper semiconductor layer 59. Accordingly, it is possible to prevent the current from being concentrated through the sidewall of the light emitting cell 56 at the edge of the transparent electrode layer 61.

Meanwhile, the insulating layer 67 covers the entire surface of the light emitting cells 56. The insulating layer 67 has openings on the lower semiconductor layers 55 and also has openings on the upper semiconductor layers 59 or the transparent electrode layer 61. Meanwhile, sidewalls of the light emitting cells 56 are covered by the insulating layer 67. The insulating layer 67 may also cover the substrate 51 in the regions between the light emitting cells 56. The insulating layer 67 may be formed of a silicon oxide film (SiO ₂ ) or a silicon nitride film.

Wirings 69 are formed on the insulating layer 67. The wirings 69 are electrically connected to the lower semiconductor layers 55 and the upper semiconductor layers 59 through the openings. The wiring 69 may be electrically connected to the upper semiconductor layer 59 through the transparent electrode layer 61. Meanwhile, the wirings 69 electrically connect the lower semiconductor layers 55 and the upper semiconductor layers 59 of adjacent light emitting cells 56 to form a series array of light emitting cells 56. A plurality of such arrays may be formed, and a plurality of arrays may be connected in antiparallel to each other and connected to an AC power source to be driven. Further, a bridge rectifier (not shown) connected to the serial array of the light emitting cells may be formed, and the light emitting cells may be driven by the bridge rectifier under the AC power. The bridge rectifier may be formed by connecting the light emitting cells having the same structure as the light emitting cells 56 using the wirings 69. The wirings may be formed of a conductive material, such as a doped semiconductor material or metal, such as polycrystalline silicon.

The micro lens 71 covers the wirings 69 and the insulating layer 67. The microlens 71 has a hemispherical convex surface and can function as a convex lens. The horizontal diameter of the micro lens 71 may be a micrometer size, such as about 9 μm. The micro lens 71 may be formed of a material having a refractive index lower than that of the transparent electrode layer 69, for example, a polymer. Polymers are, for example, polymers such as polymide (PI), epoxy resin (SU-8), spin on glass (SOG) poly methylmethacrylate (PMMA), poly dimethylsioxane (PDMS), poly carbonate (PC), silicone gel ) Or resin may be used. The refractive index of the transparent electrode layer 69 and / or the microlens 71 may vary depending on the refractive index of the material layer in contact therewith. However, when the upper semiconductor layer is a gallium nitride semiconductor layer having a refractive index of approximately 2.45, the ITO layer having a refractive index of 2.04 is When SiO ₂ having a refractive index of 1.54 is used as the insulating protective film 72, the refractive index of the microlenses is selected within 1.67 to 1.8, which is an intermediate refractive index of the transparent electrode layer 69 and the insulating protective film 72. It is good to be used. It is preferable that the microlens has insulation, but it may be considered to have conductivity.

On the other hand, the insulating protective film 72 may cover the micro lens 71. The insulating protective film 72 prevents the microlens 71 and the wirings 69 from being contaminated by moisture or the like, and prevents the wirings 69 from being damaged by external pressure. The insulating protective layer 72 may be formed of a light transmissive material such as silicon oxide (SiO ₂ ) or silicon nitride.

2 to 5 are cross-sectional views illustrating a method of manufacturing a light emitting diode according to an embodiment of the present invention.

2, a lower semiconductor layer 55, an active layer 57, and an upper semiconductor layer 59 are formed on a substrate 51. In addition, before the lower semiconductor layer 55 is formed, the buffer layer 53 may be formed on the substrate 51.

The substrate 51 may include sapphire (Al ₂ O ₃ ), silicon carbide (SiC), zinc oxide (ZnO), silicon (Si), gallium arsenide (GaAs), gallium phosphorus (GaP), and lithium-alumina (LiAl ₂ O). ₃ ), but may be boron nitride (BN), aluminum nitride (AlN) or gallium nitride (GaN) substrate, but is not limited thereto, and may be variously selected according to the material of the semiconductor layer to be formed on the substrate 51. have.

The buffer layer 53 is formed to mitigate lattice mismatch between the substrate 51 and the semiconductor layer 55 to be formed thereon, and may be formed of, for example, gallium nitride (GaN) or aluminum nitride (AlN). When the substrate 51 is a conductive substrate, the buffer layer 53 is preferably formed of an insulating layer or a semi-insulating layer, and may be formed of AlN or semi-insulating GaN.

The lower semiconductor layer 55, the active layer 57, and the upper semiconductor layer 59 may be formed of a gallium nitride-based semiconductor material, that is, (B, Al, In, Ga) N, respectively. The lower and upper semiconductor layers 55 and 59 and the active layer 57 use metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy, or hydride vapor phase epitaxy (HVPE) technology. Can be grown intermittently or continuously.

The lower and upper semiconductor layers are n-type and p-type, or p-type and n-type, respectively. In the gallium nitride-based compound semiconductor layer, the n-type semiconductor layer may be formed by doping silicon (Si) as an impurity, for example, and the p-type semiconductor layer may be formed by doping magnesium (Mg) as an impurity.

The current blocking layer 58 is formed in the lower portion of the wiring 69 in the region of the upper semiconductor layer 59, and the partial region of the lower semiconductor layer 55, the active layer 57 and / or the upper semiconductor layer 59 is formed. Can be formed on. As the current blocking layer 58, an insulating material such as SiO ₂ , Al ₂ O ₃ , Si ₃ N _4, or TiO ₂ may be used, and the current blocking layer 58 may be a DBR formed by alternately stacking materials having different refractive indices.

The transparent electrode layer 61 is formed on the current blocking layer 58 and the upper semiconductor layer 59. The transparent electrode layer 61 may be formed of a conductive oxide such as indium tin oxide (ITO). Subsequently, a portion of the lower semiconductor layer 55 is etched together with the transparent electrode layer 61, the upper semiconductor layer 59, and the active layer 57 using a photoresist pattern (not shown) as an etching mask. Accordingly, the shape of the photoresist pattern is transferred to the semiconductor layers 59, 57, and 55 to form mesas having sloped sidewalls.

Subsequently, while the photoresist pattern remains on the mesas, the transparent electrode layer 61 may be recessed by a wet etching process. The transparent electrode layer 61 may be recessed from an edge of the upper semiconductor layer 59 on the mesa by adjusting an etchant and an etching time. Thereafter, the photoresist pattern is removed.

Thereafter, the lower semiconductor layer 55 is etched using a photoresist pattern (not shown) covering the plurality of mesas and defining the light emitting cell regions, thereby forming separated light emitting cells 56. In this case, the buffer layer 53 may also be etched together to expose the upper surface of the substrate 51.

The mesas are preferably covered by the photoresist pattern while the lower semiconductor layer 55 is etched using the photoresist pattern as an etching mask. Accordingly, it can be prevented from being damaged in the cell separation process of mesas. In addition, as shown in the lower semiconductor layer 55, the stepped portion is generated by the cell separation process. Thereafter, the photoresist pattern is removed.

Referring to FIG. 3, a continuous insulating layer 67 is formed on a substrate 51 having light emitting cells 56. The insulating layer 67 covers the sidewalls and the top surface of the light emitting cells 56 and covers the upper portion of the substrate 51 in the region between the light emitting cells 56. The insulating layer 67 may be formed of, for example, a silicon oxide film or a silicon nitride film using chemical vapor deposition (CVD) technology.

Since the sidewalls of the light emitting cells 56 are formed to be inclined, and the stepped portion is formed in the lower semiconductor layer 55, the insulating layer 67 may easily cover the sidewalls of the light emitting cells 56.

The insulating layer 67 may have openings that are patterned by photolithography and etching to expose the lower semiconductor layer 55, and openings that expose the upper semiconductor layer 59 or the transparent electrode layer 61.

Referring to FIG. 4, wirings 69 are formed on the insulating layer 67 having the openings. The wirings 69 are electrically connected to the lower semiconductor layers 55 and the upper semiconductor layers 59 through the openings, and the lower semiconductor layers 55 and the upper semiconductors of adjacent light emitting cells 56. Each of the layers 59 is electrically connected.

The wires 69 may be formed using a vapor deposition technique such as plating technique or electron beam deposition. Since the stepped portions are formed on the sidewalls of the light emitting cells 56, that is, the sidewalls of the lower semiconductor layer 55, the wirings 69 may be stably formed on the sidewalls of the light emitting cells 56. Disconnection and / or short circuit of the wiring can be prevented.

Referring to FIG. 5, a micro lens 71 is formed on a substrate 51 on which the wires 69 are formed. The microlens 71 may be formed using a wet etching process after forming a polymer layer on the substrate 51 on which the wirings 69 are formed. The micro lens 71 may cover a portion of the first conductivity type lower semiconductor layer 23 exposed by the mesa sidewall and the mesa etching. Alternatively, the microlens 71 may be formed by forming a polymer layer and then forming a photoresist pattern (not shown) to correspond to the lens shape using a reflow technique or the like, and dry etching the polymer layer using this as an etching mask. May be formed.

6 is a plan view for explaining various shapes of a microlens.

On the other hand, as shown in Figure 6 (a), the micro lens 71 may be circular or elliptical in plan view. That is, the horizontal cross section of the micro lens may be circular or elliptical. However, the horizontal cross section of the micro lens 71 is not limited to a circle or an ellipse, and may be a hexagon or a triangle as shown in FIGS. 6 (b) and 6 (c), or may be a quadrangle. In particular, when the horizontal cross-sectional shape of the microlenses is hexagonal or triangular, these microlenses 71 can be arranged more densely.

The shape of the micro lens may be variously selected in consideration of ease of manufacture, light extraction efficiency, and the like, and may be selected by appropriately combining the shape of the horizontal cross section and the vertical cross section. When the vertical cross section is a triangular shape and the horizontal cross section is a triangular shape as shown in FIG. 6C, the microlens may have a triangular pyramid, that is, a tetrahedral shape. Accordingly, the light incident on the micro lens can be easily emitted to the outside.

In addition, the micro lens 71 may have a smooth surface as shown in FIG. 7, or may be formed to have a rough surface on the surface as shown in FIG. 8. As such, by arranging the microlenses 71 having various shapes on the transparent electrode layer 69 and the mesa sidewalls, light generated in the active layer 25 may be emitted to the outside through the microlenses 71 to improve light extraction efficiency. It can be improved.

The protective insulating film 72 is formed on the substrate 51 on which the microlenses 71 are formed. The protective insulating layer 72 may be formed of a light transmissive material such as a silicon oxide film or a silicon nitride film by using a chemical vapor deposition technique. As a result, the light emitting diode of FIG. 1 is completed.

51 substrate 53 buffer layer
55 lower semiconductor layer 56 light emitting cell
57: active layer 58: current blocking layer
59: upper semiconductor layer 61: transparent electrode layer
67 insulation layer 69 wiring
71: microlens 72: insulating protective film

Claims (13)

Light emitting cells spaced apart from each other on a substrate;
A transparent electrode layer on an upper surface of each light emitting cell;
Wires for electrically connecting adjacent light emitting cells;
An insulating layer disposed between the wirings and the light emitting cells to prevent a short circuit in the light emitting cell by the wirings; And
Including microlens,
Each of the light emitting cells includes a lower semiconductor layer, an upper semiconductor layer positioned above the lower semiconductor layer, and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, wherein the lower semiconductor layer surrounds the light emitting cell. Along the sidewalls,
Each of the light emitting cells is provided such that sidewalls of at least one of the lower semiconductor layer, the active layer, and the upper semiconductor layer are inclined with respect to the substrate,
The micro lens is a light emitting diode positioned on the transparent electrode layer, the wiring, the insulating layer and the side walls of the light emitting cells. The method according to claim 1,
The light emitting diode further comprises an insulating protective film covering the micro lens. The light emitting diode of claim 2, wherein the microlens is formed of a material having a refractive index of the transparent electrode layer and an intermediate refractive index of the insulating protective layer. The light emitting diode of claim 3, wherein the micro lens is formed of a polymer. The light emitting diode of claim 4, wherein the upper semiconductor layer is a gallium nitride based semiconductor layer, the transparent electrode layer is an ITO layer, and the insulating protective layer is formed of SiO ₂ . The light emitting diode of claim 1, wherein the microlens has a shape in which the width of the microlens becomes narrower as the vertical section thereof rises upward from the transparent electrode layer. The method according to claim 1,
The microlens is a light emitting diode, characterized in that the horizontal cross-section on the transparent electrode layer is a circular, elliptical, hexagonal, square or triangular. The method according to claim 1,
Each of the light emitting cells is provided in at least an upper semiconductor layer, and includes a current blocking layer provided in a predetermined area corresponding to a lower portion of the wiring.
The current blocking layer is a light emitting diode, characterized in that SiO ₂ , Al ₂ O ₃ , Si ₃ N ₄ or TiO ₂ . The method according to claim 1,
Each of the light emitting cells further includes a current blocking layer,
The current blocking layer is provided in at least an upper semiconductor layer of each of the light emitting cells, and is provided in a predetermined area corresponding to a lower portion of the wiring,
The current blocking layer is a light emitting diode, characterized in that the DBR. The method according to claim 9,
The DBR has a structure in which a low refractive index layer and a high refractive index layer are continuously stacked repeatedly,
The low refractive index layer is SiO ₂ or Al ₂ O ₃ is used,
The high refractive index layer is a light emitting diode, characterized in that Si ₃ N ₄ or TiO ₂ is used. Forming a lower semiconductor layer, an active layer and an upper semiconductor layer on the substrate,
Forming a transparent electrode layer on the upper semiconductor layer,
A portion of the lower semiconductor layer is etched together with the transparent electrode layer, the upper semiconductor layer, and the active layer to form a plurality of mesas.
Etching the lower semiconductor layer to form light emitting cells electrically separated from each other,
Forming a continuous insulating layer on the substrate having the light emitting cells,
Patterning the insulating layer to form openings exposing the lower semiconductor layers and openings exposing the transparent electrode layers,
Wirings are formed on a substrate on which the insulating layer is formed, wherein each of the wirings includes a lower semiconductor layer of one of the light emitting cells and a transparent electrode layer of a light emitting cell neighboring the one of the light emitting cells. Connecting through the openings exposing the layer and the transparent electrode layer to connect adjacent light emitting cells,
Forming a polymer layer on the substrate on which the light emitting cells, the transparent electrode layer, the wirings, and the insulating layer are formed, and then etching a part of the polymer layer to form a plurality of micro lenses;
Each of the light emitting cells is provided such that sidewalls of at least one of the lower semiconductor layer, the active layer, and the upper semiconductor layer are inclined with respect to the substrate,
The plurality of micro lenses are formed on the transparent electrode layer, the wiring, the insulating layer and the side walls of the light emitting cells. The method of claim 11,
The method of claim 1, further comprising forming an insulating protective film covering the plurality of micro lenses. The method of claim 11,
Before forming a lower semiconductor layer, an active layer and an upper semiconductor layer on the substrate, and before forming the transparent electrode layer,
And forming a current blocking layer provided in at least a portion of the upper semiconductor layer corresponding to the lower portion of the wiring.

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