KR20120024288A - Method for plating layer of substrate) - Google Patents

Method for plating layer of substrate) Download PDF

Info

Publication number
KR20120024288A
KR20120024288A KR1020100087125A KR20100087125A KR20120024288A KR 20120024288 A KR20120024288 A KR 20120024288A KR 1020100087125 A KR1020100087125 A KR 1020100087125A KR 20100087125 A KR20100087125 A KR 20100087125A KR 20120024288 A KR20120024288 A KR 20120024288A
Authority
KR
South Korea
Prior art keywords
plating layer
copper
seed
hole
circuit board
Prior art date
Application number
KR1020100087125A
Other languages
Korean (ko)
Inventor
문정호
오상혁
Original Assignee
삼성전기주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전기주식회사 filed Critical 삼성전기주식회사
Priority to KR1020100087125A priority Critical patent/KR20120024288A/en
Priority to JP2011192424A priority patent/JP2012060121A/en
Priority to US13/225,963 priority patent/US20120055800A1/en
Publication of KR20120024288A publication Critical patent/KR20120024288A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
    • H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0338—Layered conductor, e.g. layered metal substrate, layered finish layer or layered thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

PURPOSE: A method for forming a coating layer of a printed circuit board is provided to form a copper coating layer of a uniform thickness by successively advancing a first coating process and a second coating process when manufacturing the printed circuit board. CONSTITUTION: A penetration hole is processed on CCL(Copper Clad Lamination)(10). A seed coating layer(20) is formed on the penetration hole. Resist(40) is spread on the CCL and seed coating layer. A dry film is exposed and developed on the seed coating layer. A first coating layer(50) is formed on the seed coating layer. A copper coating layer(60) is formed on the first coating layer. The resist and the seed coating layer remaining on the first coating layer are eliminated. A pattern is formed.

Description

인쇄회로기판의 도금층 형성 방법{METHOD FOR PLATING LAYER OF SUBSTRATE)}Plating layer formation method of printed circuit board {METHOD FOR PLATING LAYER OF SUBSTRATE)}

본 발명은 인쇄회로기판의 도금층 형성 방법에 관한 것으로, 보다 상세하게는 기판의 회로패턴 부위와 관통홀 부위에 균일한 두께의 동도금층을 형성하도록 하는 인쇄회로기판의 도금층 형성 방법에 관한 것이다.
The present invention relates to a method of forming a plated layer of a printed circuit board, and more particularly, to a method of forming a plated layer of a printed circuit board to form a copper plating layer having a uniform thickness in the circuit pattern portion and the through-hole portion of the substrate.

전자기기의 소형화 및 다기능화에 따라 인쇄회로기판도 다양한 기능을 요구받고 있다. 특히 SIP(System in package)의 경우 열적 전기적 우수성이 요구되고 있다. 이런 열적, 전기적 특성을 강화하기 위하여 기존 마이크로 비아 홀로 가공되던 홀을 관통홀(PTH: Plated through hole)로 변경하여 그 특성을 강화하는 시도가 많아지고 있다. 그러나 SIP용 관통홀의 충진 도금은 좁은 피치와 넓은 홀 사이즈 등의 제약으로 인하여 도금의 한계성이 많으며, 특히, 넓은 관통홀을 충진시키기 위해서는 고전류 밀도의 도금이 필요하기 때문에 회로패턴 부위와 관통홀 부위의 도금 두께 편차가 심하게 되어 도금 두께의 균일성을 만족시키지 못하는 문제점이 발생된다.With the miniaturization and multifunction of electronic devices, printed circuit boards are also required for various functions. Especially in the case of SIP (System in package), thermal and electrical excellence is required. In order to reinforce these thermal and electrical characteristics, attempts to reinforce the characteristics by changing holes that have been processed into conventional micro via holes into plated through holes (PTH) are being made. However, the filling plating of SIP through-holes has a lot of plating limitations due to the narrow pitch and the wide hole size. Especially, in order to fill wide through-holes, high current density plating is required. Since the plating thickness variation is severe, there is a problem that does not satisfy the uniformity of the plating thickness.

종래의 SIP용 관통홀의 도금방법에 대해 아래 도시된 도면을 통해 살펴보면 다음과 같다.Looking at the conventional method for plating the through hole for SIP through the drawings shown below are as follows.

도 1a~1f는 일반적인 방법으로 가공된 종래의 SIP용 관통홀의 도금방법이다.1A to 1F illustrate a plating method of a conventional through hole for SIP processed by a general method.

동박적층판(COPPER CLAD LAMINATION, 이하 'CCL'이라고 함)(10)에 회로의 층간 접속을 위하여 관통홀 형성하며, 상기 관통홀 형성 방법으로는 기계적인 방법(CNC, 레이저 가공 등)이 사용되어 지며,(도 1b), 시드 도금층(20)은 무전해 또는 전해 도금법을 이용하여 CCL(10) 상에 동박이 형성된다.(도 1c). 상기 시드 도금층(20) 상에 레지스트(40)을 적층하고 상기 레지스트(40)을 노광 및 현상(도 1d)한 후 전해도금법을 이용하여 동도금층(60) 형성한다.(도 1e). 이때, 상기 관통홀(11)에 동도금층(60)이 형성되게 될 때, 상기 관통홀(11) 부분에 전류밀도가 높게 형성되고, 관통홀(11)의 좁은 피치로 인하여 상기 회로패턴(61) 부분의 동도금층(60)과 상기 관통홀(11) 부분의 동도금층(61)이 균일하게 형성되지 않는 문제점이 지적되고 있다.
Through-holes are formed in the copper clad laminate (COPPER CLAM LAMINATION, hereinafter referred to as 'CCL') 10 for interlayer connection of circuits, and mechanical methods (CNC, laser machining, etc.) are used as the through-hole forming method. The seed plating layer 20 is formed of copper foil on the CCL 10 by using an electroless or electrolytic plating method (FIG. 1C). After the resist 40 is laminated on the seed plating layer 20, the resist 40 is exposed and developed (FIG. 1D), and a copper plating layer 60 is formed by using an electroplating method (FIG. 1E). At this time, when the copper plating layer 60 is formed in the through-hole 11, the current density is formed in the portion of the through-hole 11, the circuit pattern 61 due to the narrow pitch of the through-hole 11 It has been pointed out that the copper plating layer 60 of the () part and the copper plating layer 61 of the through hole 11 are not uniformly formed.

따라서, 본 발명은 종래에 제기되고 있는 문제점을 해결하기 위하여 창안된 것으로서, 인쇄회로기판 제작시 1차 도금과 2차 도금을 순차적으로 진행하여 도금 두께의 차이를 극복하고 보다 안정적인 도금을 할 수 있는 방법이 제공됨에 발명에 목적이 있다.
Therefore, the present invention was devised to solve the problems posed in the related art. In the manufacture of a printed circuit board, the first plating and the second plating may be sequentially performed to overcome the difference in plating thickness and to provide more stable plating. It is an object of the invention to provide a method.

본 발명의 상기 목적은, CCL(COPPER CLAD LAMINATION)에 관통홀을 가공하는 단계, 상기 관통홀에 시드 도금층을 형성하는 단계, 상기 CCL과 상기 시드 도금층 상에 레지스트을 도포하는 단계, 상기 시드 도금층 상에 상기 드라이 필름을 노광 및 현상하는 단계, 상기 시드 도금층 상에 1차 도금층을 형성하는 단계, 상기 1차 도금층 상에 동도금층을 형성하는 단계 및 상기 1차 도금층 상에 남아 있는 레지스트와 시드 도금층을 제거하여 패턴을 형성하는 단계를 포함하는 인쇄회로기판의 도금층 형성 방법이 제공됨에 의해서 달성된다.The object of the present invention is to process a through hole in CCL (COPPER CLAD LAMINATION), forming a seed plating layer in the through hole, applying a resist on the CCL and the seed plating layer, on the seed plating layer Exposing and developing the dry film, forming a primary plating layer on the seed plating layer, forming a copper plating layer on the primary plating layer, and removing the resist and seed plating layer remaining on the primary plating layer. It is achieved by providing a plating layer forming method of a printed circuit board comprising the step of forming a pattern.

또한, 상기 관통홀은 기계적 수단과 화학적 수단으로 형성될 수 있다.In addition, the through hole may be formed by mechanical means and chemical means.

또한, 상기 기계적 수단은 드릴, 레이져 가공이 될 수 있으며, 화학적 수단으로는 에칭이 될 수 있다.In addition, the mechanical means may be drilled, laser processing, the chemical means may be etching.

또한, 상기 1차 도금층의 두께는 3~5um으로 형성될 수 있다.In addition, the thickness of the primary plating layer may be formed of 3 ~ 5um.

또한, 상기 1차 도금층의 도금 두께는 약전류 0.5A/dm2~1.0A/dm2이하의 전류 밀도에 의해 진행될 수 있다.In addition, the plating thickness of the primary plating layer may be advanced by a current density of about 0.5A / dm 2 to 1.0A / dm 2 or less.

또한, 상기 동도금층의 두께는 상기 1차 도금층 위에 20~25um으로 형성 될 수 있다.In addition, the thickness of the copper plating layer may be formed of 20 ~ 25um on the primary plating layer.

또한, 상기 동도금층의 도금 두께는 고전류 1.5A/dm2~2.0A/dm2 이상의 전류밀도에 의해 진행될 수 있다.
In addition, the plating thickness of the copper plating layer may be advanced by a current density of 1.5A / dm 2 to 2.0A / dm 2 or higher.

본 발명의 인쇄회로기판의 도금층 형성 방법은 1차 도금과 2차 도금을 진행함으로써, 관통홀 피치가 좁고 관통홀 체적이 큰 SIP 제품군에서 회로패턴 부위와 관통홀 부위의 충진되는 동도금층의 도금 두께 편차를 작게 할 수 있는 장점이 있다.
In the method of forming a plating layer of the printed circuit board of the present invention, the plating thickness of the copper plating layer filled with the circuit pattern portion and the through hole portion in the SIP product family is narrowed by the first plating and the second plating. There is an advantage that the deviation can be made small.

도 1은 종래의 관통홀을 구비한 CCL의 도금 방법.
도 2는 비아홀과 관통홀의 동도금층 비교도.
도 3은 본 발명의 관통홀을 구비한 동도금층 형성 순서도
도 4는 종래의 도금 방법과 본 발명의 도금방법 비교 그래프.
도 5는 종래의 도금 방법에 의한 동도금층과 본 발명의 도금방법에 의한 동도금층 비교 확대도.1 is a plating method of a CCL having a conventional through hole.
Figure 2 is a comparison of the copper plating layer of the via hole and the through hole.
Figure 3 is a flow chart forming copper plated layer having a through hole of the present invention
Figure 4 is a graph of the conventional plating method and the plating method of the present invention.
5 is a comparative enlarged view of a copper plating layer by a plating method of the present invention and a copper plating layer by a conventional plating method.

본 발명에 따른 인쇄회로기판의 도금층 형성 방법에 대한 기술적 구성을 비롯한 작용효과에 관한 상항은 본 발명의 바람직한 실시예가 도시된 도면을 참조하여 아래의 상세한 설명에 의해서 명확하게 이해될 것이다.The above-mentioned matters relating to the operational effects including the technical configuration of the plating layer forming method of the printed circuit board according to the present invention will be clearly understood by the following detailed description with reference to the drawings in which preferred embodiments of the present invention are shown.

그러나 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 수 있다. 본 실시예들은 본 발명의 개시가 완전하도록 하고, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공될 수 있다.The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. The embodiments may be provided to make the disclosure of the present invention complete, and to fully inform the scope of the invention to those skilled in the art.

도 2를 참조하여 설명하면, 도 2a처럼 CCL(10) 상에 비아홀(12)을 형성한 경우 상기 비아홀(12)의 상면과 하면의 비아홀(12) 직경의 차이로 인하여, 상기 비아홀(12) 하면에 레진 잔사가 남아 때문에 신뢰성에 취약하다. 반면, 상기 CCL(10) 상에 관통홀(11)을 형성한 경우에는 상기 관통홀(11)의 내측면에 레진 잔사가 남는 문제점이 발생하지 않기 때문에, 전자기기의 소형화 및 다기능화에 따라 인쇄회로 기판에 적용되고 있다.Referring to FIG. 2, when the via hole 12 is formed on the CCL 10 as shown in FIG. 2A, due to the difference between the diameter of the via hole 12 on the upper and lower surfaces of the via hole 12, the via hole 12 is formed. Resin residues remain on the bottom side, making it vulnerable to reliability. On the other hand, when the through hole 11 is formed on the CCL 10, since the resin residue does not remain on the inner surface of the through hole 11, printing is performed according to the miniaturization and multifunctionality of the electronic device. It is applied to a circuit board.

도 3을 참조하여 본 발명의 실시예에 따른 인쇄회로기판의 도금층 형성 방법에 대하여 상세히 설명한다.A method of forming a plating layer of a printed circuit board according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 3.

본 발명의 실시예에 따른 인쇄회로기판의 도금층 형성 방법은 CCL(COPPER CLAD LAMINATION)(10)에 관통홀(11)을 가공하는 단계, 상기 CCL(10)과 상기 관통홀(11)에 시드 도금층(20)을 형성하는 단계, 상기 시드 도금층(20) 상에 레지스트(40)을 도포하는 단계, 상기 레지스트(40)을 노광 및 현상하는 단계, 상기 시드 도금층(20) 상에 1차 도금층(50)을 형성하는 단계, 상기 1차 도금층(50) 상에 동도금층(60)을 형성하는 단계 및 상기 1차 도금층(50)에 남아 있는 레지스트(40)과 상기 시드 도금층(20)을 제거하는 단계를 포함하여 이루어진다.In the method of forming a plating layer of a printed circuit board according to an embodiment of the present invention, the step of processing the through-hole 11 in the CCL (COPPER CLAD LAMINATION) 10, the seed plating layer in the CCL (10) and the through-hole (11) Forming (20), applying a resist (40) on the seed plating layer (20), exposing and developing the resist (40), and first plating layer (50) on the seed plating layer (20). ), Forming the copper plating layer 60 on the primary plating layer 50 and removing the resist 40 and the seed plating layer 20 remaining in the primary plating layer 50. It is made, including.

여기서, 상기 CCL(COPPER CLAD LAMINATION, 이하 'CCL'이라함)(10)은 2~3um의 동박층을 가질 수 있으며, 상기 동박층의 소재는 에폭시(Epoxy or Modified Epoxy), 폴리 이미드(Polyimide), 폴리에틸렌 테레프탈레이드(PET, Polyethyeleneterepthalate), 사이아나이드 에스테르(Cyanide Ester) 등으로 이루어 질 수 있다.Here, the CCL (COPPER CLAD LAMINATION, hereinafter referred to as 'CCL') 10 may have a copper foil layer of 2 ~ 3um, the material of the copper foil layer is epoxy (Epoxy or Modified Epoxy), polyimide (Polyimide) ), Polyethylene terephthalate (PET, Polyethyeleneterepthalate), cyanide ester (Cyanide Ester) and the like.

상기 CCL(10)에 관통홀(11)을 형성하는 방법으로는 기계적인 가공 방법인 드릴과 레이저 등이 사용할 수 있으며, 또한 화학적 에칭 방법으로도 관통홀(11)을 형성할 수 있으나, 본 발명은 이에 한정하지 않고, 여러 가지 방법으로 관통홀(11)를 형성할 수 있다.(도 3a)As a method of forming the through hole 11 in the CCL 10, a drill and a laser, which is a mechanical processing method, may be used, and the through hole 11 may also be formed by a chemical etching method. The present invention is not limited thereto, and the through hole 11 may be formed in various ways (FIG. 3A).

상기 CCL(10)과 상기 관통홀(11)에 시드 도금층(20)을 형성하는 방법은 무전해 및 전해도금을 있을 수 있으나, 본 발명은 이에 한정하지 않고, 여러 가지 방법으로 시드 도금층(20)을 형성할 수 있다.The method of forming the seed plating layer 20 in the CCL 10 and the through hole 11 may be electroless and electroplating, but the present invention is not limited thereto, and the seed plating layer 20 may be formed in various ways. Can be formed.

상기 시드 도금층(20) 상에 레지스트(40)을 도포하는 단계에서 상기 레지스트는 여러 종류가 있을 수 있으나, 가장 범용적으로 사용되는 드라이필름을 이용하여 상기 시드 도금층(20) 상에 도포한다.(도 3b)In the step of applying the resist 40 on the seed plating layer 20, the resist may be various, but is applied on the seed plating layer 20 using a dry film which is most widely used. 3b)

상기 시드 도금층(20) 상에 상기 레지스트(40)가 도포된 상태에서 회로패턴(61)를 형성하기 위해서는 마스크(Mask)(30)을 이용하여 상기 레지스트(40)을 노광(Exposure) 하게 된다. 상기 노광(Exposure)은 Subtractive 공법과는 반대로 상기 회로패턴(61)이 형성되는 부분에는 빚을 노출 시키지 않고 그 외의 다른 부분들을 빚에 노출시키며, 상기 빚에 노출된 부분들은 경화(polymerization)된다.(도 3c)In order to form the circuit pattern 61 in the state in which the resist 40 is coated on the seed plating layer 20, the resist 40 is exposed using a mask 30. In contrast to the subtractive method, the exposure does not expose the debt to the portion where the circuit pattern 61 is formed, and exposes other portions to the debt, and the portions exposed to the debt are polymerized. (FIG. 3C)

상기 현상(Development) 공정에서는 빚에 노출된 상기 레지스트(40) 부분들이 현상액(탄산나트륨)에 의해 용해되어 제거된다.(도 3d)In the development process, portions of the resist 40 exposed to debt are dissolved and removed by a developer (sodium carbonate) (FIG. 3D).

상기 시드 도금층(20) 상에 1차 도금층(50)을 형성하는 단계는 약전류인 0.5A/dm2~1.0A/dm2 의 전류밀도를 인가하여 3~5um의 1차 도금층(50)을 형성한다. 상기 1차 도금층(50)을 형성함으로써, 상기 회로패턴(61) 부위와 상기 관통홀(11) 부위의 동도금층(60)의 두께 차이를 줄일 수 있다.(도 3e)The forming of the primary plating layer 50 on the seed plating layer 20 may be performed by applying a current density of 0.5 A / dm 2 to 1.0 A / dm 2 , which is a weak current, to form the primary plating layer 50 having a size of 3 to 5 μm. Form. By forming the primary plating layer 50, the thickness difference between the copper plating layer 60 between the circuit pattern 61 portion and the through hole 11 portion can be reduced (FIG. 3E).

상기 1차 도금층(50)상에 동도금층(60)을 형성하는 단계는 상기 약전류가 인가되어 3~5um의 1차 도금층(50) 형성된 CCL(10) 상에 고전류 1.5A/dm2 ~2.0A/dm2 의 전류밀도를 인가하여 25um의 상기 동도금층(60)을 형성한다.(도 3f)Forming the copper plating layer 60 on the primary plating layer 50 is the weak current is applied to the high current 1.5A / dm 2 on the CCL (10) formed with a primary plating layer 50 of 3 ~ 5um The copper plating layer 60 of 25 um was formed by applying a current density of ˜2.0 A / dm 2 (FIG. 3F).

상기 관통홀(11) 내에는 약전류에 의해 1차 도금층(50)이 확보되었기 때문에 상기 회로패턴(61) 대비 상기 관통홀(11) 내의 동도금층(60)의 충진 속도가 빨라 관통홀(11) 주위 영역의 도금이 기존 공법에 비해 상대적으로 낮게 형성되어 회로패턴(61)부와 관통홀(11)의 동도금층(61)의 단차가 작아지게 된다.Since the primary plating layer 50 is secured by the weak current in the through hole 11, the filling speed of the copper plating layer 60 in the through hole 11 is faster than that of the circuit pattern 61. The plating of the peripheral area is relatively lower than that of the existing method, so that the step between the circuit pattern 61 and the copper plating layer 61 of the through hole 11 is reduced.

상기 1차 도금층(50)에 남아있는 레지스트(40)와 시드 도금층(20)을 제거하는 단계에서는 상기 레지스트(40)는 수산화나트륨 용액을 이용하여 제거하게 된다.In the step of removing the resist 40 and the seed plating layer 20 remaining in the first plating layer 50, the resist 40 is removed using a sodium hydroxide solution.

상기 1차 도금층(50)과 상기 시드층(20)은 에칭액을 이용하여 제거하게 되며, 에칭액으로는 염화동 용액이나 염화철 용액 또한, 황산이나 황산과산화수소의 약품이 주로 사용된다.(도 3g)The primary plating layer 50 and the seed layer 20 are removed using an etching solution, and copper etching solution, iron chloride solution, and sulfuric acid or hydrogen sulfate peroxide are mainly used as the etching solution.

도 4 및 도 5는 종래의 도금 방법과 본 발명의 도금 방법을 비교한 것이다..4 and 5 compare the conventional plating method with the plating method of the present invention.

도 4는 종래의 도금 방법과 본 발명의 도금방법 비교 그래프이다.4 is a graph comparing the conventional plating method and the plating method of the present invention.

상기 회로패턴(61)의 동도금층(60)과 상기 관통홀(11)의 동도금층(60)의 단차가 최대 10um 이하 일 때의 동도금층(60)의 두께를 나타낸 것으로 종래의 도금방법의 경우 평균 동도금층(60)의 두께가 40um 정도였으나, 본 발명의 도금 방법의 경우에는 평균 34um정도의 동도금층(60)을 형성할 수 있어, 이것은 약 5um 정도 도금 두께를 낮추었을 경우에도 상기 동도금층(60)의 형성이 가능하다.The thickness of the copper plating layer 60 when the step between the copper plating layer 60 of the circuit pattern 61 and the copper plating layer 60 of the through hole 11 is 10 μm or less in the case of the conventional plating method Although the average copper plating layer 60 had a thickness of about 40 μm, in the case of the plating method of the present invention, the copper plating layer 60 having an average of about 34 μm can be formed, which is even when the plating thickness is reduced by about 5 μm. The formation of 60 is possible.

도 5에서는 종래의 도금 방법에 의한 동도금층과 본 발명의 도금방법에 의한 동도금층 비교 확대도이다.In FIG. 5, the copper plating layer by the conventional plating method is compared with the copper plating layer by the plating method of this invention.

상기 종래의 도금방법으로는 상기 동도금층(60) 형성시 상기 관통홀(11) 주위의 영역에서 동도금층(60)이 높게 도금되며, 이러한 현상은 피치가 좁은 관통홀(11)에서 고전류 밀도를 인가하여 동도금층(60)을 형성 할 때 더욱 많이 발생한다. 반면, 본 발명의 도금방법의 경우에는 상기 관통홀(11) 주위의 영역에서 상기 동도금층(60)이 높게 형성되지 않는 것을 확인할 수 있다.In the conventional plating method, when the copper plating layer 60 is formed, the copper plating layer 60 is plated high in a region around the through hole 11. This phenomenon results in a high current density in the through hole 11 having a narrow pitch. When applied to form a copper plating layer 60 is more generated. On the other hand, in the case of the plating method of the present invention, it can be seen that the copper plating layer 60 is not formed high in the region around the through hole 11.

이상, 본 발명의 바람직한 실시예를 참조로 본 발명의 인쇄회로기판의 도금층 형성 방법에 대하여 설명하였지만, 본 발명의 사상을 벗어나지 않는 범위 내에서 수정, 변경 및 다양한 변형 실시예가 가능함은 당업자에게 명백하다.
The plating layer forming method of the printed circuit board of the present invention has been described above with reference to a preferred embodiment of the present invention, but it is apparent to those skilled in the art that modifications, changes, and various modifications can be made without departing from the spirit of the present invention. .

10: CCL 11: 관통홀
12: 비아홀 20: 시드 층
30: 마스크 40: 레지스트
50: 1차 도금층 60: 동도금층
61: 회로패턴10: CCL 11: Through Hole
12: via hole 20: seed layer
30 mask 40 resist
50: primary plating layer 60: copper plating layer
61: circuit pattern

Claims (7)

CCL(COPPER CLAD LAMINATION)에 관통홀을 가공하는 단계;
상기 관통홀에 시드 도금층을 형성하는 단계;
상기 CCL과 상기 시드 도금층 상에 레지스트을 도포하고, 상기 드라이 필름을 노광 및 현상하는 단계;
상기 시드 도금층 상에 1차 도금층을 형성하는 단계;
상기 1차 도금층 상에 동도금층을 형성하는 단계 및
상기 1차 도금층 상에 남아 있는 레지스트과 시드 도금층을 제거하여 패턴을 형성하는 단계;를 포함하는 인쇄회로기판의 도금층 형성 방법.
Machining the through holes in CCL (COPPER CLAD LAMINATION);
Forming a seed plating layer in the through hole;
Applying a resist on the CCL and the seed plating layer, and exposing and developing the dry film;
Forming a primary plating layer on the seed plating layer;
Forming a copper plating layer on the primary plating layer; and
Forming a pattern by removing the resist and the seed plating layer remaining on the primary plating layer.
제 1항에 있어서,
상기 관통홀은 기계적 수단과 화학적 수단으로 형성될 수 있는 인쇄회로기판의 도금층 형성 방법.
The method of claim 1,
The through hole may be formed by a mechanical means and a chemical means plating layer forming method of a printed circuit board.
제 2항에 있어서,
상기 기계적 수단은 드릴, 레이져 가공이 될 수 있으며, 화학적 수단으로는 에칭이 될 수 있는 인쇄회로기판의 도금층 형성 방법.
The method of claim 2,
The mechanical means may be a drill, laser processing, the chemical means can be etched plating layer forming method of a printed circuit board.
제 1항에 있어서,
상기 1차 도금층의 두께는 3~5um으로 형성된 인쇄회로기판의 도금층 형성 방법.
The method of claim 1,
The thickness of the primary plating layer is a plating layer forming method of a printed circuit board formed of 3 ~ 5um.
제 4항에 있어서,
또한, 상기 1차 도금층의 도금 두께는 약전류 0.5A/dm2~1.0A/dm2이하의 전류 밀도에 의해 진행되는 인쇄회로 기판의 도금층 형성 방법.
The method of claim 4, wherein
In addition, the plating thickness of the primary plating layer is a plating layer forming method of the printed circuit board is advanced by a current density of about 0.5A / dm 2 ~ 1.0A / dm 2 or less.
제 1항에 있어서,
상기 동도금층의 두께는 상기 1차 도금층 위에 20~25um으로 형성된 인쇄회로기판의 도금층 형성 방법.
The method of claim 1,
The thickness of the copper plating layer is a plating layer forming method of a printed circuit board formed in 20 ~ 25um on the primary plating layer.
제 6항 있어서,
상기 동도금층의 도금 두께는 고전류 1.5A/dm2~2.0A/dm2 이상의 전류밀도에 의해 진행되는 인쇄회로기판의 도금층 형성 방법.The method of claim 6,
The plating thickness of the copper plating layer is a plating layer forming method of a printed circuit board is advanced by a current density of 1.5A / dm 2 ~ 2.0A / dm 2 or more high current.
KR1020100087125A 2010-09-06 2010-09-06 Method for plating layer of substrate) KR20120024288A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1020100087125A KR20120024288A (en) 2010-09-06 2010-09-06 Method for plating layer of substrate)
JP2011192424A JP2012060121A (en) 2010-09-06 2011-09-05 Method for forming plated layer of printed board
US13/225,963 US20120055800A1 (en) 2010-09-06 2011-09-06 Method for forming plating layer of printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100087125A KR20120024288A (en) 2010-09-06 2010-09-06 Method for plating layer of substrate)

Publications (1)

Publication Number Publication Date
KR20120024288A true KR20120024288A (en) 2012-03-14

Family

ID=45769868

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100087125A KR20120024288A (en) 2010-09-06 2010-09-06 Method for plating layer of substrate)

Country Status (3)

Country Link
US (1) US20120055800A1 (en)
JP (1) JP2012060121A (en)
KR (1) KR20120024288A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103491728B (en) * 2013-09-30 2016-06-08 电子科技大学 The working method of a kind of printed electronic circuit board blind hole and fine-line

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5139923A (en) * 1987-07-08 1992-08-18 Hitachi, Ltd. Method for improving adhesion of a resist layer to a metallic layer and electrolessly plating a wiring pattern thereon
JPH10303561A (en) * 1997-04-30 1998-11-13 Hitachi Chem Co Ltd Multi-layer wiring board and its manufacture
JP4052434B2 (en) * 2001-02-05 2008-02-27 Ｔｄｋ株式会社 Multilayer substrate and manufacturing method thereof
JP2002368425A (en) * 2001-06-08 2002-12-20 Toppan Printing Co Ltd Printed circuit board and its manufacturing method
JP2003110241A (en) * 2001-09-28 2003-04-11 Kyocera Corp Wiring board and electronic equipment using the same
JP3976564B2 (en) * 2001-12-20 2007-09-19 日本リーロナール有限会社 Via filling method
KR100632552B1 (en) * 2004-12-30 2006-10-11 삼성전기주식회사 Fill plating structure of inner via hole and manufacturing method thereof
JP2007109706A (en) * 2005-10-11 2007-04-26 Matsushita Electric Ind Co Ltd Process for producing multilayer printed wiring board
WO2011062037A1 (en) * 2009-11-20 2011-05-26 イビデン株式会社 Printed circuit board and manufacturing method of printed circuit board

Also Published As

Publication number Publication date
US20120055800A1 (en) 2012-03-08
JP2012060121A (en) 2012-03-22

Similar Documents

Publication Publication Date Title
CN106376184B (en) Embedded type circuit production method and package substrate
US8143533B2 (en) Method for forming resist pattern, method for producing circuit board, and circuit board
CN108617104B (en) Method for manufacturing printed circuit board with thickened copper local pattern
JP6819608B2 (en) Multi-layer printed wiring board and its manufacturing method
KR101019150B1 (en) Manufacturing method of printed circuit board having via-on-pad structure
JP2019046860A (en) Printed-circuit board and manufacturing method thereof
US9402318B2 (en) Printed wiring board
TW202211739A (en) Method for manufacturing printed wiring board
KR20160002361A (en) Print wiring substrate and manufacturing method thereof
KR100772432B1 (en) Method of manufacturing printed circuit board
US8074352B2 (en) Method of manufacturing printed circuit board
US20140042122A1 (en) Method of manufacturing printed circuit board
KR100869049B1 (en) Semi-additive pcb manufacturing method with employing uv sensitive polyimide lamination
JP2015043408A (en) Printed circuit board and manufacturing method of the same
KR101070798B1 (en) PCB and manufacturing method thereof
JP4730222B2 (en) Wiring board manufacturing method
TWI636720B (en) Circuit board structure and method for fabricating the same
KR20100109698A (en) Method of manufacturing a printed circuit board
KR20120024288A (en) Method for plating layer of substrate)
CN110519917B (en) Method for manufacturing through hole
CN109788661B (en) Flexible circuit board and preparation method thereof
JPH036880A (en) Printed wiring board and manufacture thereof
JP2016025307A (en) Wiring board manufacturing method and wiring board
JP2005108941A (en) Multilayer wiring board and its manufacturing method
KR101009118B1 (en) A method for manufacturing of landless printed circuit board

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
AMND Amendment
J201 Request for trial against refusal decision
J301 Trial decision

Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20120802

Effective date: 20131018