KR20120015882A - Light emitting device package - Google Patents

Abstract

PURPOSE: A light emitting device package is provided to improve the optical extraction efficiency of a light emitting device by forming a pad electrode in the lower side of a package body and minimizing light suspension due to a pad. CONSTITUTION: A light emitting structure(110) is on the upper side of a package body(120b). The light emitting structure comprises a first electrical conductive semiconductor layer, an active layer, a second electrical conductive semiconductor layer. A second electrode pad(152) is included in the lower side of the package body. A first electrode pad(151) is electrically connected to the first electrical conductive semiconductor layer. Passivation(130) is placed in the package body and between the light emitting structure and the first electrode pad.

Description

Light emitting device package {LIGHT EMITTING DEVICE PACKAGE}

Embodiments relate to a light emitting device package, a method for manufacturing the same, and an illumination system.

A light emitting device may be generated by combining elements of group III and group V on a periodic table of a p-n junction diode having a characteristic in which electrical energy is converted into light energy. LED can realize various colors by adjusting the composition ratio of compound semiconductors.

When the forward voltage is applied, the n-layer electrons and the p-layer holes combine to emit energy corresponding to the energy gap of the conduction band and the valence band. It is mainly emitted in the form of heat or light, and when it is emitted in the form of light, it becomes a light emitting device.

For example, nitride semiconductors are receiving great attention in the field of optical devices and high power electronic devices due to their high thermal stability and wide bandgap energy. In particular, blue light emitting devices, green light emitting devices, and ultraviolet light emitting devices using nitride semiconductors are commercially used and widely used.

Conventional light emitting devices can be classified into a lateral type and a vertical type according to the position of the electrode layer, and the vertical type light emitting devices are wire-bonded to the n electrode to inject current from the outside. For the p electrode, eutectic bonding was used.

However, in the light emitting device package according to the related art, as the wire bonding pad for the n electrode is positioned on the upper portion of the light emitting structure, external light extraction efficiency of the emitted light may be inhibited, and the light emitting pad may exist to emit light. There was a difficulty in carrying out a conformal coating on the device chip.

The embodiment can improve the light extraction efficiency of the light emitting device, and to provide a light emitting device package, a manufacturing method and an illumination system of which a conformal coating is useful on the light emitting device chip.

The light emitting device package according to the embodiment includes a package body; A light emitting structure on a top surface of the package body, the first conductive semiconductor layer, the second conductive semiconductor layer, an active layer between the first conductive semiconductor layer and the first conductive semiconductor layer; A second electrode pad on the bottom surface of the package body; A first electrode pad on the bottom surface of the package body while being electrically connected to the first conductive semiconductor layer; And a passivation interposed between the package body and the light emitting structure and the first electrode pad.

In addition, the method of manufacturing a light emitting device package according to the embodiment comprises the steps of preparing a package body; Forming a light emitting structure including an active layer between a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and the first conductivity type semiconductor layer and the first conductivity type semiconductor layer; Attaching the second conductive semiconductor layer of the light emitting structure to the upper surface of the package body; Separating the package body and the light emitting structure in units of chips; Forming a second electrode pad on a bottom surface of the package body; And forming a first electrode pad electrically connected to the first conductivity type semiconductor layer through passivation on the bottom surface of the package body.

In addition, the lighting system according to the embodiment includes a light emitting unit having the light emitting device package.

According to the embodiment, by forming the pad electrode under the package body, light blocking efficiency of the light emitting device can be improved by minimizing light blocking by the pad. Also, since the pad electrode is not on the light emitting device, conformal coating is performed on the light emitting device chip. This useful light emitting device package, its manufacturing method and lighting system can be provided.

In addition, the embodiment uses a silicon (silicone) having a three-dimensional (3D) structure as a substrate and the n-electrode and p-electrode (p-electrode) are both located at the bottom of the substrate (wire bonding) Without the need for (wire bonding), the SMT process and the eutectic (eutectic bonding) process can supply the current from the outside, it is possible to implement a package-integrated vertical light emitting device (LED).

In addition, according to the embodiment, a light emitting device capable of minimizing the epi-layer loss area when performing wafer-to-wafer bonding between the epi-layer and the silicon substrate of the light emitting structure. It is possible to provide a method for manufacturing a package.

1 is a cross-sectional view of a light emitting device package according to a first embodiment according to the embodiment.
2 is a cross-sectional view of a light emitting device package according to a second embodiment according to the embodiment.
3 to 8 illustrate a process cross-sectional view of a light emitting device package according to the embodiment.
9 is a top perspective view of a light emitting device package according to the second embodiment;
10 is a bottom perspective view of a light emitting device package according to the second embodiment;
11 is a cross-sectional view of a light emitting device package according to the embodiment.
12 is a perspective view of a lighting unit according to an embodiment.
13 is a perspective view of a backlight unit according to an embodiment.

In the description of the embodiments, it is to be understood that each layer (film), area, pattern or structure may be referred to as being "on" or "under" the substrate, each layer Quot; on "and" under "are intended to include both" directly "or" indirectly " do. Also, the criteria for top, bottom, or bottom of each layer will be described with reference to the drawings.

In the drawings, the thickness or size of each layer is exaggerated, omitted, or schematically illustrated for convenience and clarity of description. In addition, the size of each component does not necessarily reflect the actual size.

(Example)

1 is a cross-sectional view illustrating a light emitting device package 200a according to a first embodiment according to an embodiment, and FIG. 2 is a cross-sectional view illustrating a light emitting device package 200b according to a second embodiment according to an embodiment.

The embodiment can improve the light extraction efficiency of the light emitting device, and to provide a light emitting device package, a manufacturing method and an illumination system of which a conformal coating is useful on the light emitting device chip.

To solve this problem, the light emitting device package according to the embodiment includes a package body 120b, a first conductivity type semiconductor layer 112, a second conductivity type semiconductor layer 116, and the first conductivity type semiconductor layer 112; An active layer 114 between the first conductive semiconductor layer 112 and a light emitting structure 110 provided on an upper surface of the package body 120b and a second electrode pad provided on a lower surface of the package body 120b. 152, a first electrode pad 151 provided on a bottom surface of the package body 120b while being electrically connected to the first conductive semiconductor layer 112, the package body 120b, and the light emitting structure. Passivation 130 interposed between the 110 and the first electrode pad 151 may be included.

According to the light emitting device package according to the embodiment, a manufacturing method and an illumination system thereof, a silicon having a three-dimensional (3D) structure is used as a substrate and an n-electrode and a p-electrode are formed. All of them are located at the bottom of the substrate so that they can be supplied from the outside through SMT process and eutectic bonding process without the need for wire bonding, and package integrated vertical light emitting device (LED) ) Can be implemented. The package body 120b may be a silicon substrate, but is not limited thereto.

In addition, in the embodiment, the package body may have a predetermined slope on the side at the top and bottom. The package body may employ a wet etching, for example, KOH-based wet etching to form a three-dimensional (3D) structure, the side surface of the 3D structure may have a vertically symmetrical or asymmetrical structure. .

For example, the package body 120a of the first embodiment may have an upper and lower width a of an inclined upper portion equal to an inclined lower upper and lower width b.

On the other hand, in the second embodiment, the package body 120b may have an inclined upper and lower width a 'less than an inclined lower upper and lower b' width. In addition, in the second embodiment, the package body 120b may have a predetermined inclination on the side surface only at the bottom thereof, but is not limited thereto.

According to the second embodiment, when the silicon substrate is wet-etched and manufactured in a 3D structure, the angle θ of the etch hypotenuse is controlled to about 55 ° to 57 °, and thus, as in Example 1, If the length of b is symmetrical, the length of c may be longer, resulting in loss of the epi-layer and silicon substrate of the light emitting structure when wafer to wafer bonding is performed. The epi-layer region may be widened. To solve this problem, a 'and b' are asymmetrical as in the second embodiment, and a 'is shortened to minimize the epi-layer loss region as in c'.

According to the second embodiment, a light emitting device capable of minimizing an epi-layer loss area when wafer-to-wafer bonding of an epi-layer and a silicon substrate of a light emitting structure is performed. It is possible to provide a method for manufacturing a package.

The embodiment may further include a phosphor layer 230 (see FIG. 11) coated on the upper surface of the light emitting structure 110, but is not limited thereto.

According to the embodiment, it is possible to combine the conformal coating technology with a structure that does not require wire bonding.

According to the embodiment, by forming the pad electrode under the package body, light blocking efficiency of the light emitting device can be improved by minimizing light blocking by the pad. Also, since the pad electrode is not on the light emitting device, conformal coating is performed on the light emitting device chip. This useful light emitting device package, its manufacturing method and lighting system can be provided.

In addition, according to the embodiment it is possible to accept the advantages of the conventional vertical chip in the same form as the conventional vertical light emitting device chip (chip) structure.

In addition, according to the embodiment, it is possible to configure a multi chip module by applying a silicon substrate having a specific structure based on MEMS technology.

In addition, according to the embodiment, the pad formed on the lower part of the package body can be subjected to eutectic bonding (Eutectic bonding) or SMT process, so that a chip level package and a highly integrated module can be configured, thereby making the ultra-light emitting device You can implement a package.

According to the light emitting device package according to the embodiment, a manufacturing method and an illumination system thereof, a silicon having a three-dimensional (3D) structure is used as a substrate and an n-electrode and a p-electrode are formed. All of them are located at the bottom of the substrate so that they can be supplied from the outside through SMT process and eutectic bonding process without the need for wire bonding, and package integrated vertical light emitting device (LED) ) Can be implemented.

In addition, according to the embodiment, a light emitting device capable of minimizing the epi-layer loss area when performing wafer-to-wafer bonding between the epi-layer and the silicon substrate of the light emitting structure. It is possible to provide a method for manufacturing a package.

Hereinafter, a method of manufacturing a light emitting device package according to an embodiment will be described with reference to FIGS. 3 to 8. Hereinafter, description will be given based on the second embodiment, but is not limited thereto.

First, the package body 120b is prepared as shown in FIG. 3.

In the preparing of the package body 120b, the package body 120b may be in a boundary state in units of chips. Alternatively, the package body may be in a state where boundaries are separated by a chip unit, but is not limited thereto.

For example, the first mask pattern 310 and the second mask pattern 320 are formed on the upper and lower surfaces of the package body 120b, respectively, and are used as an etch mask to establish the boundary of a chip unit or to separate the boundaries of a chip unit. The process can proceed.

The package body 120b may be a silicon substrate, but is not limited thereto. For example, the package body 120b may be any one of a conductive substrate such as silicon (Si), silicon carbide (SiC), GaAs, GaN, GaP, InP, Ge, and the like.

In an embodiment, the package body 120b may have a predetermined inclination on the side at the top and the bottom thereof. The package body may employ a wet etching, for example, KOH-based wet etching to form a three-dimensional (3D) structure, the side surface of the 3D structure may have a vertically symmetrical or asymmetrical structure. .

For example, the package body 120a of the first embodiment may have an upper and lower width a of an inclined upper portion equal to an inclined lower upper and lower width b.

On the other hand, in the second embodiment, the package body 120b may have an inclined upper and lower width a 'less than an inclined lower upper and lower b' width. In addition, in the second embodiment, the package body 120b may have a predetermined inclination on the side surface only at the bottom thereof, but is not limited thereto.

According to the second embodiment, when the silicon substrate is wet-etched and manufactured in a 3D structure, the angle θ of the etch hypotenuse is controlled to about 55 ° to 57 °, and thus, as in Example 1, If the length of b is symmetrical, the length of c may be longer, resulting in loss of the epi-layer and silicon substrate of the light emitting structure when wafer to wafer bonding is performed. The epi-layer region may be widened.

In order to solve this problem, in the second embodiment, a 'and b' are asymmetrical as shown in FIG. 2, and a 'is shortened to minimize the epi-layer loss region as shown in c'.

Accordingly, the second embodiment further includes an area exposed by the second mask pattern 320 rather than an area exposed by the first mask pattern 310 in order to realize asymmetry of the width of the upper and lower sides of the package body 120b. It may be narrowed, but is not limited thereto.

According to the second embodiment, a light emitting device capable of minimizing an epi-layer loss area when wafer-to-wafer bonding of an epi-layer and a silicon substrate of a light emitting structure is performed. It is possible to provide a method for manufacturing a package.

Next, as shown in FIG. 4, the light emitting structure 110 is formed on the first substrate 105, and the light emitting structure 110 and the package body 120b are bonded as shown in FIG. 5.

Meanwhile, FIG. 4 is a step of attaching the second conductive semiconductor layer of the light emitting structure 110 to the upper surface of the package body 120b so that the light emitting structure 110 is not separated by a chip unit. Although not shown, the light emitting structure 110 may be bonded in a state where boundaries are separated on a chip basis.

The first substrate 105 may include an insulating substrate or a conductive substrate. For example, the first substrate 105 may include sapphire (Al ₂ O ₃ ), SiC, Si, GaAs, GaN, ZnO, GaP, InP, Ge, and Ga ₂ 0 ₃ . At least one of may be used. Impurities on the surface may be removed by wet cleaning the first substrate 105.

Thereafter, the light emitting structure 110 including the first conductive semiconductor layer 112, the active layer 114, and the second conductive semiconductor layer 116 may be formed on the first substrate 105.

A buffer layer (not shown) may be formed between the first substrate 105 and the light emitting structure 110. The buffer layer (not shown) may mitigate lattice mismatch between the material of the light emitting structure 110 and the first substrate 105, and the material of the buffer layer may be a Group III-V compound semiconductor such as GaN, InN, or AlN. , InGaN, AlGaN, InAlGaN, or AlInN. An undoped semiconductor layer may be formed between the buffer layer and the light emitting structure 110, but is not limited thereto.

The first conductivity type semiconductor layer 112 may be implemented as a group III-V compound semiconductor doped with a first conductivity type dopant, and when the first conductivity type semiconductor layer 112 is an N-type semiconductor layer, The first conductivity type dopant may be an N type dopant and may include Si, Ge, Sn, Se, Te, but is not limited thereto.

A semiconductor material having the compositional formula of the first conductive semiconductor layer 112 may be _{In x Al y Ga 1 -x- y} N (0≤x≤1, 0≤y≤1, 0≤x + y≤1) It may include.

The first conductive semiconductor layer 112 may be formed of any one or more of GaN, InN, AlN, InGaN, AlGaN, InAlGaN, AlInN, AlGaAs, InGaAs, AlInGaAs, GaP, AlGaP, InGaP, AlInGaP, InP.

The first conductive semiconductor layer 112 may form an N-type GaN layer using a chemical vapor deposition method (CVD), molecular beam epitaxy (MBE), or sputtering or hydroxide vapor phase epitaxy (HVPE). . In addition, the first conductive semiconductor layer 112 may include a silane containing n-type impurities such as trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), and silicon (Si). The gas SiH ₄ may be injected and formed.

The active layer 114 has an energy band inherent in the active layer (light emitting layer) material because electrons injected through the first conductive semiconductor layer 112 and holes injected through the second conductive semiconductor layer 116 formed thereafter meet each other. It is a layer that emits light with energy determined by.

The active layer 114 may be formed of at least one of a single quantum well structure, a multi quantum well structure (MQW), a quantum-wire structure, or a quantum dot structure. For example, the active layer 114 may be formed by injecting trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), and trimethyl indium gas (TMIn) to form a multi-quantum well structure. It is not limited to this.

The well layer / barrier layer of the active layer 114 is formed of one or more pair structures of InGaN / GaN, InGaN / InGaN, GaN / AlGaN, InAlGaN / GaN, GaAs (InGaAs), / AlGaAs, GaP (InGaP) / AlGaP. It may be, but is not limited to such. The well layer may be formed of a material having a lower band gap than the band gap of the barrier layer.

A conductive cladding layer may be formed on or under the active layer 114. The conductive clad layer may be formed of an AlGaN-based semiconductor, and may have a higher band gap than the band gap of the active layer 114.

The second conductive type semiconductor layer 116 is a second conductive type dopant is doped -5-group three-V compound semiconductor, for _{example, In x Al y Ga 1 -x-} y N (0≤x≤1, 0≤y And a semiconductor material having a composition formula of ≦ 1, 0 ≦ x + y ≦ 1). When the second conductive semiconductor layer 116 is a P-type semiconductor layer, the second conductive dopant may include Mg, Zn, Ca, Sr, Ba, or the like as a P-type dopant.

The second conductivity type semiconductor layer 116 is a bicetyl cyclone containing p-type impurities such as trimethyl gallium gas (TMGa), ammonia gas (NH ₃ ), nitrogen gas (N ₂ ), and magnesium (Mg) in the chamber. Pentadienyl magnesium (EtCp ₂ Mg) {Mg (C ₂ H ₅ C ₅ H ₄ ) ₂ } may be injected to form a p-type GaN layer, but is not limited thereto.

In an exemplary embodiment, the first conductive semiconductor layer 112 may be an N-type semiconductor layer, and the second conductive semiconductor layer 116 may be a P-type semiconductor layer, but is not limited thereto. In addition, a semiconductor, for example, an N-type semiconductor layer (not shown) having a polarity opposite to that of the second conductivity type may be formed on the second conductivity type semiconductor layer 116. Accordingly, the light emitting structure 110 may be implemented as any one of an N-P junction structure, a P-N junction structure, an N-P-N junction structure, and a P-N-P junction structure.

Thereafter, the step of attaching the second conductive semiconductor layer 116 of the light emitting structure 110 to the upper surface of the package body 120b may be performed. The light emitting structure 110 and the package body 120b may be coupled to each other by eutectic bonding, but are not limited thereto. Alternatively, bonding may be performed by forming a bonding layer on the package body 120b using nickel (Ni), gold (Au), or the like.

An embodiment may form an ohmic layer (not shown), a reflective layer (not shown), etc. on the upper surface of the package body 120b in contact with the light emitting structure 110, but is not limited thereto.

For example, when the ohmic layer is formed, the ohmic layer may be formed by stacking a single metal, a metal alloy, a metal oxide, or the like in multiple layers so as to efficiently inject the carrier. For example, the ohmic layer may be indium tin oxide (ITO), indium zinc oxide (IZO), indium zinc tin oxide (IZTO), indium aluminum zinc oxide (IAZO), indium gallium zinc oxide (IGZO), or indium gallium (IGTO). tin oxide), aluminum zinc oxide (AZO), antimony tin oxide (ATO), gallium zinc oxide (GZO), IZO (IZO Nitride), AGZO (Al-Ga ZnO), IGZO (In-Ga ZnO), ZnO, IrOx , RuOx, NiO, RuOx / ITO, Ni / IrOx / Au, and Ni / IrOx / Au / ITO, Ag, Ni, Cr, Ti, Al, Rh, Pd, Ir, Ru, Mg, Zn, Pt, Au, It may be formed including at least one of Hf, but is not limited to such materials.

In addition, when a reflective layer (not shown) is formed, the reflective layer may be made of Al, Ag, or a metal layer including an alloy containing Al or Ag.

In addition, the embodiment may include a zener diode (not shown) in the package body 120b, but is not limited thereto.

Thereafter, a process of removing the substrate 105 from the light emitting structure 110 may be performed. For example, the method of removing the first substrate 105 may use a high power laser to separate the first substrate or use a chemical etching method. In addition, the first substrate 105 may be removed by physically grinding. In this case, when the laser lift-off method LLO is applied with a predetermined energy at room temperature, energy is absorbed at the interface between the first substrate 105 and the light emitting structure 110, and the bonding surface of the light emitting structure is thermally decomposed so that the first substrate is thermally decomposed. 105 and the light emitting structure 110 may be separated, but is not limited thereto.

Next, as illustrated in FIGS. 6 and 7, the package body 120b and the light emitting structure 110 may be separated in units of chips.

For example, the third mask pattern 330 may be formed on the light emitting structure 110, and the package body 120b and the light emitting structure 110 may be separated in units of chips using the etching mask as an etching mask.

Next, as shown in FIG. 8, a second electrode pad 152 is formed on the bottom surface of the package body 120b and the first electrode pad 151 electrically connected to the first conductive semiconductor layer 112 is formed. The passivation 130 is formed on the bottom surface of the package body.

A first electrode 141 is formed on the first conductive semiconductor layer 112, which is formed on the side of the light emitting structure 110 and the package body 120b to be electrically connected to the first electrode pad 151. Can be.

9 is a top perspective view of the light emitting device package according to the second embodiment, and FIG. 10 is a bottom perspective view of the light emitting device package according to the second embodiment.

According to the light emitting device package according to the embodiment, the first electrode pad 151 may be formed under the package body 120b through the first electrode 141.

9 and 10 illustrate the state in which the 3D structure is formed by etching the package body 120b into an asymmetric shape as in the second embodiment, but is not limited thereto.

According to the light emitting device package according to the embodiment, a manufacturing method and an illumination system thereof, a silicon having a three-dimensional (3D) structure is used as a substrate and an n-electrode and a p-electrode are formed. All of them are located at the bottom of the substrate so that they can be supplied from the outside through SMT process and eutectic bonding process without the need for wire bonding, and package integrated vertical light emitting device (LED) ) Can be implemented. The package body 120b may be a silicon substrate, but is not limited thereto.

In addition, in the embodiment, the package body may have a predetermined slope on the side at the top and bottom. The package body may employ a wet etching, for example, KOH-based wet etching to form a three-dimensional (3D) structure, the side surface of the 3D structure may have a vertically symmetrical or asymmetrical structure. .

In the second embodiment, the package body 120b may have an inclined upper and lower width a 'less than an inclined lower upper and lower b' width. In addition, in the second embodiment, the package body 120b may have a predetermined inclination on the side surface only at the bottom thereof, but is not limited thereto.

According to the second embodiment, a light emitting device capable of minimizing an epi-layer loss area when wafer-to-wafer bonding of an epi-layer and a silicon substrate of a light emitting structure is performed. It is possible to provide a method for manufacturing a package.

According to the embodiment, by forming the pad electrode under the package body, light blocking efficiency of the light emitting device can be improved by minimizing light blocking by the pad. Also, since the pad electrode is not on the light emitting device, conformal coating is performed on the light emitting device chip. This useful light emitting device package, its manufacturing method and lighting system can be provided.

In addition, according to the embodiment it is possible to accept the advantages of the conventional vertical chip in the same form as the conventional vertical light emitting device chip (chip) structure.

In addition, according to the embodiment, it is possible to configure a multi chip module by applying a silicon substrate having a specific structure based on MEMS technology.

In addition, according to the embodiment, the pad formed on the lower part of the package body can be subjected to eutectic bonding (Eutectic bonding) or SMT process, so that a chip level package and a highly integrated module can be configured, thereby making the ultra-light emitting device You can implement a package.

11 is a cross-sectional view of a light emitting device package 200 according to the embodiment.

In an embodiment, the phosphor layer 230 coated on the upper surface of the light emitting structure 110 may be formed. According to the embodiment, it is possible to combine the conformal coating technology with a structure that does not require wire bonding.

According to the embodiment, by forming the pad electrode under the package body, light blocking efficiency of the light emitting device can be improved by minimizing light blocking by the pad. Also, since the pad electrode is not on the light emitting device, conformal coating is performed on the light emitting device chip. This useful light emitting device package, its manufacturing method and lighting system can be provided.

In addition, according to the light emitting device package, the manufacturing method and the illumination system according to the embodiment, using a silicon (silicone) having a three-dimensional (3D) structure as a substrate, n-electrode and p-electrode (p-electrode) ) Are all located at the bottom of the substrate, so that current can be supplied externally by SMT process and eutectic bonding process without wire bonding, and package integrated vertical light emitting device (LED) can be implemented.

In addition, according to the embodiment, a light emitting device capable of minimizing the epi-layer loss area when performing wafer-to-wafer bonding between the epi-layer and the silicon substrate of the light emitting structure. It is possible to provide a method for manufacturing a package.

The light emitting device package according to the embodiment may be applied to an illumination system. The lighting system includes a lighting unit shown in FIG. 12 and a backlight unit shown in FIG. 13, and may include a traffic light, a vehicle headlight, a signboard, and the like.

12 is a perspective view 1100 of a lighting unit according to an embodiment.

Referring to FIG. 12, the lighting unit 1100 is installed in the case body 1110, the light emitting module unit 1130 installed in the case body 1110, and the case body 1110 and supplies power from an external power source. It may include a connection terminal 1120 provided.

The case body 1110 may be formed of a material having good heat dissipation characteristics. For example, the case body 1110 may be formed of a metal material or a resin material.

The light emitting module unit 1130 may include a substrate 1132 and at least one light emitting device package 200 mounted on the substrate 1132.

The substrate 1132 may be a circuit pattern printed on an insulator, and for example, a general printed circuit board (PCB), a metal core PCB, a flexible PCB, a ceramic PCB, and the like. It may include.

In addition, the substrate 1132 may be formed of a material that reflects light efficiently, or the surface may be formed of a color that reflects light efficiently, for example, white, silver, or the like.

The at least one light emitting device package 200 may be mounted on the substrate 1132. The light emitting device package 200 may include, but is not limited to, a light emitting device package 120a according to the first embodiment or a light emitting device package 120b according to the second embodiment.

Each of the light emitting device packages 200 may include at least one light emitting diode (LED). The light emitting diodes may include colored light emitting diodes emitting red, green, blue, or white colored light, and UV light emitting diodes emitting ultraviolet (UV) light.

The light emitting module unit 1130 may be disposed to have a combination of various light emitting device packages 200 to obtain color and luminance. For example, a white light emitting diode, a red light emitting diode, and a green light emitting diode may be combined to secure high color rendering (CRI).

The connection terminal 1120 may be electrically connected to the light emitting module unit 1130 to supply power. According to FIG. 12, the connection terminal 1120 is coupled to the external power source by being connected to the socket in a socket manner, but is not limited thereto. For example, the connection terminal 1120 may be formed in a pin shape and inserted into an external power source, or may be connected to the external power source by a wire.

13 is an exploded perspective view 1200 of a backlight unit according to an embodiment.

The backlight unit 1200 according to the embodiment includes a light guide plate 1210, a light emitting module unit 1240 that provides light to the light guide plate 1210, a reflective member 1220 under the light guide plate 1210, and the light guide plate. 1210, a bottom cover 1230 for accommodating the light emitting module unit 1240 and the reflective member 1220, but is not limited thereto.

The light guide plate 1210 serves to surface light by diffusing light. The light guide plate 1210 is made of a transparent material, for example, an acrylic resin series such as polymethyl metaacrylate (PMMA), polyethylene terephthlate (PET), polycarbonate (PC), cycloolefin copolymer (COC), and polyethylene naphthalate (PEN). It may include one of the resins.

The light emitting module unit 1240 provides light to at least one side of the light guide plate 1210 and ultimately serves as a light source of a display device in which the backlight unit is installed.

The light emitting module unit 1240 may be in contact with the light guide plate 1210, but is not limited thereto. Specifically, the light emitting module unit 1240 includes a substrate 1242 and a plurality of light emitting device packages 200 mounted on the substrate 1242, wherein the substrate 1242 is connected to the light guide plate 1210. It may be encountered, but is not limited thereto.

The substrate 1242 may be a printed circuit board (PCB) including a circuit pattern (not shown). However, the substrate 1242 may include not only a general PCB but also a metal core PCB (MCPCB, Metal Core PCB), a flexible PCB (FPCB, Flexible PCB), and the like, but is not limited thereto.

The plurality of light emitting device packages 200 may be mounted on the substrate 1242 such that a light emitting surface on which light is emitted is spaced apart from the light guide plate 1210 by a predetermined distance.

The reflective member 1220 may be formed under the light guide plate 1210. The reflective member 1220 may improve the luminance of the backlight unit by reflecting the light incident on the lower surface of the light guide plate 1210 upward. The reflective member 1220 may be formed of, for example, PET, PC, or PVC resin, but is not limited thereto.

The bottom cover 1230 may accommodate the light guide plate 1210, the light emitting module unit 1240, the reflective member 1220, and the like. To this end, the bottom cover 1230 may be formed in a box shape having an upper surface opened, but is not limited thereto.

The bottom cover 1230 may be formed of a metal material or a resin material, and may be manufactured using a process such as press molding or extrusion molding.

According to the light emitting device package according to the embodiment, a manufacturing method and an illumination system thereof, a silicon having a three-dimensional (3D) structure is used as a substrate and an n-electrode and a p-electrode are formed. All of them are located at the bottom of the substrate so that they can be supplied from the outside through SMT process and eutectic bonding process without the need for wire bonding, and package integrated vertical light emitting device (LED) ) Can be implemented.

In addition, according to the embodiment, a light emitting device capable of minimizing the epi-layer loss area when performing wafer-to-wafer bonding between the epi-layer and the silicon substrate of the light emitting structure. It is possible to provide a method for manufacturing a package.

In addition, according to the embodiment, by forming the pad electrode under the package body, light blocking efficiency of the light emitting device can be improved by minimizing light blocking caused by the pad, and since the pad electrode is not on the light emitting device, The formal coating can provide a useful light emitting device package, a method of manufacturing the same, and an illumination system.

The features, structures, effects and the like described in the embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, and the like illustrated in the embodiments may be combined or modified with respect to other embodiments by those skilled in the art to which the embodiments belong. Accordingly, the contents of such combinations and modifications should be construed as being included in the scope of the embodiments.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It can be seen that the modification and application of branches are possible. For example, each component specifically shown in the embodiment can be modified. It is to be understood that the present invention may be embodied in many other specific forms without departing from the spirit or essential characteristics thereof.

Claims (9)

Package body;
A light emitting structure on a top surface of the package body, the first conductive semiconductor layer, the second conductive semiconductor layer, an active layer between the first conductive semiconductor layer and the first conductive semiconductor layer;
A second electrode pad on the bottom surface of the package body while being electrically connected to the second conductive semiconductor layer;
A first electrode pad electrically connected to the first conductive semiconductor layer and extending toward a side of the package body and formed on a bottom surface of the package body; And
And a passivation interposed between the package body and the light emitting structure and the first electrode pad. The method according to claim 1,
The package body,
A light emitting device package having a predetermined slope on the upper side and the lower side. The method of claim 2,
The package body,
A light emitting device package in which the upper and lower widths of the inclined upper portion are equal to the inclined lower upper and lower widths. The method of claim 2,
The package body,
A light emitting device package in which the upper and lower widths of the inclined upper part are different from the inclined lower upper and lower widths. The method of claim 4, wherein
The package body,
A light emitting device package, wherein the upper and lower widths of the inclined upper portion are less than the inclined lower upper and lower widths. The method according to claim 1,
The package body,
A light emitting device package having a predetermined slope on the side only at the bottom. The method according to claim 1,
The light emitting device package further comprises a phosphor layer coated on the upper surface of the light emitting structure. The method according to claim 1,
A light emitting device package in which no pad electrode is formed on an upper surface of the light emitting structure. The method according to any one of claims 1 to 8,
The light emitting device package is in contact with the light emitting structure and the package body.

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