JP2004289047A - Semiconductor light emitting element and its manufacturing method - Google Patents

Semiconductor light emitting element and its manufacturing method Download PDF

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Publication number
JP2004289047A
JP2004289047A JP2003081973A JP2003081973A JP2004289047A JP 2004289047 A JP2004289047 A JP 2004289047A JP 2003081973 A JP2003081973 A JP 2003081973A JP 2003081973 A JP2003081973 A JP 2003081973A JP 2004289047 A JP2004289047 A JP 2004289047A
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light emitting
semiconductor light
substrate
emitting device
semiconductor
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Masaki Hashimura
昌樹 橋村
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Toyoda Gosei Co Ltd
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Toyoda Gosei Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To improve productivity of a semiconductor light emitting element and to improve external quantum efficiency of the semiconductor light emitting element. <P>SOLUTION: When a laser beam is used, a tilting surface 1a of a substrate 1 can be formed readily. Especially, when the tilting surface 1a is made 100 μm or more high, a semiconductor wafer 800 can be divided at a desired position even while keeping the substrate about 200 to 300 μm thick. According to such a constitution, the tilting surface 1a can be ensured wider and at the same time, the wafer 800 can be divided into each light emitting element 100 at a desired position more readily and accurately or surely than by a conventional one. That is, higher external quantum efficiency and higher productivity can be acquired at once than by a conventional method. Furthermore, the substrate 1 can be formed to a convex lens shape by chamfering at least a part of ridges L1, L2 by blast treatment or the like. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【０００１】
【発明の属する技術分野】
本発明は、基板の上面（表側の水平面）上に結晶成長により複数の半導体層を積層して形成される半導体発光素子とその製造方法に関する。
【０００２】
【従来の技術】
【特許文献１】
特開平７−１３１０６９号公報
【特許文献２】
特開平１１−１６３４０３号公報
【０００３】
上記の特許文献１や特許文献２などから判る様に、通常上記の結晶成長基板は、３００μｍ〜８００μｍ程度の厚さを有しており、これらの基板は研磨処理を経て通常は５０μｍ〜１５０μｍ程度の厚さまで薄くしてから、個々のチップ（発光素子）単位に分割される。この様な薄板化のための研磨処理は、必要となる各種の半導体層の結晶成長工程の前に行っても良いし、後に行っても良い。
ただし、基板を薄くし過ぎると、基板自身が割れ易くなり、更に研磨処理工程に費やす時間も長くなるため望ましくない。また、基板が厚過ぎると、半導体ウエハの分割時に所望の形状に正確或いは確実に分割することが難しくなるため望ましくない。
【０００４】
以上の理由から、通常上記の研磨処理は、半導体ウエハを個々のチップ単位に分割する分割工程よりも前の段階に、基板が約１００μｍ程度の厚さになるまで実施される。また、例えば３００μｍの厚さを有するサファイア基板を１００μｍ程度の厚さまで研磨する際には、通常５時間〜６時間程度の時間を要するのが現状である。
【０００５】
【発明が解決しようとする課題】
しかしながら、半導体発光素子の製造に当り高い生産性を確保するためには、例えば上記の様な研磨処理工程などに数時間もの長い時間を費やすことは、決して望ましいことではない。即ち、上記の様な研磨処理工程などは、半導体発光素子の生産性向上を阻害する一つの限定要因となっている。
【０００６】
また、特にＬＥＤなどの半導体発光素子の構造においては、発光層から基板内に入射された後にその基板内を通過して再び基板の何れか１つの界面（表面：ひょう面）に到達した光は、極力その到達点（即ち、その界面）から外部に取り出すことが外部量子効率の観点から望ましいと考えられる。
【０００７】
しかしながら、従来の半導体発光素子の場合、基板の側壁が結晶成長面に対して略垂直に切り立っている場合が多く、それらの界面では光は再び基板内に反射され易いため、その到達点（即ち、その界面）から即座にそれらの光を外部に取り出す効率は非常に低かった。このため、従来の半導体発光素子では、少なくともこれらの観点において、外部量子効率が十分には得られていなかった。
【０００８】
本発明は、上記の課題を解決するために成されたものであり、その目的は、半導体発光素子の生産性を向上させることである。
また、本発明のその他の目的は、半導体発光素子の外部量子効率を向上させることである。
ただし、上記の個々の目的は、本発明の個々の手段の内の少なくとも何れか１つによって、個々に達成されれば十分なのであって、本願の個々の発明は、上記の全ての課題を同時に解決し得る手段が存在することを必ずしも保証するものではない。
【０００９】
【課題を解決するための手段、並びに、作用及び発明の効果】
上記の課題を解決するためには、以下の手段が有効である。
即ち、本発明の第１の手段は、基板の上面（表側の水平面）上に結晶成長により複数の半導体層を積層して形成される半導体発光素子において、基板の側壁に、基板の裏側に斜めに露出し、かつ基板の裏面にまで連なる少なくとも高さ５０μｍ以上の傾斜面を設けることである。
【００１０】
この様な構成に従えば、鉛直方向から測った傾斜面の傾斜角θ（０°＜θ＜９０°）がある程度の大きさを持つ時、結晶成長面から基板内に入射した光が上記の傾斜面に到達した際には、その光は従来よりも高い確率で基板の外側へ透過される。また、上記の構成に従えば、基板の側壁の少なくとも一部において、広い傾斜面が確保されるため、基板の側方からの光の取り出し効率が従来よりも大きく向上する。したがって、これらの作用により、発光素子の外部量子効率を従来よりも高くすることができる。
【００１１】
また、半導体ウエハを各発光素子単位に分割する前に、この様な傾斜面を各発光素子毎に形成しておけば、必ずしも上記の研磨処理工程を導入しなくても、その半導体ウエハを容易に分割することができるため、このような構成は半導体発光素子の生産性の向上にも寄与し得る。
【００１２】
ただし、半導体ウエハを分割する際に、容易、正確、又は確実に所望の位置で個々の発光素子に分割するためには、或いは、基板の側方からの光の取り出し効率（外部量子効率）を十分に確保するためには、以下の構成に従うことがより望ましい。
【００１３】
即ち、本発明の第２の手段は、上記の第１の手段において、上記の傾斜面の高さを１００μｍ以上にすることである。
この様な構成に従えば、上記の傾斜面をより広く確保できると同時に、従来よりも更に容易、正確、又は確実に所望の位置で個々の発光素子にウエハを分割することが可能となる。したがって、従来よりも高い外部量子効率と従来よりも高い生産性を同時に獲得することができる。
【００１４】
尚、高さ５０μｍ以上の大きな傾斜面を形成する効率的な手段としては、例えば、基板裏面へのレーザービーム照射によるエッチング処理などが非常に有用である。これらの製造方法に付いては、後から詳しく言及する。
【００１５】
レーザービームを用いた場合、容易に上記の傾斜面を形成することができるが、特にこの傾斜面の高さを１００μｍ以上とした場合、基板の厚さを凡そ２００μｍ〜３００μｍ程度にまで厚くしたままでも、半導体ウエハを所望位置で分割することが可能である。したがって、この様な構成によれば、従来よりも遥かに基板の厚さを厚く確保することができる。
【００１６】
この様な構成下においては、基板の裏面を必ずしも研磨処理しなくとも良く、また、基板の厚さが厚く確保されている場合程、上記の傾斜面から発光素子の側方に光を多量に取り出すことができる。したがって、この様な作用によっても、本発明の半導体発光素子では、従来よりも外部量子効率を更に高くすることができる。
【００１７】
また、第３の手段は、上記の第１又は第２の手段において、鉛直方向から測った傾斜面の傾斜角θを１０°以上４５°以下にすることである。
この範囲に上記の傾斜角θを納めておけば、半導体ウエハを個々の発光素子に分割する際に、所望の部位でより容易、正確、又は確実に分割処理を実行することができる。
【００１８】
この範囲よりも傾斜角θを小さくすると、発光素子の側方からの光の取り出し効率（外部量子効率）を高く確保することが徐々に難しくなる。また、この範囲よりも傾斜角θを大きくすると、所望の部位でより容易、正確、又は確実に分割処理を実行することが徐々に難しくなる。
また、基板による光の屈折や集光作用、或いはハンドリングや後工程（エッチング）等を考慮しても、実用上、上記の範囲内に傾斜角θを確保することが望ましい。
【００１９】
更に、レーザービームの照射により、傾斜面を形成する場合にも、傾斜角θがこの範囲内に有れば、現行の加工技術水準に照らして比較的容易に半導体ウエハの裏面に、各発光素子単位に傾斜面を形成することができる。
ただし、より望ましくは、傾斜面の傾斜角θは、１５°以上３０°以下が良い。この範囲であれば、分割処理部の品質（歩留り）や傾斜面の光取り出し効果（性能）やレーザービームの照射時のスキャン回数（生産性）や、或いはチップのハンドリングや後工程（エッチング）等の各面で有利な発光素子を製造することが容易となる。
【００２０】
第４の手段は、上記の第１乃至第３の何れか１つの手段によって製造されるフリップチップ型のＬＥＤおいて、基板の裏面と傾斜面とが成す稜の少なくとも一部を面取りすることである。
【００２１】
図１は、本発明に係わる半導体発光素子１００を複数有する半導体ウエハ８００の模式的な断面図である。基板１の裏面１ｂと各傾斜面１ａとが成す２本の稜Ｌ１，Ｌ２は、図面のｙ軸方向に伸びている。図面中央の半導体発光素子１００が持つ稜Ｌ１は面取りされていないが、稜Ｌ２は面取りされている。
尚、符号２ａはｎ型半導体層を示しており、符号２ｂはｐ型半導体層を、符号ｈは傾斜面１ａの高さ（略Ｖ字形状の分割溝の深さ）を、符号ｔは半導体ウエハ８００の厚さを、また、符号θは傾斜面１ａの鉛直方向から測った傾斜角をそれぞれ示している。ただし、ｎ型半導体層２ａは、複数の半導体層から成る多層構造を有していてもても良い。ｐ型半導体層２ｂに付いても同様である。これらの多層構造に付いては、それぞれ公知、或いは任意の多層構造を採用することができる。
【００２２】
例えばこの様な基板の裏面と傾斜面とが成す稜（Ｌ１，Ｌ２）の少なくとも一部を面取りすることにより、基板１を凸レンズ形状に形成することができるため、半導体発光素子１００から出力される光の向きを所望の範囲に絞り込むことが可能となる。
【００２３】
第５の手段は、上記の第４の手段において、上記の稜に対して垂直な断面における、その稜が面取りされた部分の曲率半径を１０μｍ以上５００μｍ以下にすることである。
【００２４】
この曲率半径は、図１の符号Ｒが示す長さに相当するものであるが、この長さＲ（曲率半径Ｒ）を１０μｍ以上５００μｍ以下にすることで、実用性の高い集光作用を有する凸レンズ形状を形成することができる。
この曲率半径Ｒは、一つの半導体発光素子において、必ずしも１つの一定値に保つ必要はなく、基板上で局所的に任意の値を採ることができる。
また、この曲率半径Ｒの最適値又は好適値は、半導体発光素子の厚さｔや傾斜面の高さｈや傾斜面の傾斜角θや発光層の面積や発光素子の発光波長や、或いは発光素子の具体的な用途等に応じて適当な値を選択すれば良い。
即ち、このような手段によっても、外部量子効率や出力方向に関する出力特性等を改善することができる。
【００２５】
第６の手段は、上記の第１乃至第３の何れか１つの手段によって製造されるワイヤーボンディング型のＬＥＤにおいて、略グラス形状、略深皿形状、又は略パラボラ形状の反射面を有するリードフレームの内側底部に、略透明の接着剤を用いて上記の基板の裏面を接着することである。
【００２６】
このような構成に従えば、上記の接着剤の透光作用と上記の反射面の反射作用により、ワイヤーボンディング型のＬＥＤにおいて、上記の傾斜面から出力された光をも効率よく光取り出し方向に出力することができる。
また、上記の接着剤が上記の傾斜面に覆い被さる場合には、鉛直方向から測った傾斜面の傾斜角θは、勿論、その接着剤の屈折率などの各種の諸条件を十分に考慮して、外部量子効率が十分に高まる様に好適或いは最適な値に調整・設定することが望ましい。
【００２７】
以下、上記の本発明の半導体発光素子に係わる製造工程に関する、重要、或いはより望ましい製造方法に付いて説明する。
【００２８】
即ち、第７の手段は、上記の第１乃至第６の何れか１つの手段によって製造される半導体発光素子の製造工程において、半導体発光素子を複数有する半導体ウエハの裏面にレーザービームを照射することにより、上記の二面の傾斜面から成り断面形状が略Ｖ字型で深さが５０μｍ以上の分割溝を形成するレーザー照射工程と、上記の分割溝を用いて半導体ウエハを半導体発光素子単位に分割するウエハ分割工程とを設けることである。
ただし、上記の溝の深さは、勿論、１００μｍ以上であれば更に良い。
【００２９】
この様な方法により、上記の分割溝の深さや大きさや形状を所望の仕様に容易に形成することが可能となる。また、基板の裏面の研磨処理工程が省略可能となるため、製造時間を従来よりも大幅に短縮できる。
更に、この様な工法で半導体発光素子を製造すれば、基板側壁の傾斜面が上記の分割溝と同時に形成できるので、加工の工数や更には各半導体発光素子間（各チップ間）の分割部の幅（切り代ろ）等をも合理的に節約することができるので、同一面積の１枚の半導体ウエハ上に従来よりも多数のチップ（発光素子）を従来よりも短時間で形成でき、よって生産性の面等でも非常に都合が良い。
或いは、同一面積の１枚の半導体ウエハ上に従来と同数のチップ（発光素子）を形成する場合でも、従来は確保できなかった基板側壁の傾斜面を容易に形成することができる様になり好都合である。
即ち、この様な工法は、上記の本発明の半導体発光素子の製造に非常に適している。
【００３０】
第８の手段は、上記の第７の手段において、上記の分割溝の略Ｖ字型の内角を２０°以上９０°以下にすることである。
この様な略Ｖ字型の分割溝を形成すれば、前述の傾斜面の傾斜角θを同時に最適或いは好適な値に形成することができる。
【００３１】
第９の手段は、上記の第７又は第８の手段のレーザー照射工程とウエハ分割工程との間に、半導体ウエハの裏面をブラスト処理、エッチング処理、又は研磨処理することにより、レーザービームの照射に伴って発生した飛散物を除去する飛散物除去工程を設けることである。
【００３２】
この様な飛散物除去工程を設ければ、レーザービームの照射によって溶融した基板の溶融物等が飛散して、基板の裏面や側壁（傾斜部）等に付着しても、半導体ウエハの裏面には結晶成長された半導体結晶層がないため、十分強力に半導体ウエハの裏面をブラスト処理、エッチング処理、又は研磨処理することができ、これにより、光を吸収し易い上記の飛散物（溶融物）を容易かつ確実に基板の界面（裏面や側壁）から取り去ることができる。したがって、この様な方法によれば、効果的に外部量子効率を向上させることができる。
【００３３】
第１０の手段は、上記の第９の手段の飛散物除去工程とウエハ分割工程との間に、或いは、上記の第９の手段の飛散物除去工程の代りに、半導体ウエハの裏面をブラスト処理、エッチング処理、又は研磨処理することにより、レーザービームの照射に伴って発生した熱影響層を除去する熱影響層除去工程を設けることである。
【００３４】
ただし、上記の熱影響層とは、レーザービームの照射に伴って発生した熱の影響を強く受けている基板の一部の層を指す。この様な熱影響層は、基板の歪み（応力）、透光性、或いは屈折率等に悪影響を与えることが多いため、除去しておくことが望ましいが、上記の第１１の手段によれば、上記の飛散物（溶融物）と同様に、これらの熱影響層をも除去することができる。即ち、この様な方法によっても、半導体発光素子の外部量子効率を向上させることができる。
【００３５】
第１１の手段は、上記の第９または第１０の手段において、上記の分割溝の開口幅を２５μｍ以上にすることである。この分割溝の開口幅は、より望ましくは５０μｍ以上にすると良い。この様な構成に従えば、上記の傾斜面をブラスト処理、或いはエッチング処理する際に、それらの処理の作用が効果的に傾斜面全面に及ぶため、効率良く、容易或いは確実にそれらの処理を実施することができる。
【００３６】
より具体的には、例えばブラスト処理の場合、直径約５μｍ前後の粒子を用いることが多いが、上記の分割溝の開口幅を２５μｍ以上（より望ましくは５０μｍ以上）にすることにより、半導体ウエハを分割する前の段階で、それらの粒子を上記の傾斜面の略全面にぶつけることができる。
【００３７】
第１２の手段は、上記の第７乃至第１１の何れか１つの手段において、基板を挟んで上記の分割溝の反対側に位置する半導体ウエハの分割許容領域を少なくともｎ型半導体層が露出するまで半導体ウエハの上面よりエッチングする分割許容領域エッチング工程を設けることである。勿論、上記の分割許容領域は半導体ウエハの上面より基板が露出したり削れたりするまでエッチングしても良い。
【００３８】
例えば前述の図１の半導体ウエハ８００では、２つの傾斜面１ａから構成される分割溝Ｓの反対側に位置する分割許容領域１ｃは、基板１の一部が幾らか削れるまで基板１をエッチング処理することにより形成されている。
上記の分割許容領域エッチング工程を設けることにより、半導体ウエハを所望の位置でより容易、正確、或いは確実に分割することができる。
【００３９】
第１３の手段は、上記の第１２の手段において、分割許容領域エッチング工程の後に、分割許容領域をスクライブ又はダイシングする工程を設けることである。
この様な工程を設けることにより、半導体ウエハを所望の位置で、更に容易、正確、或いは確実に分割することができる。
以上の本発明の手段により、前記の課題を効果的、或いは合理的に解決することができる。
【００４０】
【発明の実施の形態】
以下、本発明を具体的な実施例に基づいて説明する。ただし、本発明は以下に示す実施例に限定されるものではない。
〔第１実施例〕
図２に、本第１実施例におけるレーザー照射工程前の半導体ウエハ８００の模式的な断面図を例示する。サファイアから成る基板１の上面（結晶成長面）には、ｎ型半導体層２ａやｐ型半導体層２ｂ等が結晶成長処理によりそれぞれ順次積層されている。
【００４１】
ｐ型半導体層２ｂの上面から基板の裏面１ｂまでの厚さｔは約３５０μｍであり、ｎ型半導体層２ａには負電極６が、ｐ型半導体層２ｂには正電極７が、それぞれ蒸着されている。
この半導体ウエハ８００に設けられている分割許容領域１ｃは、上方からドライエッチングすることにより基板１の上面（結晶成長面）よりも下の部分が露出されて形成されたものである。
【００４２】
図３は、本第１実施例におけるレーザー照射工程での半導体ウエハ８００の模式的な断面図である。傾斜面１ａは、半導体ウエハ８００に略Ｖ字型の断面形状を持つ分割溝Ｓを形成することにより設けられる。
図４に、図３の基板１の傾斜面１ａの典型的形状を例示する断面写真（ｂ）と、その加工方法を具体的に例示する説明図（ａ）を示す。断面写真（ｂ）に例示する断面形状は、例えば、説明図（ａ）に例示する様にレーザービームの照射位置や焦点の深さなどを少しずつ変えて、同一方向（図１のｙ軸方向）に１０回程度ビーム端をスキャンさせることにより、形成することができる。
【００４３】
このレーザー照射工程では、例えばＹＡＧレーザーの第３次高調波（波長３５５ｎｍ）を用い、ビーム径５μｍ〜１０μｍ程度のレーザービームを照射して、基板１の裏面１ｂから、深さ約５０μｍ〜２５０μｍ程度深い連続線状の分離溝Ｓを形成する。
【００４４】
図５は、本第１実施例における熱影響層除去工程での半導体ウエハ８００の模式的な断面図である。本工程では、レーザー加工に伴う図略の熱影響層をブラスト処理により除去する。この時、基板１の裏面１ｂや傾斜面１ａに付着した飛散物や溶融物をも同時に除去することができる。本図５中の裏面１ｂに向う多数の矢印は、ブラスト処理に用いられる粒子の投入方向を表している。
【００４５】
上記の熱影響層は、基板の歪み（応力）、透光性、或いは屈折率等に悪影響を与えることが多いため、除去しておくことが望ましく、この様な方法によっても、半導体発光素子の外部量子効率を向上させることができる。
【００４６】
また、上記の分割溝の開口幅を２５μｍ以上にすると良い。この分割溝の開口幅は、より望ましくは５０μｍ以上にすると良い。この様な構成に従えば、上記の傾斜面１ａをブラスト処理する際に、それらの処理の作用が効果的に傾斜面全面に及ぶため、効率良く、容易或いは確実に傾斜面１ａ等を処理することができる。例えば、直径約４μｍ前後の粒子を用いる場合、上記の分割溝Ｓの開口幅を５０μｍ〜６０μｍ程度にすることにより、それらの粒子を上記の傾斜面１ａの略全面に効率よくぶつけることができる。
【００４７】
図６は、本第１実施例におけるスクライブ工程での半導体ウエハ８００の模式的な断面図である。略Ｖ字型の分割溝Ｓを構成する傾斜面１ａの高さ（即ち、分割溝Ｓの深さ）ｈが十分に高い（深い）場合や、分割許容領域１ｃの幅（図６の左右方向）が十分に広い場合や、或いは傾斜面１ａの傾斜角θが十分に小さい場合などを除き、通常、分割許容領域１ｃにはスクライブライン１ｅを設けることが望ましい。このスクライブライン１ｅの設定により、半導体ウエハ８００を所望の位置で容易、正確、或いは確実に分割することができる。
【００４８】
図７は、以上の工程にしたがって、形成され分割された本第１実施例における半導体発光素子１０１の模式的な断面図である。ただし、電極（６，７）などの図示は省略した。符号１ｄは隣の素子との分離面（即ち、半導体発光素子１０１の側壁）を表している。
【００４９】
この半導体発光素子１０１は、フリップチップ型の搭載方式を前提とするものであり、図１の半導体発光素子１００よりも傾斜角θや高さｈや曲率半径Ｒをより大きく取り、その他の部分を略同等の大きさに確保することにより形成したものである。図１の傾斜面１ａと裏面１ｂとが成す稜（Ｌ１，Ｌ２）を面取りする際のその面取り部分の曲率半径Ｒは、本図７の半導体発光素子１０１においては、傾斜面１ａの高さｈの凡そ半分程度に大きく確保されている。
【００５０】
例えば、上記の様に半導体発光素子１０１の基板１の形状を凸レンズ状にすることにより、ＬＥＤの光出力方向を所望の範囲に絞り込むことができる。
また、側壁に広い傾斜面１ａを備え、傾斜角θや曲率半径Ｒを適度に確保することにより、従来よりも外部量子効率を向上させることができる。
例えば、傾斜角θはレーザー照射工程において、光学的に調整しても良いし、上記の様に機械的に調整しても良い。また、上記の曲率半径Ｒはブラスト処理に用いる粒子の粒の大きさや処理時間、或いは粒子の投入速度などに依って調整することが可能である。
【００５１】
図８は、上記の第１実施例に対する一つの変形例を例示する半導体ウエハ８０１の模式的な断面図である。本半導体ウエハ８０１の本図中略中央におけるスクライブライン１ｅ′は、負電極６が蒸着されるｎ型半導体層２ａの露出面１ｃ′と同一の面上にスクライブ加工を施すことにより形成されている。
【００５２】
この様な構成に従えば、スクライブ加工の対象とすべき加工対象面を露出させるための専用のエッチング工程が不要となり、その様なエッチング工程と、負電極６を蒸着すべき蒸着対象面を露出させるためのエッチング工程とを区別することなく、同一処理により同時に実施することが可能となる。
前記の第１実施例は、例えばこの様な変形的な実施形態で実施しても良い。特にこの様な手順に従えば、半導体発光素子の製造時間を短くしたり、或いは製造工程をより簡潔に構成したりすることも可能である。
【００５３】
〔第２実施例〕
図９は、本第２実施例における半導体発光素子１０２の模式的な断面図である。本図９に示す様に、この半導体発光素子１０２は、ワイヤーボンディング型の搭載様式に従うものであり、第１実施例で例示した製造工程と略同等の製造工程に従って製造されたものである。
符号６はｎ型半導体層２ａに設けられた負電極を、符号７はｐ型半導体層２ｂに設けられた正電極をそれぞれ指している。
【００５４】
リードフレーム３には、略パラボラ形状の反射面３ａが設けられており、その表面は略鏡面状に形成されている。半導体発光素子１０２の基板１は透光性接着剤４により、反射面３ａの内側底部中央に接着されている。この透光性接着剤４は外部量子効率を向上させる意味で、極力透明な材料を選択することが望ましい。しかしながら、半導体発光素子１０２の基板１は本発明の構成に基づいて十分に厚く確保することができるので、その限りにおいては例え導電性を有する接着剤を用いてもｐｎ接合部などに短絡が発生する恐れは無く、よってこの様な場合には、この透光性接着剤４としては必ずしも絶縁性を有する材料を選択する必要はない。
【００５５】
半導体発光素子１０２の傾斜面１ａの傾斜角θは、透光性接着剤４の屈折率の大小などに合わせて、好適或いは最適に設定することが望ましい。或いは、傾斜面１ａの傾斜角θの値を先に決めて、透光性接着剤４の材料を屈折率などの諸条件を考慮して選択する様に、材料の方を調整しても良い。
【００５６】
上記の半導体発光素子１０２では、前述の本発明の作用により、傾斜面１ａを有する基板１の側壁からの光取り出し効果効率は、従来よりも高くなっているので、この様なワイヤーボンディング型のＬＥＤ（半導体発光素子）の搭載様式においても、従来よりも高い外部量子効率を確保することができる。
【図面の簡単な説明】
【図１】本発明に係わる半導体発光素子１００を複数有する半導体ウエハ８００の断面形状を例示する模式的な説明図。
【図２】本発明の第１実施例におけるレーザー照射工程前の半導体ウエハ８００の模式的な断面図。
【図３】本発明の第１実施例におけるレーザー照射工程での半導体ウエハ８００の模式的な断面図。
【図４】図３の基板１の傾斜面１ａの典型的形状を例示する断面写真（ｂ）と、その加工方法を具体的に例示する説明図（ａ）。
【図５】本発明の第１実施例における熱影響層除去工程での半導体ウエハ８００の模式的な断面図。
【図６】本発明の第１実施例におけるスクライブ工程での半導体ウエハ８００の模式的な断面図。
【図７】本発明の第１実施例における半導体発光素子１０１の模式的な断面図。
【図８】本発明の第１実施例に対する変形例を例示する半導体ウエハ８０１の模式的な断面図。
【図９】本発明の第２実施例における半導体発光素子１０２の模式的な断面図。
【符号の説明】
８００ … 半導体ウエハ
１００ … 半導体発光素子
１０１ … 半導体発光素子（第１実施例：フリップチップ型）
１０２ … 半導体発光素子（第２実施例：ワイヤーボンディング型）
１ … 基板
１ａ… 傾斜面
１ｂ… 基板の裏面
１ｃ… 半導体ウエハの分割許容領域
１ｄ… 半導体ウエハ８００の分離面（半導体発光素子１０１の側壁）
２ａ… ｎ型半導体層
２ｂ… ｐ型半導体層
３ … リードフレーム
４ … 透光性接着剤
６ … 負電極
７ … 正電極
ｈ … 傾斜面１ａの高さ（略Ｖ字形状の分割溝の深さ）
ｔ … 半導体ウエハ８００の厚さ
θ … 傾斜面１ａの鉛直方向から測った傾斜角
Ｌｉ… 基板の裏面１ｂと傾斜面１ａとが成す稜（ｉ＝１，２）
Ｒ … 稜Ｌｉの面取り時の面取り部の曲率半径[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor light emitting device formed by stacking a plurality of semiconductor layers by crystal growth on an upper surface (front horizontal surface) of a substrate and a method of manufacturing the same.
[0002]
[Prior art]
[Patent Document 1]
Japanese Patent Application Laid-Open No. Hei 7-131069 [Patent Document 2]
JP-A-11-163403
As can be seen from the above-mentioned Patent Documents 1 and 2, the above-mentioned crystal growth substrate usually has a thickness of about 300 μm to 800 μm, and these substrates are usually about 50 μm to 150 μm after polishing. And then divided into individual chips (light emitting elements). Such a polishing treatment for thinning may be performed before or after a necessary crystal growth step of various semiconductor layers.
However, if the substrate is too thin, the substrate itself is liable to crack, and the time spent in the polishing process is undesirably long. On the other hand, if the substrate is too thick, it is difficult to accurately or reliably divide the semiconductor wafer into a desired shape when dividing the semiconductor wafer.
[0004]
For the above reasons, the above polishing process is usually performed before the dividing step of dividing the semiconductor wafer into individual chip units until the substrate has a thickness of about 100 μm. Further, for example, when polishing a sapphire substrate having a thickness of 300 μm to a thickness of about 100 μm, it usually takes about 5 to 6 hours.
[0005]
[Problems to be solved by the invention]
However, in order to secure high productivity in manufacturing a semiconductor light emitting device, it is not desirable to spend a long time as long as several hours in, for example, the above polishing process. That is, the above-described polishing process is one of the limiting factors that hinders an improvement in the productivity of the semiconductor light emitting device.
[0006]
In particular, in the structure of a semiconductor light-emitting element such as an LED, light that has entered the substrate from the light-emitting layer, passed through the substrate, and has reached any one interface (surface: hail surface) of the substrate again It is considered that it is desirable to take out as much as possible from its arrival point (that is, its interface) from the viewpoint of external quantum efficiency.
[0007]
However, in the case of a conventional semiconductor light emitting device, the side wall of the substrate often stands up substantially perpendicular to the crystal growth surface, and light is easily reflected back into the substrate at the interface between them, so that the light reaches its arrival point (ie, , Its interface), and the efficiency of extracting the light to the outside was very low. For this reason, in the conventional semiconductor light emitting device, sufficient external quantum efficiency has not been obtained at least from these viewpoints.
[0008]
The present invention has been made to solve the above problems, and an object of the present invention is to improve the productivity of a semiconductor light emitting device.
Another object of the present invention is to improve the external quantum efficiency of a semiconductor light emitting device.
However, it is sufficient if each of the above-mentioned objects is achieved individually by at least one of the individual means of the present invention, and the individual invention of the present application solves all the above-mentioned problems simultaneously. It does not necessarily guarantee that a solution exists.
[0009]
Means for Solving the Problems, Functions and Effects of the Invention
In order to solve the above-mentioned problems, the following means are effective.
That is, the first means of the present invention is a semiconductor light emitting device formed by stacking a plurality of semiconductor layers by crystal growth on the upper surface (horizontal surface on the front side) of a substrate. And an inclined surface having a height of at least 50 μm and extending to the back surface of the substrate.
[0010]
According to such a configuration, when the inclination angle θ (0 ° <θ <90 °) of the inclined surface measured from the vertical direction has a certain magnitude, the light incident on the substrate from the crystal growth surface becomes the above-described light. When the light reaches the inclined surface, the light is transmitted to the outside of the substrate with a higher probability than before. Further, according to the above configuration, a wide inclined surface is ensured in at least a part of the side wall of the substrate, so that the efficiency of extracting light from the side of the substrate is greatly improved as compared with the related art. Therefore, by these actions, the external quantum efficiency of the light emitting element can be made higher than before.
[0011]
In addition, if such an inclined surface is formed for each light emitting element before dividing the semiconductor wafer into each light emitting element unit, the semiconductor wafer can be easily manufactured without necessarily introducing the above-mentioned polishing step. Such a configuration can also contribute to an improvement in the productivity of the semiconductor light emitting device.
[0012]
However, in order to easily, accurately, or surely divide a semiconductor wafer into individual light emitting elements at a desired position when dividing the semiconductor wafer, or take out light from the side of the substrate (external quantum efficiency). In order to secure a sufficient level, it is more preferable to follow the following configuration.
[0013]
That is, a second means of the present invention is that the height of the inclined surface is 100 μm or more in the first means.
According to such a configuration, the above-described inclined surface can be secured more widely, and at the same time, it is possible to divide the wafer into individual light emitting elements at desired positions more easily, accurately, or surely than before. Therefore, it is possible to simultaneously obtain a higher external quantum efficiency than before and a higher productivity than before.
[0014]
As an efficient means for forming a large inclined surface having a height of 50 μm or more, for example, an etching process by irradiating a laser beam to the back surface of the substrate is very useful. These manufacturing methods will be described later in detail.
[0015]
When a laser beam is used, the above-described inclined surface can be easily formed. In particular, when the height of the inclined surface is set to 100 μm or more, the thickness of the substrate is kept increased to about 200 μm to 300 μm. However, it is possible to divide the semiconductor wafer at a desired position. Therefore, according to such a configuration, the thickness of the substrate can be secured much larger than in the related art.
[0016]
Under such a configuration, the back surface of the substrate does not necessarily need to be polished, and the larger the thickness of the substrate is, the more light is emitted from the inclined surface to the side of the light emitting element. Can be taken out. Therefore, even with such an effect, the semiconductor light emitting device of the present invention can further increase the external quantum efficiency as compared with the related art.
[0017]
A third means is that, in the first or second means, the inclination angle θ of the inclined surface measured from the vertical direction is set to 10 ° or more and 45 ° or less.
If the above-mentioned inclination angle θ is set within this range, when dividing the semiconductor wafer into individual light emitting elements, it is possible to more easily, accurately, or surely execute the division processing at a desired portion.
[0018]
If the inclination angle θ is smaller than this range, it becomes gradually difficult to ensure high light extraction efficiency (external quantum efficiency) from the side of the light emitting element. If the inclination angle θ is larger than this range, it becomes gradually difficult to easily, accurately, or surely execute the division processing at a desired portion.
In addition, in consideration of the refraction and light condensing action of the substrate, or handling and post-processing (etching), it is practically desirable to secure the inclination angle θ within the above range.
[0019]
Furthermore, even when an inclined surface is formed by irradiating a laser beam, if the inclination angle θ is within this range, each light emitting element can be relatively easily disposed on the back surface of the semiconductor wafer in light of the current processing technology level. An inclined surface can be formed in the unit.
However, more desirably, the inclination angle θ of the inclined surface is preferably 15 ° or more and 30 ° or less. Within this range, the quality (yield) of the division processing unit, the light extraction effect (performance) of the inclined surface, the number of scans during laser beam irradiation (productivity), chip handling and post-processing (etching), etc. It is easy to manufacture an advantageous light emitting element in each aspect.
[0020]
The fourth means is that, in the flip-chip type LED manufactured by any one of the first to third means, at least a part of a ridge formed by the back surface of the substrate and the inclined surface is chamfered. is there.
[0021]
FIG. 1 is a schematic sectional view of a semiconductor wafer 800 having a plurality of semiconductor light emitting devices 100 according to the present invention. Two ridges L1 and L2 formed by the back surface 1b of the substrate 1 and each inclined surface 1a extend in the y-axis direction in the drawing. The edge L1 of the semiconductor light emitting device 100 at the center of the drawing is not chamfered, but the edge L2 is chamfered.
Reference numeral 2a denotes an n-type semiconductor layer, reference numeral 2b denotes a p-type semiconductor layer, reference numeral h denotes a height of the inclined surface 1a (depth of a substantially V-shaped division groove), and reference numeral t denotes a semiconductor. The thickness of the wafer 800 and the symbol θ indicate the inclination angle of the inclined surface 1a measured from the vertical direction. However, the n-type semiconductor layer 2a may have a multilayer structure including a plurality of semiconductor layers. The same applies to the p-type semiconductor layer 2b. Known or arbitrary multilayer structures can be adopted for these multilayer structures.
[0022]
For example, the substrate 1 can be formed in a convex lens shape by chamfering at least a part of the ridge (L1, L2) formed by the back surface and the inclined surface of such a substrate, so that the semiconductor light emitting element 100 outputs. It is possible to narrow the direction of light to a desired range.
[0023]
A fifth means is that, in the fourth means, a radius of curvature of a portion of the cross section perpendicular to the ridge where the ridge is chamfered is set to 10 μm or more and 500 μm or less.
[0024]
This radius of curvature corresponds to the length indicated by the symbol R in FIG. 1. By setting the length R (radius of curvature R) to 10 μm or more and 500 μm or less, a highly practical light-condensing action is obtained. A convex lens shape can be formed.
This radius of curvature R does not necessarily need to be kept at one constant value in one semiconductor light emitting element, and can take an arbitrary value locally on the substrate.
The optimum value or preferable value of the radius of curvature R is determined by the thickness t of the semiconductor light emitting element, the height h of the inclined surface, the inclination angle θ of the inclined surface, the area of the light emitting layer, the emission wavelength of the light emitting element, or light emission. An appropriate value may be selected according to the specific use of the element.
That is, even with such means, the external quantum efficiency and the output characteristics related to the output direction can be improved.
[0025]
A sixth means is a lead frame having a substantially glass-shaped, substantially dish-shaped, or substantially parabolic-shaped reflecting surface in the wire bonding type LED manufactured by any one of the first to third means. Is bonded to the bottom surface of the substrate using a substantially transparent adhesive.
[0026]
According to such a configuration, in the wire bonding type LED, the light output from the inclined surface can be efficiently extracted in the light extraction direction by the light transmitting action of the adhesive and the reflecting action of the reflective surface. Can be output.
When the adhesive covers the inclined surface, the inclination angle θ of the inclined surface measured from the vertical direction, of course, various conditions such as the refractive index of the adhesive should be sufficiently considered. Therefore, it is desirable to adjust and set a suitable or optimum value so that the external quantum efficiency is sufficiently increased.
[0027]
Hereinafter, an important or more preferable manufacturing method related to the manufacturing process of the semiconductor light emitting device of the present invention will be described.
[0028]
That is, the seventh means is to irradiate a back surface of a semiconductor wafer having a plurality of semiconductor light emitting elements with a laser beam in the manufacturing process of the semiconductor light emitting element manufactured by any one of the first to sixth means. A laser irradiation step of forming a divided groove having a substantially V-shaped cross-section and a depth of 50 μm or more formed by the above-mentioned two inclined surfaces, and dividing the semiconductor wafer into semiconductor light-emitting element units using the divided groove. And a wafer dividing step for dividing.
However, the depth of the groove is, of course, even better if it is 100 μm or more.
[0029]
By such a method, it is possible to easily form the depth, the size, and the shape of the above-mentioned division groove to desired specifications. In addition, since the polishing process for the back surface of the substrate can be omitted, the manufacturing time can be significantly reduced as compared with the related art.
Furthermore, if a semiconductor light emitting device is manufactured by such a method, the inclined surface of the substrate side wall can be formed simultaneously with the above-mentioned dividing groove, so that the number of processing steps and further the dividing portion between each semiconductor light emitting device (between each chip). Can be reduced rationally, so that a larger number of chips (light emitting elements) can be formed on a single semiconductor wafer of the same area in a shorter time than in the past. Therefore, it is very convenient in terms of productivity and the like.
Alternatively, even in the case where the same number of chips (light emitting elements) as in the past is formed on one semiconductor wafer having the same area, the inclined surface of the substrate side wall, which could not be secured conventionally, can be easily formed. It is.
That is, such a method is very suitable for manufacturing the above-described semiconductor light emitting device of the present invention.
[0030]
An eighth means is that, in the seventh means, the substantially V-shaped inner angle of the divided groove is set to 20 ° or more and 90 ° or less.
If such a substantially V-shaped dividing groove is formed, the above-described inclination angle θ of the inclined surface can be simultaneously formed to an optimum or suitable value.
[0031]
The ninth means is to irradiate a laser beam by blasting, etching, or polishing the back surface of the semiconductor wafer between the laser irradiation step and the wafer dividing step of the seventh or eighth means. Is provided with a scattered matter removing step of removing scattered matter generated with the above.
[0032]
If such a scattered matter removing step is provided, even if the molten material of the substrate melted by the irradiation of the laser beam scatters and adheres to the back surface or the side wall (inclined portion) of the substrate, etc. Since there is no semiconductor crystal layer on which the crystal is grown, the back surface of the semiconductor wafer can be blasted, etched, or polished sufficiently powerfully, whereby the scattered matter (melt) easily absorbs light. Can be easily and reliably removed from the interface (back surface or side wall) of the substrate. Therefore, according to such a method, external quantum efficiency can be effectively improved.
[0033]
The tenth means is to blast the back surface of the semiconductor wafer between the scattered matter removing step of the ninth means and the wafer dividing step or instead of the scattered matter removing step of the ninth means. A heat-affected layer removing step of removing a heat-affected layer generated by laser beam irradiation by performing etching, or polishing.
[0034]
However, the above-mentioned heat-affected layer refers to a part of the layer of the substrate that is strongly affected by the heat generated by the irradiation of the laser beam. Such a heat-affected layer often has an adverse effect on the strain (stress), light-transmitting property, or refractive index of the substrate, and thus it is desirable to remove the heat-affected layer. However, according to the eleventh means, These heat-affected layers can be removed as in the case of the above-mentioned scattered matter (melt). That is, even by such a method, the external quantum efficiency of the semiconductor light emitting device can be improved.
[0035]
An eleventh means is that, in the ninth or tenth means, the opening width of the division groove is 25 μm or more. The opening width of the dividing groove is more desirably 50 μm or more. According to such a configuration, when the above sloping surface is subjected to blasting or etching, the action of the processing effectively covers the entire surface of the sloping surface, so that the processing can be performed efficiently, easily or reliably. Can be implemented.
[0036]
More specifically, for example, in the case of blasting, particles having a diameter of about 5 μm are often used, but by setting the opening width of the above-mentioned dividing groove to 25 μm or more (more preferably 50 μm or more), At a stage before the division, the particles can be hit on substantially the entire inclined surface.
[0037]
According to a twelfth aspect, in any one of the seventh to eleventh aspects, at least the n-type semiconductor layer is exposed at a division allowable region of the semiconductor wafer located on the opposite side of the division groove with the substrate interposed therebetween. That is, an etching step of dividing into allowable regions, which etches from the upper surface of the semiconductor wafer up to the above, is provided. Needless to say, the above-mentioned division allowable region may be etched until the substrate is exposed or cut off from the upper surface of the semiconductor wafer.
[0038]
For example, in the semiconductor wafer 800 of FIG. 1 described above, the division allowable region 1c located on the opposite side of the division groove S composed of the two inclined surfaces 1a is processed by etching the substrate 1 until the substrate 1 is partially removed. It is formed by doing.
By providing the above-described division allowable region etching step, the semiconductor wafer can be divided more easily, accurately, or reliably at a desired position.
[0039]
A thirteenth means is that, in the twelfth means, a step of scribing or dicing the division allowable area is provided after the division allowable area etching step.
By providing such a process, the semiconductor wafer can be further easily, accurately, or surely divided at a desired position.
By the means of the present invention described above, the above problems can be effectively or rationally solved.
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described based on specific examples. However, the present invention is not limited to the embodiments described below.
[First embodiment]
FIG. 2 illustrates a schematic cross-sectional view of the semiconductor wafer 800 before the laser irradiation step in the first embodiment. On the upper surface (crystal growth surface) of the substrate 1 made of sapphire, an n-type semiconductor layer 2a, a p-type semiconductor layer 2b, and the like are sequentially laminated by a crystal growth process.
[0041]
The thickness t from the upper surface of the p-type semiconductor layer 2b to the back surface 1b of the substrate is about 350 μm, the negative electrode 6 is deposited on the n-type semiconductor layer 2a, and the positive electrode 7 is deposited on the p-type semiconductor layer 2b. ing.
The division allowable region 1c provided in the semiconductor wafer 800 is formed by performing dry etching from above to expose a portion below the upper surface (crystal growth surface) of the substrate 1.
[0042]
FIG. 3 is a schematic sectional view of the semiconductor wafer 800 in the laser irradiation step in the first embodiment. The inclined surface 1a is provided by forming a division groove S having a substantially V-shaped cross section in the semiconductor wafer 800.
FIG. 4 shows a cross-sectional photograph (b) illustrating a typical shape of the inclined surface 1a of the substrate 1 in FIG. 3, and an explanatory diagram (a) specifically illustrating the processing method. The cross-sectional shape illustrated in the cross-sectional photograph (b) may be changed in the same direction (the y-axis direction in FIG. 1) by gradually changing the irradiation position of the laser beam, the depth of the focal point, and the like as illustrated in the explanatory diagram (a). The laser beam can be formed by scanning the beam end about 10 times in ()).
[0043]
In the laser irradiation step, for example, a third harmonic (wavelength: 355 nm) of a YAG laser is used to irradiate a laser beam having a beam diameter of about 5 μm to 10 μm, and a depth of about 50 μm to 250 μm from the back surface 1 b of the substrate 1. A deep continuous linear separation groove S is formed.
[0044]
FIG. 5 is a schematic sectional view of the semiconductor wafer 800 in the heat affected layer removing step in the first embodiment. In this step, a heat-affected layer (not shown) accompanying the laser processing is removed by blasting. At this time, the scattered matter and the melt attached to the back surface 1b and the inclined surface 1a of the substrate 1 can be removed at the same time. Many arrows pointing to the back surface 1b in FIG. 5 indicate the direction in which the particles used for the blast processing are charged.
[0045]
Since the above-mentioned heat-affected layer often has an adverse effect on the strain (stress), light-transmitting property, or refractive index of the substrate, it is desirable to remove the heat-affected layer. External quantum efficiency can be improved.
[0046]
Further, it is preferable that the opening width of the above-mentioned dividing groove is 25 μm or more. The opening width of the dividing groove is more desirably 50 μm or more. According to such a configuration, when the above-mentioned sloping surface 1a is blast-processed, the effect of the processing effectively covers the entirety of the sloping surface 1a, so that the sloping surface 1a or the like is efficiently, easily or reliably processed. be able to. For example, when particles having a diameter of about 4 μm are used, by setting the opening width of the division groove S to about 50 μm to 60 μm, the particles can be efficiently hit on substantially the entire surface of the inclined surface 1 a.
[0047]
FIG. 6 is a schematic sectional view of the semiconductor wafer 800 in the scribing process in the first embodiment. When the height h (that is, the depth of the divided groove S) h of the inclined surface 1a constituting the substantially V-shaped divided groove S is sufficiently high (deep), or the width of the divided allowable area 1c (the left-right direction in FIG. 6). In general, it is desirable to provide the scribe line 1e in the division allowable area 1c, except when the width is large enough or when the inclination angle θ of the inclined surface 1a is sufficiently small. By setting the scribe line 1e, the semiconductor wafer 800 can be easily, accurately, or surely divided at a desired position.
[0048]
FIG. 7 is a schematic cross-sectional view of the semiconductor light emitting device 101 according to the first embodiment formed and divided according to the above steps. However, illustration of the electrodes (6, 7) and the like is omitted. Reference numeral 1d indicates a separation surface from the adjacent element (that is, a side wall of the semiconductor light emitting element 101).
[0049]
The semiconductor light emitting device 101 is based on a flip-chip type mounting method. The semiconductor light emitting device 101 has a larger inclination angle θ, height h, and radius of curvature R than the semiconductor light emitting device 100 of FIG. It is formed by securing approximately the same size. When chamfering a ridge (L1, L2) formed by the inclined surface 1a and the back surface 1b in FIG. 1, the radius of curvature R of the chamfered portion is the height h of the inclined surface 1a in the semiconductor light emitting device 101 in FIG. About half of the size is secured.
[0050]
For example, by making the shape of the substrate 1 of the semiconductor light emitting element 101 into a convex lens shape as described above, the light output direction of the LED can be narrowed down to a desired range.
Further, by providing a wide inclined surface 1a on the side wall and appropriately securing the inclination angle θ and the radius of curvature R, the external quantum efficiency can be improved as compared with the related art.
For example, the tilt angle θ may be adjusted optically in the laser irradiation step, or may be adjusted mechanically as described above. Further, the radius of curvature R can be adjusted according to the size and processing time of the particles used for the blast processing, the input speed of the particles, and the like.
[0051]
FIG. 8 is a schematic cross-sectional view of a semiconductor wafer 801 illustrating a modified example of the first embodiment. The scribe line 1e 'at the approximate center of the semiconductor wafer 801 in the figure is formed by performing scribe processing on the same surface as the exposed surface 1c' of the n-type semiconductor layer 2a on which the negative electrode 6 is deposited.
[0052]
According to such a configuration, a dedicated etching process for exposing a processing target surface to be subjected to scribe processing is not required, and such an etching process and a deposition target surface on which the negative electrode 6 is to be deposited are exposed. It is possible to carry out the same process at the same time without distinguishing the etching process for performing the same.
The first embodiment described above may be implemented, for example, in such a modified embodiment. In particular, according to such a procedure, it is possible to shorten the manufacturing time of the semiconductor light emitting device or to simplify the manufacturing process.
[0053]
[Second embodiment]
FIG. 9 is a schematic sectional view of the semiconductor light emitting device 102 according to the second embodiment. As shown in FIG. 9, the semiconductor light emitting device 102 conforms to a mounting method of a wire bonding type, and is manufactured according to a manufacturing process substantially equivalent to the manufacturing process exemplified in the first embodiment.
Reference numeral 6 indicates a negative electrode provided on the n-type semiconductor layer 2a, and reference numeral 7 indicates a positive electrode provided on the p-type semiconductor layer 2b.
[0054]
The lead frame 3 is provided with a substantially parabolic reflection surface 3a, and the surface is formed in a substantially mirror-like shape. The substrate 1 of the semiconductor light emitting element 102 is adhered to the center of the inner bottom of the reflection surface 3a by the translucent adhesive 4. It is desirable to select a transparent material as much as possible from the viewpoint of improving the external quantum efficiency. However, since the substrate 1 of the semiconductor light emitting device 102 can be sufficiently thick based on the configuration of the present invention, a short circuit occurs at the pn junction even if a conductive adhesive is used. Therefore, in such a case, it is not necessary to select a material having an insulating property as the translucent adhesive 4.
[0055]
The inclination angle θ of the inclined surface 1a of the semiconductor light emitting element 102 is desirably set appropriately or optimally according to the magnitude of the refractive index of the translucent adhesive 4. Alternatively, the value of the inclination angle θ of the inclined surface 1a may be determined in advance, and the material may be adjusted so that the material of the translucent adhesive 4 is selected in consideration of various conditions such as the refractive index. .
[0056]
In the above-described semiconductor light emitting device 102, the efficiency of light extraction from the side wall of the substrate 1 having the inclined surface 1a is higher than that of the conventional semiconductor light emitting device by the above-described operation of the present invention. Also in the mounting mode of the (semiconductor light emitting element), a higher external quantum efficiency can be secured than before.
[Brief description of the drawings]
FIG. 1 is a schematic explanatory view illustrating a cross-sectional shape of a semiconductor wafer 800 having a plurality of semiconductor light emitting devices 100 according to the present invention.
FIG. 2 is a schematic cross-sectional view of the semiconductor wafer 800 before a laser irradiation step in the first embodiment of the present invention.
FIG. 3 is a schematic sectional view of a semiconductor wafer 800 in a laser irradiation step according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional photograph (b) illustrating a typical shape of the inclined surface 1a of the substrate 1 in FIG. 3, and an explanatory diagram (a) specifically illustrating a processing method thereof.
FIG. 5 is a schematic sectional view of the semiconductor wafer 800 in a heat affected layer removing step according to the first embodiment of the present invention.
FIG. 6 is a schematic cross-sectional view of the semiconductor wafer 800 in a scribe step according to the first embodiment of the present invention.
FIG. 7 is a schematic sectional view of the semiconductor light emitting device 101 according to the first embodiment of the present invention.
FIG. 8 is a schematic sectional view of a semiconductor wafer 801 illustrating a modification of the first embodiment of the present invention.
FIG. 9 is a schematic sectional view of a semiconductor light emitting device 102 according to a second embodiment of the present invention.
[Explanation of symbols]
800: semiconductor wafer 100: semiconductor light emitting device 101: semiconductor light emitting device (first embodiment: flip chip type)
102 semiconductor light emitting device (second embodiment: wire bonding type)
DESCRIPTION OF SYMBOLS 1 ... Substrate 1a ... Inclination surface 1b ... Substrate back surface 1c ... Permissible division area 1d of semiconductor wafer ... Separation surface of semiconductor wafer 800 (side wall of semiconductor light emitting element 101)
2a n-type semiconductor layer 2b p-type semiconductor layer 3 lead frame 4 translucent adhesive 6 negative electrode 7 positive electrode h height of inclined surface 1a (depth of substantially V-shaped dividing groove) )
t: the thickness of the semiconductor wafer 800 θ: the inclination angle Li measured from the vertical direction of the inclined surface 1a: the ridge formed by the back surface 1b of the substrate and the inclined surface 1a (i = 1, 2)
R: radius of curvature of the chamfered part when chamfering the edge Li

Claims (13)

基板の上面（表側の水平面）上に結晶成長により複数の半導体層を積層して形成される半導体発光素子において、
前記基板の側壁は、前記基板の裏側に斜めに露出し、かつ、前記基板の裏面にまで連なる、少なくとも高さ５０μｍ以上の傾斜面を有する
ことを特徴とする半導体発光素子。In a semiconductor light emitting device formed by stacking a plurality of semiconductor layers by crystal growth on an upper surface (a horizontal surface on a front side) of a substrate,
A semiconductor light-emitting device, wherein a side wall of the substrate has an inclined surface having a height of at least 50 μm or more, which is obliquely exposed on the back side of the substrate and continues to the back surface of the substrate. 前記傾斜面の高さは、１００μｍ以上である
ことを特徴とする請求項１に記載の半導体発光素子。The device according to claim 1, wherein the height of the inclined surface is 100 μm or more. 鉛直方向から測った前記傾斜面の傾斜角θを１０°以上４５°以下にした
ことを特徴とする請求項１又は請求項２に記載の半導体発光素子。The semiconductor light emitting device according to claim 1, wherein an inclination angle θ of the inclined surface measured from a vertical direction is set to 10 ° or more and 45 ° or less. フリップチップ型のＬＥＤであって、
前記基板の裏面と前記傾斜面とが成す稜の少なくとも一部は、面取りされている
ことを特徴とする請求項１乃至請求項３のいずれか１項に記載の半導体発光素子。A flip-chip type LED,
4. The semiconductor light emitting device according to claim 1, wherein at least a part of a ridge formed by the back surface of the substrate and the inclined surface is chamfered. 5. 前記稜に対して垂直な断面における、前記稜が面取りされた部分の曲率半径は、１０μｍ以上５００μｍ以下である
ことを特徴とする請求項４に記載の半導体発光素子。5. The semiconductor light emitting device according to claim 4, wherein a radius of curvature of a portion where the ridge is chamfered in a cross section perpendicular to the ridge is 10 μm or more and 500 μm or less. ワイヤーボンディング型のＬＥＤであって、
略グラス形状、略深皿形状、又は略パラボラ形状の反射面を有するリードフレームの内側底部に、略透明の接着剤を用いて前記基板の裏面が接着されている
ことを特徴とする請求項１乃至請求項３のいずれか１項に記載の半導体発光素子。A wire bonding type LED,
2. The back surface of the substrate is adhered to an inner bottom portion of a lead frame having a reflection surface of a substantially glass shape, a substantially deep dish shape, or a substantially parabolic shape using a substantially transparent adhesive. The semiconductor light emitting device according to claim 1. 請求項１乃至請求項６の何れか１項に記載の半導体発光素子の製造方法であって、
前記半導体発光素子を複数有する半導体ウエハの裏面にレーザービームを照射することにより、二面の前記傾斜面から成り、断面形状が略Ｖ字型で深さが５０μｍ以上の分割溝を形成するレーザー照射工程と、
前記分割溝を用いて前記半導体ウエハを前記半導体発光素子単位に分割するウエハ分割工程と
を有する
ことを特徴とする半導体発光素子の製造方法。The method for manufacturing a semiconductor light emitting device according to claim 1, wherein:
By irradiating a laser beam to a back surface of a semiconductor wafer having a plurality of the semiconductor light emitting elements, laser irradiation is performed which forms a divided groove having two inclined surfaces, a substantially V-shaped cross section, and a depth of 50 μm or more. Process and
A wafer dividing step of dividing the semiconductor wafer into the semiconductor light emitting element units using the division grooves. 前記分割溝の前記略Ｖ字型の内角を２０°以上９０°以下にした
ことを特徴とする請求項７に記載の半導体発光素子の製造方法。8. The method according to claim 7, wherein an inner angle of the substantially V-shape of the division groove is set to be not less than 20 [deg.] And not more than 90 [deg.]. 前記レーザー照射工程と前記ウエハ分割工程との間に、前記半導体ウエハの裏面をブラスト処理、エッチング処理、又は研磨処理することにより、前記レーザービームの照射に伴って発生した飛散物を除去する飛散物除去工程を有する
ことを特徴とする請求項７又は請求項８に記載の半導体発光素子の製造方法。Between the laser irradiation step and the wafer division step, the back surface of the semiconductor wafer is blasted, etched, or polished to remove scattered matter generated by the laser beam irradiation. The method for manufacturing a semiconductor light emitting device according to claim 7, further comprising a removing step. 前記飛散物除去工程と前記ウエハ分割工程との間に、或いは、前記飛散物除去工程の代りに、
前記半導体ウエハの裏面をブラスト処理、エッチング処理、又は研磨処理することにより、前記レーザービームの照射に伴って発生した熱影響層を除去する熱影響層除去工程を有する
ことを特徴とする請求項９に記載の半導体発光素子の製造方法。Between the scattered matter removing step and the wafer dividing step, or instead of the scattered matter removing step,
10. A heat-affected layer removing step of removing a heat-affected layer generated by the irradiation of the laser beam by blasting, etching, or polishing the back surface of the semiconductor wafer. 3. The method for manufacturing a semiconductor light emitting device according to item 1. 前記分割溝の開口幅を２５μｍ以上にした
ことを特徴とする請求項９または請求項１０に記載の半導体発光素子の製造方法。The method according to claim 9, wherein an opening width of the division groove is set to 25 μm or more. 前記基板を挟んで前記分割溝の反対側に位置する前記半導体ウエハの分割許容領域を少なくともｎ型半導体層が露出するまで前記半導体ウエハの上面よりエッチングする分割許容領域エッチング工程を有する
ことを特徴とする請求項７乃至請求項１１の何れか１項に記載の半導体発光素子の製造方法。A dividing allowable region etching step of etching a dividing allowable region of the semiconductor wafer located on the opposite side of the dividing groove with the substrate from an upper surface of the semiconductor wafer until at least an n-type semiconductor layer is exposed. The method of manufacturing a semiconductor light emitting device according to claim 7. 前記分割許容領域エッチング工程の後に、前記分割許容領域をスクライブ又はダイシングする工程を有する
ことを特徴とする請求項１２に記載の半導体発光素子の製造方法。13. The method according to claim 12, further comprising a step of scribing or dicing the divided allowable area after the dividing allowable area etching step.
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