KR20120000247A - Stack package - Google Patents

Stack package Download PDF

Info

Publication number
KR20120000247A
KR20120000247A KR1020100060504A KR20100060504A KR20120000247A KR 20120000247 A KR20120000247 A KR 20120000247A KR 1020100060504 A KR1020100060504 A KR 1020100060504A KR 20100060504 A KR20100060504 A KR 20100060504A KR 20120000247 A KR20120000247 A KR 20120000247A
Authority
KR
South Korea
Prior art keywords
substrate
semiconductor chips
semiconductor
stacked
locking tape
Prior art date
Application number
KR1020100060504A
Other languages
Korean (ko)
Inventor
김승지
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020100060504A priority Critical patent/KR20120000247A/en
Publication of KR20120000247A publication Critical patent/KR20120000247A/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: A stacked package is provided to reduce the height of an entire stacked package by forming a locking tape on the upper side part of a semiconductor chip which is arranged in an utmost top part. CONSTITUTION: Two or more semiconductor chips(110) are placed on a substrate(100). A connecting member(120) electrically connects the semiconductor chips and the substrate. A locking tape(130) is formed on the semiconductor chip except for a bonding pad part. A sealing member(140) seals the one side of the substrate which includes the locking tape, the connecting member, and the semiconductor chips. An outer connection member(150) is formed in the other side of the substrate which faces the one side of the substrate.

Description

Stack Package {STACK PACKAGE}

The present invention relates to a stack package, and more particularly, to a stack package capable of preventing warpage of semiconductor chips.

Packaging technology for semiconductor integrated circuits has been continuously developed to meet the demand for miniaturization and mounting efficiency. Recently, various technologies for "stack" have been developed as miniaturization and high performance of electric / electronic products are required. have. The term "stack" in the semiconductor industry refers to a technology in which at least two chips or packages are stacked vertically, and according to the stack technology, a product having a memory capacity that is twice as large as the memory capacity that can be realized in a semiconductor integration process may be implemented. In addition, the efficiency of the use of the mounting area can be improved.

However, in the stack package according to the related art described above, as a plurality of semiconductor chips are stacked on a substrate, an overhang occurs at an edge portion of the semiconductor chips. As a result, warpage of the semiconductor chip occurs at the portion where the overhang occurs, which causes a problem that the height of the stack package is increased to expose the semiconductor chip disposed at the top even after the subsequent molding process. The warpage phenomenon of these semiconductor chips is further intensified when the semiconductor chips are stacked stepwise on the substrate.

The present invention provides a stack package capable of preventing warpage of semiconductor chips.

According to an embodiment of the present invention, a stack package includes a substrate, at least two or more semiconductor chips stacked on the substrate, and other edges and sides facing the one edge from an upper surface of one edge of at least one of the stacked semiconductor chips. And a locking tape formed to extend through the substrate.

The semiconductor chips are stacked stepwise on the substrate.

The locking tape extends from an upper surface of the semiconductor chip disposed on the top of the semiconductor chips to the substrate.

The locking tape extends from the top surface of each of the semiconductor chips to the substrate.

According to an embodiment of the present invention, a stack package may include: a connecting member electrically connecting the semiconductor chips and between the semiconductor chips and the substrate; an encapsulation member sealing one surface of the substrate including the connecting member and the semiconductor chips; It further includes an external connection terminal formed on the other surface opposite to one surface of the substrate.

The present invention provides a stack package in which a plurality of semiconductor chips are stacked in a stepped manner, by forming a locking tape extending from an upper surface of one side edge of the stacked semiconductor chips to a side surface of the stacked semiconductor chips, thereby effectively bending the stacked semiconductor chips. It can prevent.

In addition, the present invention can reduce the height of the entire stack package by forming the locking tape only on the upper surface portion of the semiconductor chip disposed on the top, through which the encapsulation member does not completely surround the semiconductor chips, exposing the top semiconductor chip. The phenomenon can be prevented.

1 is a cross-sectional view showing a stack package according to an embodiment of the present invention.
2 is a cross-sectional view for explaining a locking tape in a stack package according to an embodiment of the present invention.
3 is a cross-sectional view showing a stack package according to another embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 is a cross-sectional view showing a stack package according to an embodiment of the present invention.

As shown, at least two or more semiconductor chips 110 are stacked on the substrate 100 in an electrically connected state. The substrate 100 may include, for example, a printed circuit board having a connection pad (not shown), and the semiconductor chips 110 may each include, for example, memory chips having bonding pads (not shown). In addition, the semiconductor chips 110 may be chips of the same type or chips of different types.

The semiconductor chips 110 are stacked in a stepped manner on the substrate 100 with an adhesive 105 interposed therebetween. The semiconductor chips 110 are stacked so that the bonding pads are exposed in a stepped manner toward one direction in the lower layer, and the bonding pads are exposed in the other direction opposite to the one direction in the upper layer. Although not shown, the semiconductor chips 110 may be stacked to expose the bonding pads in a stepped direction in both lower and upper layers, or may be stacked in various other ways.

A connection member 120 electrically connecting the stacked semiconductor chips 110 and between the semiconductor chips 110 and the substrate 100 is formed. The connection member 120 may include, for example, bonding wires electrically connecting the connection pads of the substrate 100 and the respective bonding pads of the semiconductor chip 110. Various connection means such as leads are applicable.

At least one or more of the stacked semiconductor chips 110, for example, a locking tape extending from an upper surface of one edge of each of the semiconductor chips 110 to the substrate 100 through the other edge and the side opposite to the one edge. Locking Tape 130 is formed. The locking tape 130 includes, for example, a spacer tape. Here, the locking tape 130 is formed to extend from the top surface of the stacked semiconductor chips 110 to the substrate 100 through the side surface, thereby functioning to physically fix the semiconductor chips 110. According to the present invention, a stack package having improved warpage of the semiconductor chips 110 may be obtained.

The locking tape 130 may be formed on the semiconductor chips 110 except for the bonding pad portion, or may be formed on the semiconductor chip 110 including the bonding pad portion, and the locking tape 130 may be formed. When formed on the semiconductor chip 110 including the bonding pad portion, for example, a Penetration Wafer Backside Lamination (PWBL) tape is used as the locking tape 130. In addition, the locking tape 130 may also serve as an adhesive member between the semiconductor chips 110 disposed above and below, so that the adhesive 105 may be omitted when the semiconductor chips 110 are stacked. .

An encapsulation member 140 is formed to seal one surface of the substrate 100 including the locking tape 130, the connection member 120, and the semiconductor chips 110, and the other surface facing the one surface of the substrate 100. An external connection terminal 150 is formed thereon. In the embodiment of the present invention, since the warping phenomenon of the semiconductor chips 110 is prevented by the locking tape 130, the height of the entire stack package is not increased due to the warpage of the semiconductor chips 110. Thus, according to the present invention, since the encapsulation member 140 is formed to sufficiently seal the stacked semiconductor chips 110, it is possible to prevent the semiconductor chip 110 disposed on the top thereof from being exposed.

FIG. 2 is a cross-sectional view illustrating a locking tape in a stack package according to an exemplary embodiment of the present invention. Hereinafter, a process of forming the locking tape will be described in detail with reference to FIG. 2.

As illustrated, after stacking the semiconductor chips 110 on the substrate 100 with the adhesive 105 interposed therebetween, a portion A of the locking tape 130 may be formed on an upper surface of one side edge of the semiconductor chip 110. ) Is attached. The locking tape 130 is attached in a dual head manner, for example, and a first head of the dual heads picks up the locking tape 130 to the upper surface of the semiconductor chip 110. Attach. Then, with the locking tape 130 attached on the upper surface of the semiconductor chip 110, the second head picks up the remaining locking tape portion B in a vacuum state and attaches it on the substrate 100. do. In this way, it is possible to attach the locking tape 130 in a bent shape extending from the upper surface portion of one side edge of the semiconductor chip 110 to the substrate through its side surface.

Meanwhile, in the above-described embodiment of the present invention, each of the locking tapes extending from the top surface of each of the semiconductor chips stacked on the substrate to the substrate is formed, but as another embodiment of the present invention, the semiconductor chips stacked on the substrate By forming the locking tape only on the upper surface of the uppermost semiconductor chip in which the most severe bending occurs, the height of the entire stack package can be reduced.

3 is a cross-sectional view showing a stack package according to another embodiment of the present invention.

As shown, at least two or more semiconductor chips 110 are stacked on the substrate 100 in an electrically connected state. The substrate 100 may include, for example, a printed circuit board having a connection pad (not shown), and the semiconductor chips 110 may each include, for example, memory chips having bonding pads (not shown). In addition, the semiconductor chips 110 may be chips of the same type or chips of different types.

The semiconductor chips 110 are stacked in a stepped manner on the substrate 100 with an adhesive 105 interposed therebetween. The semiconductor chips 110 are stacked so that the bonding pads are exposed in a stepped manner toward one direction in the lower layer, and the bonding pads are exposed in the other direction opposite to the one direction in the upper layer. Although not shown, the semiconductor chips 110 may be stacked to expose the bonding pads in a stepped direction in both lower and upper layers, or may be stacked in various other ways.

A connection member 120 electrically connecting the stacked semiconductor chips 110 and between the semiconductor chips 110 and the substrate 100 is formed. The connection member 120 may include, for example, a bonding wire electrically connected between the connection pad of the substrate 100 and the bonding pad of the semiconductor chip 110, and although not shown, a through electrode, solder, and conductive tape. And various connection means such as leads.

Among the stacked semiconductor chips 110, the semiconductor chip disposed at the top of the lower layer semiconductor chips 110 stacked in a step direction toward one direction and the upper semiconductor chips 110 stacked stepwise toward the other direction opposite to the one direction. The locking tape 130 is formed by extending from the upper surface of one edge of the semiconductor chip disposed at the uppermost portion thereof to the substrate 100 through the other edge and the side opposite to the one edge.

The locking tape 130 may be formed on the semiconductor chips 110 except for the bonding pad portion, or may be formed on the semiconductor chip 110 including the bonding pad portion, and the locking tape 130 may be formed. When formed on the semiconductor chip 110 including the bonding pad portion, for example, a Penetration Wafer Backside Lamination (PWBL) tape is used as the locking tape 130. In addition, the locking tape 130 may also serve as an adhesive member between the semiconductor chips 110 disposed above and below, so that the adhesive 105 may be omitted when the semiconductor chips 110 are stacked. .

On the other hand, although not shown, when the semiconductor chips 110 are stacked stepwise in both the lower layer and the upper layer, the locking tape 130 extending to the substrate 100 only in the uppermost portion of the semiconductor chip disposed at the top It is also possible to form.

The locking tape 130 includes, for example, a spacer tape. Here, the locking tape 130 functions to physically fix the semiconductor chip 110 and the substrate disposed on the top of which the bending occurs most severely. It is possible to obtain a stack package in which the warpage phenomenon of 110 is effectively improved.

An encapsulation member 140 is formed to seal one surface of the substrate 100 including the locking tape 130, the connection member 120, and the semiconductor chips 110, and the other surface facing the one surface of the substrate 100. An external connection terminal 150 is formed thereon. In the exemplary embodiment of the present invention, since the warping phenomenon of the semiconductor chip 110 disposed at the top where the warping phenomenon is most severely generated by the locking tape 130 is prevented, the warping phenomenon of the semiconductor chip 110 may occur. There was no increase in the height of the entire stack package, so, according to the present invention, the encapsulation member 140 is formed to sufficiently seal the stacked semiconductor chips 110, so that the semiconductor chips 110 disposed on the uppermost portion of the stack package are formed. Exposure can be prevented.

As described above, in another embodiment of the present invention, instead of forming the locking tape 130 on all of the semiconductor chips 110, only the uppermost semiconductor chip 110 in which warpage occurs relatively, is formed. It is possible to effectively prevent the increase of the height of the entire stack package while improving the warpage of the uppermost semiconductor chip 110 where the warpage phenomenon occurs most severely. Therefore, in another embodiment of the present invention, the phenomenon in which the uppermost semiconductor chip 110 is exposed can be prevented more effectively.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

100: substrate 105: adhesive
110 semiconductor chip 120 connection member
130: locking tape 140: sealing member
150: external connection terminal

Claims (5)

Board;
At least two semiconductor chips stacked on the substrate; And
A locking tape extending from the upper surface of at least one edge of at least one of the stacked semiconductor chips to the substrate through the other edge and side facing the one edge;
Semiconductor package comprising a. The method of claim 1,
And the semiconductor chips are stacked stepwise on the substrate. The method of claim 1,
The locking tape is a semiconductor package, characterized in that formed extending from the top surface of the semiconductor chip disposed on the top of the semiconductor chip to the substrate. The method of claim 1,
The locking tape is a semiconductor package, characterized in that formed to extend from the top surface of each of the semiconductor chips to the substrate, respectively. The method of claim 1,
A connection member electrically connecting the semiconductor chips and between the semiconductor chips and the substrate;
An encapsulation member sealing one surface of the substrate including the connection member and the semiconductor chips; And
An external connection terminal formed on the other surface opposite to one surface of the substrate;
The semiconductor package further comprises.
KR1020100060504A 2010-06-25 2010-06-25 Stack package KR20120000247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020100060504A KR20120000247A (en) 2010-06-25 2010-06-25 Stack package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020100060504A KR20120000247A (en) 2010-06-25 2010-06-25 Stack package

Publications (1)

Publication Number Publication Date
KR20120000247A true KR20120000247A (en) 2012-01-02

Family

ID=45608156

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020100060504A KR20120000247A (en) 2010-06-25 2010-06-25 Stack package

Country Status (1)

Country Link
KR (1) KR20120000247A (en)

Similar Documents

Publication Publication Date Title
KR101070913B1 (en) Stacked die package
TWI401785B (en) Stacked multichip package
US8288873B2 (en) Stack package having flexible conductors
US8492889B2 (en) Semiconductor package
KR101219484B1 (en) Semiconductor chip module and semiconductor package having the same and package module
JP2010087403A (en) Semiconductor device
KR100743649B1 (en) Multi chip package
KR20100020766A (en) Stack package
KR20030059459A (en) Chip stack package
KR101458954B1 (en) Semiconductor Package apparatus having redistribution layer
KR20120000247A (en) Stack package
KR20100050981A (en) Semiconductor package and stack package using the same
KR20090022433A (en) Semiconductor package
KR100826976B1 (en) Planar stack package
KR20080074654A (en) Stack semiconductor package
KR20070043390A (en) Stack package using semiconductor chip with exposing part
KR20060133800A (en) Chip stack package
KR20110133772A (en) Semiconductor chip and stack package including the same
JP5149694B2 (en) Semiconductor device and manufacturing method thereof
KR20080074662A (en) Stack package
KR100650770B1 (en) Flip chip double die package
KR101096457B1 (en) multi package
JP5283946B2 (en) Semiconductor device and composite lead frame used therefor
KR101019705B1 (en) Substrate for fabricating semiconductor package and semiconductor package using the same
KR20110056769A (en) Interposer for stack package and stack package using the interposer

Legal Events

Date Code Title Description
WITN Withdrawal due to no request for examination