KR20110138209A - 클럭 듀티 싸이클 조정에 의한 반도체 디바이스의 성능 저하 보상 - Google Patents

클럭 듀티 싸이클 조정에 의한 반도체 디바이스의 성능 저하 보상 Download PDF

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Publication number
KR20110138209A
KR20110138209A KR1020117014958A KR20117014958A KR20110138209A KR 20110138209 A KR20110138209 A KR 20110138209A KR 1020117014958 A KR1020117014958 A KR 1020117014958A KR 20117014958 A KR20117014958 A KR 20117014958A KR 20110138209 A KR20110138209 A KR 20110138209A
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KR
South Korea
Prior art keywords
integrated circuit
duty cycle
performance
clock signal
circuit
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Withdrawn
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KR1020117014958A
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English (en)
Korean (ko)
Inventor
바실리오스 파파게오르지오우
마시에즈 위아트르
잔 호엔트쉘
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
에이엠디 팹 36 리미티드 라이어빌리티 컴퍼니 & 코. 카게
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Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드, 에이엠디 팹 36 리미티드 라이어빌리티 컴퍼니 & 코. 카게 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20110138209A publication Critical patent/KR20110138209A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/008—Reliability or availability analysis
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Pulse Circuits (AREA)
KR1020117014958A 2008-11-28 2009-11-27 클럭 듀티 싸이클 조정에 의한 반도체 디바이스의 성능 저하 보상 Withdrawn KR20110138209A (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
DE102008059502A DE102008059502A1 (de) 2008-11-28 2008-11-28 Kompensation der Leistungsbeeinträchtigung von Halbleiterbauelementen durch Anpassung des Tastgrades des Taktsignals
DE102008059502.0 2008-11-28
US12/604,532 US8018260B2 (en) 2008-11-28 2009-10-23 Compensation of degradation of performance of semiconductor devices by clock duty cycle adaptation
US12/604,532 2009-10-23

Publications (1)

Publication Number Publication Date
KR20110138209A true KR20110138209A (ko) 2011-12-26

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ID=42145369

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020117014958A Withdrawn KR20110138209A (ko) 2008-11-28 2009-11-27 클럭 듀티 싸이클 조정에 의한 반도체 디바이스의 성능 저하 보상

Country Status (6)

Country Link
US (1) US8018260B2 (https=)
JP (1) JP2012510742A (https=)
KR (1) KR20110138209A (https=)
CN (1) CN102308283A (https=)
DE (1) DE102008059502A1 (https=)
WO (1) WO2010060638A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9741443B2 (en) 2014-04-04 2017-08-22 Samsung Electronics Co., Ltd. Memory controller and system including the same
US10095420B2 (en) 2015-02-13 2018-10-09 Samsung Electronics Co., Ltd. Storage device communicating with specific pattern and operating method thereof

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8984305B2 (en) 2010-12-21 2015-03-17 Intel Corporation Method and apparatus to configure thermal design power in a microprocessor
US8578143B2 (en) * 2011-05-17 2013-11-05 Apple Inc. Modifying operating parameters based on device use
JP2015002452A (ja) * 2013-06-17 2015-01-05 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置
US9465373B2 (en) 2013-09-17 2016-10-11 International Business Machines Corporation Dynamic adjustment of operational parameters to compensate for sensor based measurements of circuit degradation
US9251890B1 (en) 2014-12-19 2016-02-02 Globalfoundries Inc. Bias temperature instability state detection and correction
US9704598B2 (en) * 2014-12-27 2017-07-11 Intel Corporation Use of in-field programmable fuses in the PCH dye
US11605416B1 (en) * 2021-11-10 2023-03-14 Micron Technology, Inc. Reducing duty cycle degradation for a signal path
CN119231931B (zh) * 2024-12-03 2025-04-01 浙江绿力智能科技有限公司 一种转换器智能调控方法及系统

Family Cites Families (10)

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Publication number Priority date Publication date Assignee Title
JPH04274100A (ja) * 1991-03-01 1992-09-30 Nec Corp テスト回路内蔵のメモリーｌｓｉ
JP2000012639A (ja) * 1998-06-24 2000-01-14 Toshiba Corp モニターｔｅｇのテスト回路
DE60122960T2 (de) * 2000-04-20 2007-03-29 Texas Instruments Incorporated, Dallas Digitale eingebaute Selbsttestschaltungsanordnung für Phasenregelschleife
US6903564B1 (en) * 2003-11-12 2005-06-07 Transmeta Corporation Device aging determination circuit
JP4360825B2 (ja) * 2002-04-24 2009-11-11 株式会社半導体エネルギー研究所 半導体装置の寿命予測方法
US7475320B2 (en) * 2003-08-19 2009-01-06 International Business Machines Corporation Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components
US7322001B2 (en) * 2005-10-04 2008-01-22 International Business Machines Corporation Apparatus and method for automatically self-calibrating a duty cycle circuit for maximum chip performance
US7333905B2 (en) * 2006-05-01 2008-02-19 International Business Machines Corporation Method and apparatus for measuring the duty cycle of a digital signal
US7330061B2 (en) * 2006-05-01 2008-02-12 International Business Machines Corporation Method and apparatus for correcting the duty cycle of a digital signal
US7495519B2 (en) * 2007-04-30 2009-02-24 International Business Machines Corporation System and method for monitoring reliability of a digital system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9741443B2 (en) 2014-04-04 2017-08-22 Samsung Electronics Co., Ltd. Memory controller and system including the same
US10095420B2 (en) 2015-02-13 2018-10-09 Samsung Electronics Co., Ltd. Storage device communicating with specific pattern and operating method thereof

Also Published As

Publication number Publication date
JP2012510742A (ja) 2012-05-10
US8018260B2 (en) 2011-09-13
DE102008059502A1 (de) 2010-06-10
US20100134167A1 (en) 2010-06-03
CN102308283A (zh) 2012-01-04
WO2010060638A1 (en) 2010-06-03

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PA0105 International application

Patent event date: 20110628

Patent event code: PA01051R01D

Comment text: International Patent Application

N231 Notification of change of applicant
PN2301 Change of applicant

Patent event date: 20111018

Comment text: Notification of Change of Applicant

Patent event code: PN23011R01D

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid