KR20110077118A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a producing method thereof are provided to improve the electrostatic capacity of a capacitor in an LDRAM device. CONSTITUTION: A semiconductor device comprises the following: a semiconductor substrate(100) including a first conductive well; a trench formed on the semiconductor substrate; an insulation pattern(155) formed in the inside of the trench for exposing the side wall of the trench; a high dielectric layer(190) formed on the exposed side wall of the trench; and a capacitor upper electrode formed on the upper side of the trench.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

The embodiment relates to a semiconductor device used in an LCD driver IC (LDI) required for driving a liquid crystal display (LCD) panel, and a method of manufacturing the same.

An LCD driver IC (LDI) is an integrated circuit (IC) that is essential for driving a liquid crystal display (LCD) panel, and refers to an integrated circuit that provides driving signals and data and interfaces with it.

Graphic random access memory (GRAM) memory, which stores data among the components of LDI, needs to be highly integrated in order to realize wide video graphics array (WVGA) high resolution that will be commercialized in the future.

When using 6T SRAM consisting of six conventional transistors, the chip size becomes larger and less competitive. Therefore, a method of miniaturizing and integrating chips is needed.

In particular, as high-density memory capacity is required for a high-performance display driver IC (DDI) structure, the memory of the SRAM structure has reached a limit in chip size shrink.

To this end, in addition to the process of forming three gate oxide films of LV (Medium Voltage), MV (Medium Voltage) and HV (High Voltage) formed in the existing LDI device, need.

Accordingly, by forming an LDRAM (Logic DRAM) composed of one capacitor in one transistor Tr in the LDI device, a memory device having a high density can be realized.

However, unlike general DRAM, it must be able to be formed at the same time as LDI, not a device for DRAM alone, so it is very difficult to make a capacitor using a deep VIA used in general DRAM.

In order to implement such a device, an oxide film serving as a capacitor of the LDRAM device is formed under the STI.

However, unlike oxide growth on active regions such as LV, MV, and HV devices, the oxide layer must be formed under the trench of the STI region, making the process complicated and difficult to optimize the process. have.

The embodiment provides a semiconductor device and a method of manufacturing the same that can improve the capacitance of an LDRAM device.

In an embodiment, a semiconductor device may include a semiconductor substrate on which a first conductivity type well is formed; A trench formed in the semiconductor substrate; An insulating pattern formed in the trench at a first height relative to the bottom surface of the trench to expose sidewalls of the trench; A high dielectric layer formed on sidewalls of the trench exposed by the insulating pattern; And a capacitor upper electrode formed on the trench including the high dielectric layer.

According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device may include: filling an oxide film in a first trench and a second trench in a semiconductor substrate, and forming a device isolation layer; Removing the oxide layer corresponding to the first trench to a predetermined thickness and exposing sidewalls of the first trench; forming a high dielectric layer only on the sidewalls of the first trench; And forming a capacitor upper electrode on the first trench that includes.

In an embodiment, the capacitance of the capacitor in the LDRAM device can be improved.

That is, since the capacitor dielectric layer is formed of a high dielectric layer, the capacitance of the capacitor can be increased.

The high dielectric layer may be selectively formed only on the sidewall of the STI trench, and the thickness thereof may be adjusted.

As a result, the capacitance of the capacitor can be stably managed and the reliability of the device can be improved.

Even if the capacitor area is small, the capacitance of the capacitor may be increased by the high dielectric layer.

Accordingly, the device can be miniaturized and highly integrated in LDLAM.

Since the capacitor dielectric layer is formed of a high dielectric constant material, the process margin of the insulating pattern formed under the STI trench can be greatly improved.

Accordingly, the isolation characteristics of the capacitors formed to be adjacent to each other in the STI trench can be improved.

Since the thickness of the insulating pattern may be optimized, the junction leakage of the capacitors adjacent to each other may be prevented and the reliability of the device may be improved.

Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

1 and 10, a semiconductor device according to an embodiment will be described.

1 is a circuit diagram of a semiconductor device for an LCD driver IC (LDI).

The LDI device may implement a logic DRAM (LDRAM) including one first transistor T1 and one first capacitor C1.

The first capacitor C1 may be formed using a trench in the STI region.

FIG. 10 is a cross-sectional view illustrating a structure of the semiconductor device for LDI shown in FIG. 1.

As shown in FIG. 10, the first transistor T1 of the LDI semiconductor device includes a gate 210, a spacer 230, and a source / drain 220 formed in the semiconductor substrate 100.

In the semiconductor substrate 100, an active region AA and a field region FA are defined by the device isolation layer 160.

A first conductivity type well NW doped with a first conductivity type impurity is formed in the active region AA of the semiconductor substrate 100.

For example, the first conductivity type impurities may be n type or p type impurities.

The first conductivity type well NW may be laid out as a first transistor region TA and first and second capacitor regions CA1 and CA2.

The first transistor T1 is formed in the first transistor area TA of the first conductivity type well NW.

The first capacitor C1 electrically connected to the first transistor T1 is formed in the first capacitor region C1 of the first conductivity type well NW.

The source / drain region 220 of the first transistor T1 may be electrically connected to the capacitor lower electrode of the first capacitor C1.

The first capacitor C1 includes a capacitor lower electrode, a capacitor dielectric layer 190, and a capacitor upper electrode 200.

For example, the first capacitor C1 may remove an insulating layer in the device isolation trench 110 and sequentially form the capacitor dielectric layer 190 and the capacitor upper electrode 200 in the trench 110. Can be.

For example, the capacitor lower electrode may be a first conductivity type well (NW) doped with the first conductivity type impurity.

The capacitor dielectric layer 190 may be an oxide film formed along a surface profile of the semiconductor substrate 100 on which the trench 110 is formed.

In particular, the capacitor dielectric layer 190 may be formed of a high dielectric material having a high dielectric constant (High K). The dielectric constant of the capacitor dielectric layer 190 may be formed of a material of 85 or more.

The capacitor dielectric layer 190 may be formed of TiO ₂ .

The capacitor dielectric layer 190 may be selectively formed only on sidewalls of the trench 110.

The capacitor upper electrode 200 may be formed of a polysilicon film formed on the semiconductor substrate 100 including the trench 110.

The first capacitor C1 may be separated from the second capacitor C2 of the neighboring second capacitor region CA2 by the insulating pattern 155 formed on the bottom surface of the trench 110.

Although not shown, the second capacitor C2 may be electrically connected to the second transistor.

That is, the charge of the first transistor T1 may be stored in the first capacitor C1, and the charge of the second transistor (not shown) may be stored in the second capacitor C2.

The first capacitor C1 and the second capacitor C2 may be symmetrically formed with respect to the insulating pattern 155 inside the trench 110.

Although not shown, a common contact may be formed on the capacitor upper electrode 200. When a bias is applied to the common contact, an inversion layer is formed on the first capacitor C1 and is a capacitor. Can be used.

The insulating pattern 155 may be formed on the bottom surface of the trench 110 to have a predetermined thickness, and may electrically separate the first capacitor C1 and the second capacitor C2.

The reliability of the device may be secured by controlling the thickness of the insulating pattern 155 and isolating neighboring capacitors.

The capacitor dielectric layer 190 may be formed of a high dielectric material on the sidewall of the trench 110.

Accordingly, the capacitance of the capacitor C1 can be increased.

Since the capacitor dielectric layer 190 is selectively formed only on the sidewall of the trench 110, a capacitor having a small area may be formed with a high capacitance.

As a result, the LDRAM device can be miniaturized and highly integrated, and the reliability of the device can be improved.

2 to 10, a method of forming a capacitor for 1TRAM of an LDI element will be described in detail.

Referring to FIG. 2, an isolation layer 160 is formed on the semiconductor substrate 100 by an STI process, and an active area AA and a field area FA are defined.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type or n-type impurities.

The active area AA may be an area in which one transistor 1 Tr and one capacitor 1 Cap are formed to form a Logic DRAM (LDRAM) of an LCD driver IC (LDI) device.

In the process of forming the device isolation layer 160, first, a pad oxide layer 130 and a pad nitride layer 140 are formed on the semiconductor substrate 100. The pad oxide layer 130 and the pad nitride layer 140 may be selectively etched by a photoresist pattern (not shown) and selectively expose the surface of the semiconductor substrate 100 corresponding to a predetermined region of the device isolation layer.

A device having a predetermined depth in the semiconductor substrate 100 by using the pad oxide layer 130 and the pad nitride layer 140 as an etching mask and performing a reactive ion etching process on the semiconductor substrate 100. The isolation trench 120 is formed.

When the isolation trench 120 is formed, a capacitor trench 110 for forming an LDRAM (Logic DRAM) of an LCD driver IC (LDI) device may be simultaneously formed in the active region AA.

For example, the capacitor trench is referred to as a first trench 110 and the device isolation trench is referred to as a second trench 120.

Thereafter, an oxide film may be gap-filled in the first trench 110 and the second trench 120 by the HDP process, and planarized by the CMP process.

Accordingly, the device isolation layer 160 may be formed in the second trench 120, and the insulating layer 150 may be gap-filled in the same manner as the device isolation layer 160 in the first trench 110.

The insulating layer 150 may be an oxide layer.

An end point of polishing during the CMP process may be the pad nitride layer 140.

Additionally, the heat treatment process by the device isolation layer 160 may be further performed.

As described above, the device isolation layer 160 may be formed on the semiconductor substrate 100, and a field region FA and an active region AA may be defined.

In addition, the insulating layer 150 may be gap-filled in the first trench 110 in which the capacitor of the LDI device is to be formed.

Thereafter, a first conductivity type well may be formed by ion implanting n-type or p-type impurities into the semiconductor substrate 100 corresponding to the active region AA to form a well region of the semiconductor substrate 100. In example embodiments, the first conductivity type well NW may be formed of an n-type impurity.

Referring to FIG. 3, the insulating layer 150 inside the first trench 110 is removed to a predetermined depth, and an insulating pattern 155 is formed.

The insulating pattern 155 may be formed to have a first height H1 based on the bottom surface of the first trench 110.

The sidewalls 115 of the first trench 110 exposed by the insulating pattern 155 may be formed to have a second height H2 greater than the first height H1.

For example, the insulating pattern 155 may be formed to a thickness of 500 ~ 900Å based on the bottom surface of the first trench 110.

The upper insulating pattern 155 forms a first photoresist pattern 10 that selectively exposes the semiconductor substrate 100 corresponding to the first trench 110.

The first photoresist pattern 10 may be formed to coat a photoresist layer on the semiconductor substrate 100 by a spin process, or to expose an upper region of the first trench 110 through a selective exposure and development process. Can be.

Then, the first photoresist pattern 10 is used as an etching mask, and an etching process is performed on the insulating layer 150 in the exposed region.

The etching process may be a wet or dry etching process.

For example, the wet etching process may selectively remove the insulating layer 150 using BHF chemical.

An etching parameter of the insulating layer 150 may be removed, and an insulating pattern 155 having a predetermined thickness may be formed in the first trench 110.

The insulating pattern 155 may separate the capacitor formed in the first trench 110 for each device in a subsequent process.

The insulating layer 150 in the first trench 110 may be selectively removed through the etching process, and the sidewall 115 of the first trench 110 may be exposed.

A change occurs depending on the density of the insulating pattern 155 remaining in the etching process of the insulating layer 150 of the first trench 110, and the thickness of the insulating pattern 155 is changed by each process change. The fluctuation may cause a large deterioration of the characteristics of the capacitor.

In this embodiment, a high dielectric constant (High-k) material may be applied to the capacitor dielectric layer to improve the process margin with respect to the thickness of the insulating pattern 155.

That is, only the thickness of the insulation pattern 155 for management sufficient for capacitor isolation can be importantly managed, so that various process variables can be fully considered.

Referring to FIG. 4, a metal layer 170 is formed on the semiconductor substrate 100 including the insulating pattern 155 and the first trench 110.

The metal layer 170 may be formed along the surfaces of the pad nitride layer 140 and the device isolation layer 160 having the same height in the field area FA.

The metal layer 170 may be formed along the surface of the first trench 110 including the insulating pattern 155 in the active region AA.

The metal layer 170 may contact the sidewall 115 of the first trench 110 exposed by the insulating pattern 155.

That is, the metal layer 170 may be formed to contact the silicon region of the semiconductor substrate 100 through the sidewall of the first trench 110.

The metal layer 170 may be formed of a titanium (Ti) layer.

Referring to FIG. 5, a heat treatment process is performed on the metal layer 170, and the silicide layer 175 is formed.

The silicide layer 175 is formed on the sidewall 115 of the first trench 110 through the heat treatment process.

That is, the silicide layer 175 is formed in a region in contact with the silicon portion through a heat treatment process for the metal layer 170.

The silicide layer 175 may be titanium silicide.

For example, the heat treatment process may be performed for 10 to 20 seconds at 700 ~ 1000 ℃ through a rapid thermal process (Rapid Thermal Process) process.

Alternatively, the heat treatment process may be performed for 30 to 60 minutes at 400 ~ 600 ℃ through a furnace (furnace) process.

Accordingly, the silicide layer 175 may be formed only on the sidewall 115 of the first trench 110 in contact with the metal layer 170.

Referring to FIG. 6, the metal layer 170 is removed.

The metal layer 170 may be selectively removed through a wet etching process.

For example, the metal layer 170 may be selectively removed using a chemical mixed with TMAH, H ₂ O ₂ and H ₂ O.

The metal layer 170 is removed, and surfaces of the pad nitride layer 140 and the device isolation layer 160 of the field area FA are exposed.

The metal layer 170 is removed, the titanium silicide layer 175 is exposed on the sidewall of the first trench 110, and the insulating pattern 155 is exposed on the bottom of the first trench 110.

Referring to FIG. 7, a thermal oxidation process of the silicide layer 175 is performed.

Through the thermal oxidation process, the silicide layer 175 may be formed of a high dielectric layer 190 having a high dielectric constant (High-k).

The high dielectric layer 190 may be formed of a TiO ₂ layer.

The thermal oxidation process may oxidize titanium silicide into a TiO ₂ film and a SiO ₂ film 180 through an annealing process in an oxygen atmosphere.

That is, the inner region of the first trench 110 may be a high dielectric layer 190 having a TiO ₂ film through the thermal oxidation process.

The TiO ₂ film is a high dielectric material having a dielectric constant of 85 or more.

The TiO ₂ film, which is the high dielectric layer 190, may be selectively formed only on the sidewall of the first trench 110 and may be used as a capacitor dielectric layer.

Meanwhile, the thickness of the high dielectric layer 190 may be adjusted by controlling the thermal oxidation process.

Referring to FIG. 8, the pad nitride layer 140, the pad oxide layer 130, and the SiO ₂ layer 180 are removed.

The pad nitride layer 140, the pad oxide layer 130, and the SiO ₂ layer 180 may be removed through a dry or wet etching process.

In this case, the insulating pattern 155 inside the first trench 110 may be protected by a separate mask (not shown).

Therefore, the device isolation layer 160 of the semiconductor substrate 100 corresponding to the field area FA is exposed.

The insulating pattern 155 and the high dielectric layer 190 of the first trench 110 corresponding to the active area AA may be exposed.

An insulating pattern 155 is formed in the lower region of the first trench 110.

Since the high dielectric constant layer 190 used as the capacitor insulating layer is formed of a high dielectric constant material, the process margin for the thickness of the insulating pattern 155 may be stably maintained.

Since the insulating pattern 155 may be formed to a sufficient thickness, the isolation of the first capacitor C1 and the second capacitor C2 formed in the first trench 110 may be stably performed in a subsequent process. I can keep it.

Referring to FIG. 9, a polysilicon layer is formed such that the first trench 110 is gap-filled and has a predetermined height on the semiconductor substrate 100.

The gate 210 may be formed in the transistor region through the selective patterning process for the polysilicon layer, and the capacitor upper electrode 200 may be formed on the capacitor regions CA1 and CA2.

In this case, the gate 210 and the capacitor upper electrode 200 may be patterned at the same time.

Referring to FIG. 10, a spacer 230 may be formed on sidewalls of the gate 210 and a source / drain region 220 may be formed in a lower region of the gate 220.

 The PMD layer 240 including the contact plug is formed on the semiconductor substrate 100 including the first transistor T1 and the first capacitor C1. The contact plug may connect the bit line wire 250 and the first transistor T1.

In an embodiment, the capacitance of the capacitor may be increased by forming the capacitor dielectric layer as a high dielectric layer.

The high dielectric layer may be selectively formed only on the sidewall of the STI trench, and the thickness thereof may be adjusted.

As a result, the capacitance of the capacitor can be stably managed and the reliability of the device can be improved.

That is, even if the capacitor area is small, the capacitance of the capacitor may be increased by the high dielectric layer.

Accordingly, the device can be miniaturized and highly integrated in LDLAM.

Since the capacitor dielectric layer is formed of a high dielectric constant material, the process margin of the insulating pattern formed under the STI trench can be greatly improved.

Accordingly, the isolation characteristics of the capacitors formed to be adjacent to each other in the STI trench can be improved.

Since the thickness of the insulating pattern may be optimized, the junction leakage of the capacitors adjacent to each other may be prevented and the reliability of the device may be improved.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a circuit diagram of a semiconductor device having one transistor and one capacitor according to an embodiment.

FIG. 2 is a cross-sectional view illustrating a structure of the semiconductor device illustrated in FIG. 1.

3 to 10 are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment.

Claims (16)

A semiconductor substrate having a first conductivity type well formed therein; A trench formed in the semiconductor substrate; An insulating pattern formed in the trench at a first height relative to the bottom surface of the trench to expose sidewalls of the trench; A high dielectric layer formed on sidewalls of the trench exposed by the insulating pattern; And And a capacitor upper electrode formed on the trench including the high dielectric layer. The method of claim 1, The high dielectric layer is a semiconductor device formed of a material having a dielectric constant of 85 or more. The method of claim 1, The high dielectric layer is a semiconductor device formed of TiO ₂ . The method of claim 1, The capacitor upper electrode is a semiconductor device formed of polysilicon. The method of claim 1, Used as a capacitor by the semiconductor substrate, the high-k dielectric layer and the capacitor upper electrode, And a transistor formed on the semiconductor substrate to be electrically connected to the capacitor. Gap-filling an oxide film in the first trench and the second trench in the semiconductor substrate and forming an isolation layer; Doping a first conductivity type impurity into the semiconductor substrate and forming a first conductivity type well; Removing the oxide layer corresponding to the first trench to a predetermined thickness and exposing sidewalls of the first trench; Forming a high dielectric layer only on sidewalls of the first trenches; And forming a capacitor upper electrode on the first trench including the high dielectric layer. The method of claim 6, The insulating pattern is formed at a first height based on the bottom surface of the trench, The trench sidewall exposed by the insulating pattern has a second height greater than the first height. The method of claim 6, The high dielectric layer is a method of manufacturing a semiconductor device is formed of a material having a dielectric constant of 85 or more. The method of claim 6, The high dielectric layer includes a material having a dielectric constant of 85 or more. The method of claim 6, The high dielectric layer is a method of manufacturing a semiconductor device formed of TiO ₂ . The method of claim 6, Forming the high dielectric layer, Forming a metal layer along sidewalls of the trench including the insulating pattern; Performing a heat treatment process on the metal layer and forming a silicide layer on sidewalls of the trench; Performing a thermal oxidation process on the silicide layer and forming a metal oxide film having a high dielectric constant. The method of claim 11, The metal layer is a method of manufacturing a semiconductor device formed of titanium (Ti). The method of claim 11, After forming the silicide layer, the metal layer is a method of manufacturing a semiconductor device comprising removing with a wet etching chemical containing TMAH, H ₂ O ₂ and H ₂ O. The method of claim 11, The metal oxide film is formed of a TiO ₂ layer, And removing the silicon oxide film formed on the TiO ₂ layer during the thermal oxidation process. The method of claim 6, The capacitor upper electrode is a semiconductor device manufacturing method formed of a polysilicon film. The method of claim 6, And forming a transistor in the semiconductor substrate corresponding to the first trench and the second trench.

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