KR20110077115A - Method for manufacturing of semiconductor device - Google Patents

Abstract

PURPOSE: A producing method of a semiconductor device is provided to selectively produce a capacitor separation insulating pattern on the bottom of a trench. CONSTITUTION: A producing method of a semiconductor device comprises the following steps: forming a first trench(110) on a semiconductor substrate(100); forming a barrier layer along to the surface profile of the semiconductor substrate; installing a barrier pattern(175) selectively exposing the bottom surface of the first trench through an etching process to the barrier layer; selectively forming an insulation pattern on the exposed bottom surface of the first trench; and removing the barrier pattern.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

The embodiment relates to a method of manufacturing a semiconductor device used in an LCD driver IC (LDI) required for driving a liquid crystal display (LCD) panel.

An LCD driver IC (LDI) is an integrated circuit (IC) that is essential for driving a liquid crystal display (LCD) panel, and refers to an integrated circuit that provides driving signals and data and interfaces with it.

Graphic random access memory (GRAM) memory, which stores data among the components of LDI, needs to be highly integrated in order to realize wide video graphics array (WVGA) high resolution that will be commercialized in the future.

When using 6T SRAM consisting of six conventional transistors, the chip size becomes larger and less competitive. Therefore, a method of miniaturizing and integrating chips is needed.

In particular, as high-density memory capacity is required for a high-performance display driver IC (DDI) structure, the memory of the SRAM structure has reached a limit in chip size shrink.

To this end, in addition to the process of forming three gate oxide films of LV (Medium Voltage), MV (Medium Voltage) and HV (High Voltage) formed in the existing LDI device, need.

Accordingly, by forming an LDRAM (Logic DRAM) composed of one capacitor in one transistor Tr in the LDI device, a memory device having a high density can be realized.

However, unlike general DRAM, it must be able to be formed at the same time as LDI, not a device for DRAM alone, so it is very difficult to make a capacitor using a deep VIA used in general DRAM.

In order to implement such a device, an oxide film serving as a capacitor of the LDRAM device is formed under the STI. However, unlike oxide growth on active regions such as LV, MV, and HV devices, the oxide layer must be formed under the trench of the STI region, making the process complicated and difficult to optimize the process. have.

The embodiment provides a method of fabricating a semiconductor device, in which an isolation layer for device isolation of capacitors adjacent to each other in an LDRAM device can be selectively formed only under the STI trench.

A method of manufacturing a semiconductor device according to an embodiment may include forming a first trench in a semiconductor substrate; Forming a barrier layer along a surface profile of the semiconductor substrate including the first trench; Forming a barrier pattern selectively exposing only a bottom surface of the first trench through an etching process on the barrier layer; Selectively forming an insulating pattern only on the bottom surface of the exposed first trench; And removing the barrier pattern.

In an embodiment, an insulating pattern for capacitor separation in the LDRAM device may be selectively formed only on the bottom surface of the trench.

Accordingly, the isolation of the capacitor elements adjacent to each other can be made stable.

In addition, since the oxide layer of the insulating pattern may be grown only on the trench bottom surface, the thickness of the insulating pattern may be optimized.

Accordingly, it is possible to prevent junction leakage of capacitors adjacent to each other and to improve the reliability of the device.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

1 is a circuit diagram of a semiconductor device for an LCD driver IC (LDI).

The LDI device may implement a logic DRAM (LDRAM) including one first transistor T1 and one first capacitor CA1.

The first capacitor CA1 may be formed using an STI trench.

FIG. 2 is a cross-sectional view illustrating a structure of the semiconductor device for LDI shown in FIG. 1.

As illustrated in FIG. 2, the first transistor T1 of the semiconductor device for LDI includes a gate 210, a spacer 230, and a source / drain 220 formed in the semiconductor substrate 100.

In the semiconductor substrate 100, an active region AA and a field region FA are defined by the device isolation layer 160.

A first conductivity type well NW doped with a first conductivity type impurity is formed in an active region of the semiconductor substrate 100.

For example, the first conductivity type impurities may be n type or p type impurities.

The first conductivity type well NW may be laid out as a first transistor area TA and a first capacitor area CA1 and CA2.

The first transistor T1 is formed in the first transistor area TA of the first conductivity type well NW.

The first capacitor CA1 electrically connected to the first transistor T1 is formed in the first capacitor region CA1 of the first conductivity type well NW.

The source / drain region of the first transistor T1 may be electrically connected to the capacitor lower electrode of the first capacitor CA1.

The first capacitor CA1 includes a capacitor lower electrode, a capacitor insulating layer 190, and a capacitor upper electrode 200.

For example, the first capacitor CA1 may remove an insulating layer in the device isolation trench 110 and sequentially form the capacitor insulating layer 190 and the capacitor upper electrode 200 in the trench 110. can do.

For example, the capacitor lower electrode may be a first conductivity type well (NW) doped with the first conductivity type impurity. The capacitor insulating layer 190 may be an oxide film formed along a surface profile of the semiconductor substrate 100 on which the trench 110 is formed. The capacitor upper electrode 200 may be formed of a polysilicon film formed on the semiconductor substrate 100 including the trench 110.

The first capacitor CA1 may be separated from the second capacitor C2 of the neighboring second capacitor region CA2 by the insulating pattern 180 formed on the bottom surface of the trench 110.

Although not shown, the second capacitor C2 may be electrically connected to the second transistor.

That is, the charge of the first transistor T1 may be stored in the first capacitor CA1, and the charge of the second transistor (not shown) may be stored in the second capacitor C2.

The first capacitor CA1 and the second capacitor C2 may be symmetrically formed with respect to the insulation pattern 180 inside the trench 110.

Although not shown, a common contact may be formed on the capacitor upper electrode 200. When a bias is applied to the common contact, an inversion layer is formed on the first capacitor CA1 and is a capacitor. Can be used.

The insulating pattern 180 may be formed on the bottom surface of the trench 110 to have a predetermined thickness, and may electrically separate the first capacitor CA1 and the second capacitor C2.

The reliability of the device may be secured by controlling the thickness of the insulating pattern 180 and isolating neighboring capacitors.

The thickness of the insulating pattern 180 may be optimized and the junction leakage of the first capacitor CA1 and the second capacitor C2 may be prevented.

That is, since the trench 110 corresponding to the separation region of the first capacitor CA1 and the second capacitor C2 becomes narrower toward the bottom, the thickness of the insulating pattern 180 inside the trench 110 is controlled. By doing so, junction leakage can be prevented.

3 to 11, a method of optimizing the insulating pattern for the 1TRAM of the LDI device will be described in detail.

Referring to FIG. 3, an isolation layer 160 is formed on the semiconductor substrate 100 by an STI process, and an active region AA and a field region B are defined.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type or n-type impurities.

The active area AA may be an area in which one transistor 1 Tr and one capacitor 1 Cap are formed to form a Logic DRAM (LDRAM) of an LCD driver IC (LDI) device.

In the process of forming the device isolation layer 160, first, a pad oxide layer 130 and a pad nitride layer 140 are formed on the semiconductor substrate 100. The pad oxide layer 130 and the pad nitride layer 140 may be selectively etched by a photoresist pattern (not shown) and selectively expose the surface of the semiconductor substrate 100 corresponding to a predetermined region of the device isolation layer.

A trench for device isolation having a predetermined depth in the semiconductor substrate 100 by using the pad oxide layer 130 and the pad nitride layer 140 as an etching mask and performing a reactive ion etching process on the semiconductor substrate. Form 120.

When the isolation trench 120 is formed, a capacitor trench 110 for forming an LDRAM (Logic DRAM) of an LCD driver IC (LDI) device may be simultaneously formed in the active region AA.

For example, the capacitor trench is referred to as a first trench 110 and the element isolation trench is referred to as a second trench 120.

Thereafter, an oxide film may be gap-filled in the first trench 110 and the second trench 120 by the HDP process, and planarized by the CMP process.

Accordingly, the device isolation layer 160 may be formed in the second trench 120, and the insulating layer 150 may be gap-filled in the same manner as the device isolation layer 160 in the first trench 110.

The insulating layer 150 may be an oxide layer.

An end point of polishing during the CMP process may be the pad nitride layer 140.

Additionally, the heat treatment process by the device isolation layer 160 may be further performed.

As described above, the device isolation layer 160 may be formed on the semiconductor substrate 100, and a field region FA and an active region AA may be defined.

In addition, an oxide layer may be gap-filled in the first trench 110 in which the capacitor of the LDI device is to be formed.

Thereafter, a first conductivity type well NW may be formed by ion implanting n-type or p-type impurities into a semiconductor substrate corresponding to the active region to form a well region of the semiconductor substrate 100 (see FIG. 2). )

Referring to FIG. 4, the insulating layer 150 inside the first trench 110 may be removed and the first trench 110 may be exposed.

A first photoresist pattern 10 is formed on the semiconductor substrate 100 to selectively expose the semiconductor substrate 100 corresponding to the first trench 110.

The first photoresist pattern 10 may be formed to coat a photoresist layer on the semiconductor substrate 100 by a spin process, or to expose an upper region of the first trench 110 through a selective exposure and development process. Can be.

In addition, the first photoresist pattern 10 is used as an etching mask, and an etching process is performed on the exposed oxide layer.

The etching process may be a wet or dry etching process.

An oxide layer inside the first trench 110 may be selectively removed through the etching process, and the side and bottom surfaces of the first trench 110 may be exposed.

Referring to FIG. 5, the pad oxide layer 130 and the pad nitride layer 140 on the semiconductor substrate 100 are removed.

The pad oxide layer 130 and the pad nitride layer 140 may be removed through a wet or dry etching process.

When the pad oxide layer 130 and the pad nitride layer 140 are removed, the device isolation layer 160 may also be removed to a predetermined thickness.

Accordingly, the first trench 110 for the capacitor may be exposed, and the device isolation layer 160 may be formed in the second trench 120.

Referring to FIG. 6, a barrier layer 170 is formed along a surface profile of the semiconductor substrate 100 including the device isolation layer 160 and the first trench 110.

The barrier layer 170 may be formed of a nitride film.

The barrier layer 170 may be formed on the surface of the semiconductor substrate 100 through a PE-CVD process.

Since the barrier layer 170 is formed through a PE-CVD process, the step coverage of the nitride layer may vary from location to location.

In other words, the barrier layer 170 corresponding to the upper surface area of the semiconductor substrate 100 may be formed to have a first thickness D1. In addition, the barrier layer 170 corresponding to the bottom surface of the first trench 110 may be formed to have a second thickness D2 smaller than the first thickness D1.

For example, the first thickness D11 of the barrier layer 170 may be 80 to 150 kPa, and the second thickness D2 of the barrier layer 170 may be 30 to 70 kPa.

This is because the step coverage of the barrier layer 170 formed through the PE-CVD process is reduced, so that the barrier layer 170 of the upper surface of the semiconductor substrate 100 and the bottom of the first trench 110 may be formed. The thickness can be formed differently.

In particular, the thickness of the barrier layer 170 may be different within the first trench 110. That is, since the deposition rate at the sidewall of the first trench 110 is faster than the bottom surface, the thickness at the sidewall of the first trench 110 may be thicker than the bottom surface.

Referring to FIG. 7, a second photoresist pattern 20 is formed on the semiconductor substrate 100 to cover the device isolation layer 160.

The second photoresist pattern 20 is formed on the barrier layer 170 corresponding to the upper region of the device isolation layer 160. The barrier layer 170 corresponding to the first trench 110 may be selectively exposed in the second photoresist pattern 20.

Referring to FIGS. 7 and 8, the second photoresist pattern 20 is used as an etching mask and a selective etching process is performed on the barrier layer 170.

The barrier layer 170 in an exposed state may be selectively removed through a selective etching process using the second photoresist pattern 20 as an etching mask.

In this case, the thickness of the barrier layer 170 on the upper surface of the semiconductor substrate 100 is different from the thickness of the barrier layer 170 on the bottom surface of the first trench 110.

Therefore, while the barrier layer 170 corresponding to the bottom surface of the first trench 110 is removed, the barrier layer 170 of the upper surface of the semiconductor substrate 100 and the sidewall of the first trench 110 may be Some remain, and the barrier pattern 175 may be formed.

Thereafter, the second photoresist pattern 20 may be removed.

Accordingly, the barrier pattern 175 remains on the sidewall of the first trench 110 and the entire upper region of the semiconductor substrate 100, and only the bottom surface of the first trench 110 may be exposed.

Referring to FIG. 9, an insulating pattern 180 is formed on the bottom surface of the first trench 110.

The insulating pattern 180 may be formed through a thermal oxidation process on the semiconductor substrate 100 including the barrier layer 170 and the first trench 110.

The insulating pattern 180 may be silicon oxide formed by reacting silicon (Si) and oxygen (O ₂ ) corresponding to the bottom surface of the first trench 110 exposed in an oxygen and hydrogen atmosphere.

Only the semiconductor substrate 100 corresponding to the bottom surface of the first trench 110 is selectively exposed by the barrier pattern 175, and the remaining area is covered by the barrier pattern 175.

Therefore, the insulating pattern 180 may be selectively formed only on the bottom surface of the first trench 110.

Through the thermal oxidation process, the thickness of the insulating pattern 180 formed on the bottom surface of the first trench 110 may be constantly adjusted.

Since the insulating pattern 180 is selectively formed on the bottom surface of the first trench 110 as the oxide layer grows, the thickness of the oxide layer may be stably formed.

Accordingly, it is possible to easily manage the capacitance of the capacitor formed in the subsequent process.

Referring to FIG. 10, the barrier pattern 175 is removed.

The barrier pattern 175 may be selectively removed through a wet or dry etching process.

The barrier pattern 175 may be removed, and the upper surface of the semiconductor substrate 100 and the device isolation layer 160 may be exposed.

The barrier pattern 175 may be removed and sidewalls of the first trench 110 may be exposed.

Since the insulating pattern 180 is selectively formed only on the bottom surface of the first trench 110, and the thickness of the insulating pattern 180 can be selectively adjusted, the insulating pattern 180 is formed inside the first trench 110. It may serve as isolation of the first capacitor CA1 and the second capacitor C2.

Afterwards, referring to FIG. 11, an oxide film may be deposited inside the first trench 110 to form the capacitor insulating layer 190.

For example, the capacitor insulating layer 190 may have a thickness thinner than that of the insulating pattern 180. The thickness ratio of the capacitor insulating layer 190 and the insulating pattern 180 may be 1: 5 to 20.

In addition, the polysilicon layer may be formed to have the first trench 110 gap-filled and have a predetermined height on the semiconductor substrate 100. The gate 210 may be formed in the transistor region through the selective patterning process for the polysilicon layer, and the capacitor upper electrode 200 may be formed on the capacitor regions CA1 and CA2.

In this case, the gate 210 and the capacitor upper electrode 200 may be patterned at the same time.

Referring back to FIG. 2, spacers 230 may be formed on sidewalls of the gate 210, and source / drain regions 220 may be formed in lower regions of the gate 220.

A silicide layer may be selectively formed on surfaces of the gate 220, the source / drain region 220, and the capacitor upper electrode 200.

The PMD layer 240 including the contact plug is formed on the semiconductor substrate 100 including the first transistor T1 and the first capacitor CA1. The contact plug may connect the bit line wire 250 and the first transistor T1.

In an embodiment, since the insulating pattern for capacitor separation is selectively formed only on the bottom surface of the trench, isolation of the capacitor elements adjacent to each other may be stably achieved.

In addition, since the oxide layer of the insulating pattern may be grown only on the bottom surface of the trench, the thickness of the insulating pattern may be optimized.

Accordingly, it is possible to prevent junction leakage of capacitors adjacent to each other and to improve the reliability of the device.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a circuit diagram of a semiconductor device having one transistor and one capacitor according to an embodiment.

FIG. 2 is a cross-sectional view illustrating a structure of the semiconductor device illustrated in FIG. 1.

3 to 11 are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the embodiment.

Claims (10)

Forming a first trench in the semiconductor substrate; Forming a barrier layer along a surface profile of the semiconductor substrate including the first trench; Forming a barrier pattern selectively exposing only a bottom surface of the first trench through an etching process on the barrier layer; Selectively forming an insulating pattern only on the bottom surface of the exposed first trench; And Removing the barrier pattern. The method of claim 1, The barrier layer is a semiconductor device manufacturing method, characterized in that formed by a nitride film through a PE-CVD process. The method of claim 1, The barrier layer may be formed to have a first thickness on an upper surface of the semiconductor substrate and sidewalls of the trench, and a second thickness on the bottom surface of the first trench. . The method of claim 3, Forming the barrier pattern, Forming a photoresist pattern to expose an upper region of the barrier layer corresponding to the first trench; Etching the barrier layer by the photoresist pattern; And manufacturing the semiconductor substrate corresponding to the bottom surface of the first trench. The method of claim 1, The insulating pattern is a method of manufacturing a semiconductor device, characterized in that formed by an oxide film through a thermal oxidation process. The method of claim 1, A method of manufacturing a semiconductor device, characterized in that a dielectric film and a polysilicon film are formed on the first trench including the insulating pattern. The method of claim 1, The semiconductor substrate includes a conductive well doped with n-type or p-type impurities, And forming the first trench in the conductive well. The method of claim 7, wherein And forming a transistor in the semiconductor substrate corresponding to the first trench and the second trench. The method of claim 1, Forming a device isolation trench through an STI process to define an active region in the semiconductor substrate; And the first trench is formed at the same time when forming the device isolation trench. 10. The method of claim 9, Gap-filling an oxide film in the first trench and the isolation trench; Selectively removing the oxide film of the first trench and exposing the first trench.

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