KR20110079281A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A semiconductor device and a manufacturing method thereof are provided to make an etching profile with a regular thickness and width by using a pyramid etching made of a self stop and to perform a stable function in a buried insulating film. CONSTITUTION: A substrate(110) includes the first trench(T1) and the second trench(T2). An element isolation film(220) is formed in the second trench. A groove is formed in a lower part of the first trench. A buried insulation film(120) is formed in the groove of a lower part of the first trench. A capacitor insulating layer is formed in the substrate of a sidewall of the first trench located at an upper side of the buried insulation film. An upper electrode(140) fills up the first trench.

Description

Semiconductor device and its manufacturing method {SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME}

The embodiment relates to a semiconductor device used in an LCD driver IC (LDI) required for driving a liquid crystal display (LCD) panel.

An LCD driver IC (LDI) is a driver IC (Integrated Circuit) essential for driving a liquid crystal display (LCD) panel, and refers to an integrated circuit that provides driving signals and data and interfaces.

Graphic random access memory (GRAM) memory, which stores data among the components of LDI, needs to be highly integrated in order to realize wide video graphics array (WVGA) high resolution that will be commercialized in the future.

When using 6T SRAM consisting of six conventional transistors, the chip size becomes larger and less competitive. Therefore, a method of miniaturizing and integrating chips is needed.

In particular, as high-density memory capacity is required for a high-performance display driver IC (DDI) structure, the memory of the SRAM structure has reached a limit in chip size shrink.

To this end, in addition to the process of forming three gate oxide films of LV (Medium Voltage), MV (Medium Voltage) and HV (High Voltage) formed in the existing LDI device, need.

Accordingly, by forming an LDRAM (Logic DRAM) composed of one capacitor in one transistor Tr in the LDI device, a memory device having a high density can be realized.

According to the prior art, a capacitor in a 1T RAM composed of one capacitor in one transistor Tr has various shapes.

On the other hand, there is a method of manufacturing a capacitor (capacitor) using a buried oxide of various shapes.

However, a capacitor using a buried oxide film according to the prior art generates a problem in leakage depending on the shape or thickness of the buried oxide film which may electrically insulate the capacitor from the substrate. Let's do it.

In addition, according to the related art, when the thickness of the buried oxide is thin or narrow, electrons on the buried oxide film surface may create a leakage path along the buried oxide film.

Embodiments provide a semiconductor device and a method of manufacturing the same, which can effectively control the shape and depth of buried oxide in a 1T RAM DDI product using buried oxide.

In an embodiment, a semiconductor device may include: a substrate including a first trench and a second trench; An isolation layer formed in the second trench; A groove formed under the first trench; A buried insulating film formed in a groove under the first trench; A capacitor insulating layer formed on the substrate on the sidewalls of the first trench above the buried insulating film; And an upper electrode filling the first trench.

In addition, the method of manufacturing a semiconductor device according to the embodiment may include forming a first trench and a second trench in a substrate; Gap-filling an insulating film in the first trench and the second trench; Planarizing the insulating layer to form a separation insulating layer in the first trench and an isolation layer in the second trench; Removing the isolation insulating film; Forming a hard mask on sidewalls of the first trenches from which the isolation insulating layer is removed; Forming a groove in the substrate under the first trench using the hard mask; Forming a buried insulating film under the first trench in which the groove is formed; Removing the hard mask and forming a capacitor insulating layer on a substrate of the first trench sidewalls above the buried insulating layer; And forming an upper electrode filling the first trench.

According to the semiconductor device and the manufacturing method thereof according to the embodiment, an etch profile having a constant thickness and width is formed by using a pyramid etch consisting of a self stop in forming a capacitor of a 1T RAM. It can make a stable function in the buried insulating film through this.

In addition, according to the embodiment, it is easy to etch depth control of a substrate for forming a buried insulating film by implementing a 1T RAM capacitor using self stop wet etch, and a sidewall hard mask. ) Has the advantage that the loss (loss).

Hereinafter, a semiconductor device and a method of manufacturing the same according to embodiments will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

(Example)

1 is a cross-sectional view of a semiconductor device according to an embodiment.

In an embodiment, a semiconductor device may include a substrate 110 including a first trench T1 and a second trench T2, an isolation layer 220 formed in the second trench T2, and the first trench. T1) a groove formed in the lower portion, a buried insulating film 120 formed in the groove under the first trench, and a capacitor insulating layer 130 formed in the substrate on the sidewall of the first trench T1 above the buried insulating film 120. And an upper electrode 140 filling the first trench T1.

In an embodiment, the buried insulating film 120 may be narrower from the top to the bottom. The buried insulating film 120 of the embodiment can be easily adjusted in thickness or width so that it does not act as a liquid source.

The buried insulating layer 120 may include a slope. For example, the buried insulating layer 120 may include a pyramid-shaped slope.

In example embodiments, the semiconductor substrate 110 may include a conductive well (not shown) doped with n-type or p-type impurities, and the first trench may be formed in the conductive well.

The embodiment may further include a capacitor ion implantation region (not shown) formed on the sidewall of the first trench T1.

The embodiment may be a semiconductor device for an LCD driver IC (LDI).

The semiconductor device for LDI according to the embodiment may include a multi chip and a logic DRAM (LDRAM).

For example, an embodiment may include a low voltage (LV) transistor (TL), a middle voltage (TM) transistor (TM), and a high voltage (TH) transistor (TH).

In addition, the LDI device of the embodiment may be implemented as an LDRAM (logic DRAM) including one first transistor TR1 and one capacitor.

The first transistor TR1 of the LDI semiconductor device may include a gate, a spacer, and a source / drain formed on the semiconductor substrate 110.

The semiconductor substrate 110 may include an active region and a field region.

A first conductivity type doped with a first conductivity type impurity may be formed in the active region of the semiconductor substrate 110. For example, the first conductivity type impurities may be n type or p type impurities.

The first conductivity type well may be laid out as a first transistor region and a capacitor region.

The first transistor TR1 may be formed in the first transistor region of the first conductivity type well.

A capacitor electrically connected to the first transistor TR1 may be formed in the capacitor region of the first conductivity type well.

The source / drain region of the first transistor TR1 may be electrically connected to the lower electrode of the capacitor C.

The capacitor C may include a capacitor lower electrode, a capacitor insulating layer 130, and a capacitor upper electrode 140.

For example, the capacitor C removes an insulating layer inside the first trench T1 for device isolation, and removes the capacitor insulating layer 130 and the capacitor upper electrode 140 inside the first trench T1. It can be formed sequentially.

For example, the capacitor lower electrode may be a first conductivity type well doped with the first conductivity type impurity. The capacitor insulating layer 130 may be an oxide film formed along a surface profile of the semiconductor substrate 110 on which the first trenches T1 are formed, but is not limited thereto. The capacitor upper electrode 140 may be formed of a polysilicon film formed on the semiconductor substrate 110 including the first trench T1, but is not limited thereto.

The capacitor C may be separated from the second capacitor (not shown) of the neighboring second capacitor region by a predetermined insulating pattern (not shown) formed on the bottom surface of the first trench T1. The second capacitor may be electrically connected to a second transistor (not shown).

That is, the charge of the first transistor TR1 may be stored in the capacitor, and the charge of the second transistor may be stored in the second capacitor.

The capacitor and the second capacitor may be symmetrically formed based on an insulation pattern inside the first trench T1.

A common contact may be formed on the capacitor upper electrode 140. When a bias is applied to the common contact, an inversion layer may be formed on the capacitor and used as a capacitor.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described with reference to FIGS. 2 through 12. Hereinafter, the manufacturing method for the capacitor C of 1 RAM will be described mainly.

First, as shown in FIG. 2, a first trench T1 and a second trench T2 (see FIG. 1) are formed in the substrate 110, and an insulating film is formed in the first trench T1 and the second trench T2. A gap fill is performed to planarize the insulating layer, so that the isolation insulating layer 122a is formed in the first trench T1, and the device isolation layer 220 is formed in the second trench T2.

For example, the device isolation layer 220 may be formed on the semiconductor substrate 110 by an STI process to define an active region and a field region.

The semiconductor substrate 110 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type or n-type impurities.

The active region may be a region in which one first transistor TR1 and one capacitor C are formed to form a logic DRAM (LDRAM) of an LCD driver IC (LDI) device.

In the process of forming the device isolation layer 220 and the isolation insulating layer 122a, a pad oxide layer 112 and a pad nitride layer 115 are formed on the semiconductor substrate 110. The pad oxide film 112 and the pad nitride film 115 are selectively etched by a photoresist pattern (not shown) and selectively surface the surface of the semiconductor substrate 110 corresponding to a predetermined region of the device isolation film and the isolation insulating film 122a. May be exposed.

Subsequently, the pad oxide layer 112 and the pad nitride layer 115 are used as an etching mask, and the semiconductor substrate 110 may be etched, for example, reactive ion etching. A first trench T1 and a second trench T2 having a depth are formed.

When the second trench T2 is formed, a first trench T1 for forming an LDRAM (Logic DRAM) of an LCD driver IC (LDI) device may be simultaneously formed in an active region.

For example, in an embodiment, the capacitor trench may be referred to as a first trench T1, and the device isolation trench may be referred to as a second trench T2.

Thereafter, an insulating film, for example, an oxide film is gap-filled in the first trenches T1 and the second trenches T2 by a gap fill process, for example, an HDP process, and planarized by a planarization process, for example, a CMP process. Can be.

Accordingly, an isolation layer 220 may be formed in the second trench T2, and an oxide layer may be gap-filled in the same shape as the isolation layer 220 in the first trench T1 to form the isolation insulation layer 122a. have.

In the planarization process, for example, the CMP process, the polishing end point may be the pad nitride layer 115. In addition, a heat treatment process may be further performed on the device isolation layer 220.

As described above, the device isolation layer 220 may be formed on the semiconductor substrate 110, and a field region and an active region may be defined.

In addition, the isolation insulating layer 122a may be formed in the first trench T1 in which the capacitor of the LDI device is to be formed.

Thereafter, a first conductivity type well may be formed by ion implanting n-type or p-type impurities into a semiconductor substrate corresponding to the active region to form a well region of the semiconductor substrate 110.

Next, as shown in FIG. 3, a first mask pattern 310 is formed on the pad insulating layer 115, and as shown in FIG. 4, the first mask pattern 310 is used as an etching mask. Remove

For example, the first mask pattern 310 may be a photoresist pattern. The photoresist layer may be coated on the semiconductor substrate 110 by a spin process, and the first trench may be subjected to selective exposure and development processes. T1) can be formed to expose the top.

Thereafter, the isolation insulating layer 122a may be etched using the first mask pattern 310 as an etch mask. The etching of the isolation insulating layer 122a may be dry etching, for example, reactive ion etching, but is not limited thereto.

Next, as shown in FIG. 5, a hard mask 320 is formed on sidewalls of the first trench T1.

For example, the forming of the hard mask 320 may include forming an oxide hard mask 322 on the sidewall of the first trench, and forming a nitride hard mask 324 on the oxide hard mask 322. It may comprise the step of forming.

Next, as shown in FIG. 6, a lower end of the hard mask 320 may be removed to expose the substrate under the first trench. For example, the bottom surface of the hard mask 320 may be removed by dry etching to expose the substrate under the first trench.

Next, as shown in FIG. 7, the first substrate G1 is formed by partially removing the exposed substrate by primary wet etching.

For example, the first wet etching may partially remove the exposed substrate by the first wet etching to form a first groove G1 including a slope in a pyramid form.

For example, the first wet etching may be etched in a direction of (111) on the surface of an exposed substrate, for example, a silicon sub (Si sub) by performing a dip treatment in a KOH solution. The first groove G1 including) may be formed.

According to the embodiment, by forming a groove including a slope in a pyramid shape, an etch profile having a predetermined thickness and width can be made, and a buried insulating film having stable performance can be realized in a subsequent buried insulating film. .

Next, as shown in FIG. 8, the second wet etching may be performed after the first wet etching. For example, the second wet etching may be a pyramid etch consisting of a self stop. For example, the secondary wet etching may be performed through pyramid etching using a DHF solution, but is not limited thereto.

According to the embodiment, the second wet etch may be performed using the DHF solution to reduce the roughness of the surface of the substrate, and thus the second groove G2 may be formed.

According to the embodiment, by forming a groove including a slope in a pyramid shape, an etch profile having a predetermined thickness and width can be made, and a buried insulating film having stable performance can be realized in a subsequent buried insulating film. .

In addition, according to the embodiment, it is easy to etch depth control of a substrate for forming a buried insulating film by implementing a 1T RAM capacitor using self stop wet etch, and a sidewall hard mask. ) Has the advantage that the loss (loss).

Accordingly, according to the embodiment, an etch profile having a constant thickness and width may be made by using a pyramid etch consisting of a self stop in forming a capacitor of a 1T RAM. Through the buried insulating film can perform a stable function.

Next, as shown in FIG. 9, a buried insulating film 120 is formed under the first trench in which the groove is formed. For example, the buried insulating film 120 may be formed through a wet oxidation process.

In an embodiment, the buried insulating film 120 may be narrower from the top to the bottom.

The buried insulating layer 120 may include a slope. For example, the buried insulating layer 120 may include a pyramid-shaped slope.

Next, as shown in FIG. 10, the hard mask 320 is removed, and as shown in FIG. 11, the capacitor insulating layer 130 is formed on the substrate of the first trench sidewall above the buried insulating layer 120.

In this embodiment, a capacitor ion implantation layer (not shown) may be formed using the pad nitride layer 115 and the buried insulating layer 120 as a mask. For example, a capacitor ion implantation layer may be formed on the sidewall substrate of the first trench T1 by tilt ion implantation.

The pad nitride layer 115 may be removed before the capacitor insulating layer 130 is formed. For example, the pad nitride layer 115 may be removed by wet etching including phosphoric acid, but is not limited thereto. In this case, a process of removing the pad oxide layer 112 may be performed.

The capacitor insulating layer 130 may form the capacitor insulating layer 130 by a thermal oxidation process. In this case, the capacitor insulating layer 130 may be formed on the upper portion of the substrate in addition to the sidewalls of the first trenches T1.

Next, as shown in FIG. 12, the upper electrode 140 may be formed to fill the first trench T1. For example, the upper electrode 140 may be formed by filling and patterning the first trenches T1 with polysilicon.

For example, the first trench T1 may be gap-filled, a polysilicon layer may be formed on the semiconductor substrate 110 to have a predetermined height, and a gate may be gated in the transistor region through a selective patterning process for the polysilicon layer. The capacitor upper electrode 140 may be formed on the capacitor region.

In this case, the first transistor gate and the capacitor upper electrode 140 may be patterned at the same time, but are not limited thereto.

Subsequently, spacers may be formed on sidewalls of the first transistor gate, and source / drain regions may be formed in the lower region of the gate.

That is, in the exemplary embodiment, the first transistor TR1 may be electrically connected to the capacitor C including the substrate 110, the capacitor insulating layer 130, and the upper electrode 140.

For example, the first transistor TR1 may be formed in the semiconductor substrate between the first trench T1 and the second trench T2.

Thereafter, an interlayer insulating layer 150 including a contact plug 160 is formed on the semiconductor substrate 110 including the first transistor TR1 and the capacitor C, for example, a PMD layer. The contact plug 160 may electrically connect the bit line wire 170 and the first transistor TR1.

In the semiconductor device according to the embodiment, a high-capacity multi DDI chip is a device having various driving ranges of LV, MV, and HV, and uses 1T RAM for chip size shrink and high capacity. Applicable

According to the semiconductor device and the manufacturing method thereof according to the embodiment, an etch profile having a constant thickness and width is formed by using a pyramid etch consisting of a self stop in forming a capacitor of a 1T RAM. It can make a stable function in the buried insulating film through this.

In addition, according to the embodiment, it is easy to etch depth control of a substrate for forming a buried insulating film by implementing a 1T RAM capacitor using self stop wet etch, and a sidewall hard mask. ) Has the advantage that the loss (loss).

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a cross-sectional view of a semiconductor device according to an embodiment.

2 to 12 are cross-sectional views of a semiconductor device in accordance with an embodiment.

Claims (16)

A substrate comprising a first trench and a second trench; An isolation layer formed in the second trench; A groove formed under the first trench; A buried insulating film formed in a groove under the first trench; A capacitor insulating layer formed on the substrate on the sidewalls of the first trench above the buried insulating film; And And an upper electrode filling the first trench. The method according to claim 1, The buried insulating film, A semiconductor device in which the width becomes narrower from the top to the bottom. The method according to claim 1, The buried insulating film, Semiconductor device comprising a slope (slope). The method of claim 3, The buried insulating film is Semiconductor device comprising a pyramid-shaped slope. The method according to claim 1, The semiconductor substrate includes a conductive well doped with n-type or p-type impurities, And a first trench formed in the conductive well. The method according to claim 1, And a capacitor ion implantation region formed on the sidewalls of the first trenches. Forming a first trench and a second trench in the substrate; Gap-filling an insulating film in the first trench and the second trench; Planarizing the insulating layer to form a separation insulating layer in the first trench and an isolation layer in the second trench; Removing the isolation insulating film; Forming a hard mask on sidewalls of the first trenches from which the isolation insulating layer is removed; Forming a groove in the substrate under the first trench using the hard mask; Forming a buried insulating film under the first trench in which the groove is formed; Removing the hard mask and forming a capacitor insulating layer on the substrate on the first trench sidewalls above the buried insulating film; And And forming an upper electrode filling the first trench. 8. The method of claim 7, Forming a hard mask on the sidewalls of the first trench, Forming an oxide film hard mask on the sidewalls of the first trenches above the remaining insulating film; And Forming a nitride film hard mask on the oxide film hard mask; manufacturing method of a semiconductor device comprising a. 8. The method of claim 7, Forming a groove in the substrate under the first trench using the hard mask, Removing a lower end of the hard mask to expose a substrate under the first trench; Forming a groove by partially removing the exposed substrate by primary wet etching. The method of claim 9, The first wet etching is And partially removing the exposed substrate by primary wet etching to form a groove including a slope in a pyramid form. The method of claim 9, The first wet etching is A method of manufacturing a semiconductor device by etching in the (111) direction on the surface of the exposed substrate by performing a dip treatment in a KOH solution to form a groove (slope). The method of claim 9, And partially removing the exposed substrate by first wet etching to form a groove, and then performing second wet etching. 13. The method of claim 12, The second wet etching is A method of manufacturing a semiconductor device, which is a pyramid etch consisting of a self stop. The method of claim 13, The second wet etching is A method of manufacturing a semiconductor device for proceeding pyramid etching using the DHF solution. 8. The method of claim 7, The semiconductor substrate includes a conductive well doped with n-type or p-type impurities, And a first trench formed in the conductive well. 8. The method of claim 7, After the step of forming the buried insulating film, And forming a capacitor ion implantation region on the sidewalls of the first trenches.

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