KR20110076174A - Method for manufacturing of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to perform isolation of an adjacent capacitor device stably, by forming an insulation pattern for capacitor isolation only on the bottom of a trench. CONSTITUTION: A trench is formed on a semiconductor substrate. An insulation film is formed so that the inside of the trench is gap-filled. A first insulation pattern is formed through a dry etching process for an insulation film. The first insulation pattern has a first thickness. A second insulation pattern(140) is formed through a wet etching process for the trench including the first insulation pattern. The second insulation pattern has a second thickness. The second thickness is smaller than the first thickness.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

The embodiment relates to a semiconductor device used in an LCD driver IC (LDI) required for driving a liquid crystal display (LCD) panel.

An LCD driver IC (LDI) is an integrated circuit (IC) that is essential for driving a liquid crystal display (LCD) panel, and refers to an integrated circuit that provides driving signals and data and interfaces with it.

Graphic random access memory (GRAM) memory, which stores data among the components of LDI, needs to be highly integrated in order to realize wide video graphics array (WVGA) high resolution that will be commercialized in the future.

When using 6T SRAM consisting of six conventional transistors, the chip size becomes larger and less competitive. Therefore, a method of miniaturizing and integrating chips is needed.

In particular, as high-density memory capacity is required for a high-performance display driver IC (DDI) structure, the memory of the SRAM structure has reached a limit in chip size shrink.

To this end, in addition to the process of forming three gate oxide films of LV (Medium Voltage), MV (Medium Voltage) and HV (High Voltage) formed in the existing LDI device, need.

Accordingly, by forming an LDRAM (Logic DRAM) composed of one capacitor in one transistor Tr in the LDI device, a memory device having a high density can be realized.

However, unlike general DRAM, it must be able to be formed at the same time as LDI, not a device for DRAM alone, so it is very difficult to make a capacitor using a deep VIA used in general DRAM.

In order to implement such a device, an oxide film serving as a capacitor of the LDRAM device is formed under the STI.

However, unlike oxide growth on active regions such as LV, MV, and HV devices, the oxide layer must be formed under the trench of the STI region, making the process complicated and difficult to optimize the process. have.

The embodiment provides a method of manufacturing a semiconductor device capable of forming a GRAM into 1T RAM in an LDRAM device.

A method of manufacturing a semiconductor device according to an embodiment includes forming a trench in a semiconductor substrate; Forming an oxide layer to gap-fill the inside of the trench; Forming a first insulating pattern having a first thickness based on a bottom surface of the trench through a dry etching process on the oxide layer; And forming a second insulating pattern having a second thickness smaller than the first thickness through a wet etching process for the trench including the first insulating pattern.

In an embodiment, since the insulating pattern for capacitor isolation is selectively formed only on the bottom surface of the trench in the LDRAM device, isolation of the adjacent capacitor devices may be stably achieved.

Accordingly, it is possible to prevent junction leakage of capacitors adjacent to each other and to improve the reliability of the device.

 The insulating pattern may be formed by sequentially controlling a dry etching process and a wet etching process.

In particular, it is possible to improve plasma damage and uniformity of the silicon substrate generated by performing the dry etching in a single process.

In addition, since the lattice structure of the exposed surface of the semiconductor substrate has a constant orientation, it is possible to prevent leakage of the currency and improve the reliability of the device.

Hereinafter, a method of manufacturing a semiconductor device according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

1 is a circuit diagram of a 1T RAM in an LDRAM of an LCD driver IC (LDI) element.

The LDI device may implement 1T RAM in an LDRAM (logic DRAM) including one first transistor T1 and one first capacitor C1.

The first capacitor C1 may be formed using a trench in the STI region.

Accordingly, a device having a specific capacitor value at the same chip size and a 1T RAM device having high density and high resolution characteristics may be implemented.

FIG. 2 is a cross-sectional view illustrating a structure of a 1T RAM semiconductor device of the LDI device shown in FIG. 1.

As illustrated in FIG. 2, the first transistor T1 of the 1T RAM semiconductor device includes a gate 170, a spacer 180, and a source / drain 190 formed on the semiconductor substrate 100.

In the semiconductor substrate 100, an active region AA and a field region FA are defined by an isolation layer 105.

A first conductivity type well NW doped with a first conductivity type impurity is formed in the active region AA of the semiconductor substrate 100.

For example, the first conductivity type impurities may be n type or p type impurities.

The first conductivity type well NW may be laid out as a first transistor region TA and first and second capacitor regions CA1 and CA2.

The first transistor T1 is formed in the first transistor area TA of the first conductivity type well NW.

The first capacitor C1 electrically connected to the first transistor T1 is formed in the first capacitor region C1 of the first conductivity type well NW.

The source / drain 190 of the first transistor T1 may be electrically connected to the capacitor lower electrode of the first capacitor C1.

The first conductivity type well NW may be used as a capacitor lower electrode of the first capacitor C1.

The first capacitor C1 includes a capacitor lower electrode, a capacitor insulating layer 150, and a capacitor upper electrode 160.

For example, the first capacitor C1 removes an insulating layer inside the isolation trench 110 and sequentially forms the capacitor insulating layer 150 and the capacitor upper electrode 160 in the trench 110. Can be formed.

For example, the capacitor lower electrode may be a first conductivity type well (NW) doped with the first conductivity type impurity.

The capacitor insulating layer 150 may be an oxide film formed along a surface profile of the semiconductor substrate 100 on which the trench 110 is formed.

The capacitor upper electrode 160 may be formed of a polysilicon film formed on the semiconductor substrate 100 including the trench 110.

The first capacitor C1 may be separated from the second capacitor C2 of the neighboring second capacitor region CA2 by the second insulating pattern 140 formed on the bottom surface of the trench 110.

Although not shown, the second capacitor C2 may be electrically connected to the second transistor.

That is, the charge of the first transistor T1 may be stored in the first capacitor C1, and the charge of the second transistor (not shown) may be stored in the second capacitor C2.

The first capacitor C1 and the second capacitor C2 may be symmetrically formed based on the second insulating pattern 140 inside the trench 110.

Although not shown, a common contact may be formed on the capacitor upper electrode 160. When a bias is applied to the common contact, an inversion layer is formed on the first capacitor C1 and is a capacitor. Can be used.

The second insulating pattern 140 may be formed on the bottom surface of the trench 110 to have a predetermined thickness, and may electrically separate the first capacitor C1 and the second capacitor C2.

The reliability of the device may be secured by controlling the thickness of the second insulating pattern 140 and isolating capacitors adjacent to each other.

The thickness of the second insulating pattern 140 may be optimized and the junction leakage of the first capacitor C1 and the second capacitor C2 may be prevented.

That is, since the trench 110 corresponding to the separation region of the first capacitor C1 and the second capacitor C2 becomes narrower toward the lower portion, the thickness of the second insulating pattern 140 inside the trench 110 is reduced. By controlling the junction junction can be prevented.

While forming the optimal thickness of the second insulating pattern 140, the uniformity of the capacitor insulating layer 150 may be improved and the capacitor characteristics may be improved.

That is, the surface profile of the first conductivity type well NW of the semiconductor substrate 100 used as the capacitor lower electrode is improved, and the capacitor insulating layer 150 formed on the capacitor lower electrode has a predetermined thickness. Can have

Accordingly, it is possible to improve the leakage current of the capacitor and to improve the characteristics of the device.

3 to 7, a method of forming a 1T RAM semiconductor device of an LDI device will be described in detail.

Referring to FIG. 3, the trench 110 is formed in the semiconductor substrate 100 by an STI process, and the insulating film 120 is gap-filled.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type or n-type impurities.

The trench 110 may be formed at the same time as the STI process for forming the device isolation layer is performed.

Although not shown, in order to form the trench 110, a pad oxide film and a pad nitride film are formed on the semiconductor substrate 100. The pad oxide layer and the pad nitride layer may be selectively etched by a photoresist pattern (not shown) to selectively expose the surface of the semiconductor substrate 100 corresponding to the device isolation layer planned region and the trench planned region.

The pad oxide layer and the pad nitride layer are used as an etching mask, and the semiconductor substrate 100 is selectively etched to form a device isolation trench (see FIG. 2) and the trench 110.

That is, when the isolation trench is formed, a capacitor trench 110 for forming LDRAM (Logic DRAM) of an LCD driver IC (LDI) device may be simultaneously formed in the active region AA.

Thereafter, the insulating film 120 may be gap-filled in the isolation trench and the trench 110 by the HDP process and planarized by the CMP process.

For example, the insulating layer 120 may be an oxide layer.

Accordingly, the device isolation layer 105 may be formed in the device isolation trench, and the insulating layer 120 may be gap-filled in the trench 110 in the same manner as the device isolation layer 105.

In addition, a heat treatment process may be further performed on the device isolation layer 105.

As described above, the device isolation layer 105 may be formed on the semiconductor substrate 100, and a field region FA and an active region AA may be defined. (See Figure 2)

In addition, the insulating layer 120 may be gap-filled in the trench 110 in which the capacitor of the LDI device is to be formed.

In order to form the well region of the semiconductor substrate 100, a first conductivity type well NW may be formed by ion implanting n-type or p-type impurities into the semiconductor substrate 100 corresponding to the active region AA. . In example embodiments, the first conductivity type well may be doped with n-type impurities.

Thereafter, the pad oxide layer and the pad nitride layer may be removed, and the device isolation layer 105 and the oxide layer 110 of the semiconductor substrate 100 may be exposed.

Referring to FIG. 4, a first etching process is performed on the insulating layer 120, and a first insulating pattern 130 is formed in the trench 110.

The first insulating pattern 130 may be removed to a predetermined thickness and selectively expose sidewalls of the trench 110.

The first etching process may be a dry etching process. The primary etching process may be a reactive ion etch process.

The first insulating pattern 130 may be formed to have a first thickness T1 based on the bottom surface of the trench 110.

For example, the primary etching process may be performed until the thickness of the first insulating pattern 130 has a thickness of 2000 to 2500 Å.

The exposed sidewalls of the trench 110 may be damaged by the plasma generated during the first etching process.

That is, roughness may be generated on the sidewall of the trench 110 by the first etching process.

This roughness deforms the lattice structure of the silicon of the semiconductor substrate 100 exposed through the trench 110 sidewalls. That is, the lattice structure of the silicon corresponding to the sidewall of the trench 110 subjected to plasma damage is deformed in the 111 direction to generate roughness.

If the silicon lattice structure is deformed, the current may cause leakage current in the 1T RAM device formed in the trench 110 and deteriorate the characteristics of the device.

Referring to FIG. 5, a second etching process is performed on the trench 110 including the first insulating pattern 130, and a second insulating pattern 140 is formed.

The first insulating pattern 130 may be removed to a predetermined thickness through the second etching process, and the exposed area of the sidewall of the trench 110 may be exposed more than the first etching process.

The second insulating pattern 140 may be formed to have a predetermined thickness on the bottom surface of the trench 110 and may electrically separate capacitors adjacent to each other.

The secondary etching process may be a wet etching process.

The secondary etching process may be a wet etching process using diluted HF chemicals.

In the secondary etching process, the ratio of DI water and DHF is used in a concentration ratio of 100: 1 to 200: 1, and may be performed for 10 to 30 minutes using a batch type equipment.

The second insulating pattern 140 may be formed to have a second thickness T2 smaller than the first thickness T1 based on the bottom surface of the trench 110.

For example, the secondary etching process may be performed when the thickness of the second insulating pattern 140 has a thickness of 800 to 1200 Å.

Roughness generated on the sidewalls of the trench 110 may be removed during the secondary etching process.

Accordingly, sidewalls of the trench 110 may have a uniform surface.

That is, during the secondary etching process, the DHF chemical may thinly remove the exposed sidewall of the trench 110. In particular, the lattice structure in the 111 direction may be decomposed to be reduced to the lattice structure in the 100 direction from the silicon surface exposed through the sidewall of the trench 110.

Therefore, the surface of the semiconductor substrate 100 exposed through the sidewall of the trench 110 may be chemically stabilized.

 In addition, through the reduction of dry etching target and DHF treatment, which is a wet etching process in which uniformity is better than dry etching, the uniformity of 10% or more when using only dry etching is controlled to within 5%. can do.

Accordingly, plasma damage and uniformity may be improved at the same time.

After the secondary etching process, a surface treatment process may be further performed.

The surface treatment process may be performed using Tetramethyl Ammonium Hydroxide (TMAH) chemical.

The surface treatment process is adjusted to a concentration of 4 ~ 10% TMAH chemical in DI water, can be performed for 1 to 10 minutes.

Accordingly, the roughness formed on the exposed sidewall of the trench 110 may be removed, and the surface roughness at the sidewall of the trench 110 may be flattened.

In an embodiment, the second insulating pattern 140 may be controlled to have an optimal thickness inside the trench 110.

In particular, the uniformity of the second insulating pattern 140 of the STI region may be controlled using the DHF chemical.

In addition, the characteristics of the device may be improved by removing the surface lattice structure of the semiconductor substrate 100 in 100 directions.

The roughness may be further improved by further performing a surface treatment process using TMAH chemical on the exposed sidewall of the trench 110.

Referring to FIG. 6, an oxide film may be deposited inside the trench 110 to form the capacitor insulating layer 150.

For example, the capacitor insulating layer 150 may have a thickness thinner than that of the second insulating pattern 130. The thickness ratio of the capacitor insulating layer 150 and the second insulating pattern 130 may be 1: 5 to 20.

In addition, the trench 110 may be gap-filled to form a polysilicon layer on the semiconductor substrate 100 to have a predetermined height.

The gate 170 may be formed in the transistor region through the selective patterning process for the polysilicon layer, and the capacitor upper electrode 160 may be formed on the capacitor regions CA1 and CA2.

In this case, the gate 170 and the capacitor upper electrode 160 may be patterned at the same time.

Referring to FIG. 7, spacers 180 may be formed on sidewalls of the gate 170, and source / drain regions 190 may be formed in lower regions of the gate 220.

For example, the source / drain 190 may be formed of p-type impurities.

When the spacer 180 is formed on the sidewall of the gate 170, the spacer may also be formed on the sidewall of the capacitor upper electrode 160.

The silicide layer 200 may be formed on the surfaces of the gate 170 and the source / drain 190.

The silicide layer 210 may be selectively formed on the surface of the capacitor upper electrode 160.

 The PMD layer 220 including the contact plug is formed on the semiconductor substrate 100 including the first transistor T1 and the first capacitor C1. The contact plug may connect the bit line wire 230 and the first transistor T1.

In an embodiment, since the insulating pattern for capacitor isolation is selectively formed only on the bottom surface of the device isolation trench, isolation of the capacitor elements adjacent to each other can be stably achieved.

The insulating pattern may be formed by sequentially controlling a dry etching process and a wet etching process.

In particular, the plasma damage and uniformity of the silicon substrate generated by performing the dry etching in a single process may be improved.

In addition, since the lattice structure of the exposed surface of the semiconductor substrate has a constant orientation, it is possible to prevent leakage of the currency and improve the reliability of the device.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a circuit diagram of a semiconductor device having one transistor and one capacitor according to an embodiment.

FIG. 2 is a cross-sectional view illustrating a structure of the semiconductor device illustrated in FIG. 1.

3 to 7 are cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment.

Claims (13)

Forming a trench in the semiconductor substrate; Forming an insulating layer to gap-fill the inside of the trench; Forming a first insulating pattern having a first thickness based on a bottom surface of the trench through a dry etching process on the insulating layer; And And forming a second insulating pattern having a second thickness smaller than the first thickness through a wet etching process for the trench including the first insulating pattern. The method of claim 1, And a capacitor dielectric layer and a capacitor upper electrode formed on the trench including the insulating pattern. The method of claim 2, The semiconductor substrate includes a conductive well doped with n-type or p-type impurities, The trench is formed in the conductive well, and the conductive well is used as a capacitor lower electrode. The method of claim 1, And a transistor formed on one side of the trench of the semiconductor substrate. The method of claim 1, The dry etching process is a method of manufacturing a semiconductor device comprising a reactive ion etching process. The method of claim 1, The wet etching process is a method of manufacturing a semiconductor device comprising using the DHF chemical. The method of claim 1, And forming a lattice structure of the surface of the semiconductor substrate exposed through the trench in the 1,0,0 direction through the wet etching process. The method of claim 1, After the dry etching process further comprising the step of performing a surface treatment process using a TMAH chemical. The method of claim 1, After the wet etching process further comprising the step of performing a surface treatment process using a TMAH chemical. The method of claim 1, The second insulating pattern is a method of manufacturing a semiconductor device comprising a thickness of 800 ~ 1200Å. The method of claim 2, The ratio of the thickness of the capacitor dielectric layer and the second insulating pattern is a manufacturing method of a semiconductor device comprising a 1: 7 ~ 20. The method of claim 1, The semiconductor substrate further includes an isolation layer defining an active region, And forming a trench and an insulating layer when the device isolation layer is formed. The method of claim 1, And the insulating film is formed of an oxide film.

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