KR20110077117A - Method for manufacturing of semiconductor device - Google Patents

Abstract

PURPOSE: A producing method of a semiconductor device is provided to stably isolate neighboring capacitor devices by selectively forming a capacitor separation insulating pattern on the bottom of a trench. CONSTITUTION: A producing method of a semiconductor device comprises the following steps: forming a first trench on a semiconductor substrate(100); forming a barrier layer along to the surface profile of the semiconductor substrate; forming a barrier pattern(175) selectively exposing the bottom of the first trench by an etching process for the barrier layer; forming a recess trench after etching the semiconductor substrate; forming an insulating pattern(180) on the recess trench; and removing the barrier pattern.

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING OF SEMICONDUCTOR DEVICE}

The embodiment relates to a semiconductor device used in an LCD driver IC (LDI) required for driving a liquid crystal display (LCD) panel.

An LCD driver IC (LDI) is an integrated circuit (IC) that is essential for driving a liquid crystal display (LCD) panel, and refers to an integrated circuit that provides driving signals and data and interfaces with it.

Graphic random access memory (GRAM) memory, which stores data among the components of LDI, needs to be highly integrated in order to realize wide video graphics array (WVGA) high resolution that will be commercialized in the future.

When using 6T SRAM consisting of six conventional transistors, the chip size becomes larger and less competitive. Therefore, a method of miniaturizing and integrating chips is needed.

In particular, as high-density memory capacity is required for a high-performance display driver IC (DDI) structure, the memory of the SRAM structure has reached a limit in chip size shrink.

To this end, in addition to the process of forming three gate oxide films of LV (Medium Voltage), MV (Medium Voltage) and HV (High Voltage) formed in the existing LDI device, need.

Accordingly, by forming an LDRAM (Logic DRAM) composed of one capacitor in one transistor Tr in the LDI device, a memory device having a high density can be realized.

However, unlike general DRAM, it must be able to be formed at the same time as LDI, not a device for DRAM alone, so it is very difficult to make a capacitor using a deep VIA used in general DRAM.

In order to implement such a device, an oxide film serving as a capacitor of the LDRAM device is formed under the STI.

However, unlike oxide growth on active regions such as LV, MV, and HV devices, the oxide layer must be formed under the trench of the STI region, making the process complicated and difficult to optimize the process. have.

The embodiment provides a method of manufacturing a semiconductor device capable of controlling the thickness of an insulating film for device isolation of capacitors adjacent to each other in an LDRAM device.

A method of manufacturing a semiconductor device according to an embodiment includes: gap-filling an oxide film in a first trench and a second trench in a semiconductor substrate and forming a device isolation film; Removing the oxide layer corresponding to the first trench and exposing the first trench; Forming a barrier layer along a surface profile of the semiconductor substrate including the device isolation layer and the first trench; Forming a barrier pattern selectively exposing only a bottom surface of the first trench through an etching process on the barrier layer; Etching the semiconductor substrate to a first depth through the exposed bottom surface of the first trench and forming a recess trench; Forming an insulating pattern in the recess trench; And removing the barrier pattern.

In an embodiment, since the insulating pattern for capacitor isolation is selectively formed only on the bottom surface of the trench in the LDRAM device, isolation of the adjacent capacitor devices may be stably achieved.

In addition, since the oxide layer of the insulating pattern may be grown only on the bottom surface of the trench, the thickness of the insulating pattern may be optimized.

The trench may be a device isolation trench formed through an STI process.

A recess trench extends below the trench, and an insulating pattern may be selectively formed only inside the recess trench.

Therefore, the thickness and width of the insulating pattern can be stabilized and the reliability of the device can be improved.

Accordingly, it is possible to prevent junction leakage of capacitors adjacent to each other and to improve the reliability of the device.

Hereinafter, a semiconductor device and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where it is described as being formed "on / under" of each layer, it is understood that the phase is formed directly or indirectly through another layer. It includes everything.

1 is a circuit diagram of a semiconductor device for an LCD driver IC (LDI).

The LDI device may implement a logic DRAM (LDRAM) including one first transistor T1 and one first capacitor C1.

The first capacitor C1 may be formed using a trench in the STI region.

FIG. 2 is a cross-sectional view illustrating a structure of the semiconductor device for LDI shown in FIG. 1.

As illustrated in FIG. 2, the first transistor T1 of the semiconductor device for LDI includes a gate 210, a spacer 230, and a source / drain 220 formed in the semiconductor substrate 100.

The semiconductor substrate 100 has an active region and a field region defined by the device isolation layer 160.

A first conductivity type well NW doped with a first conductivity type impurity is formed in the active region AA of the semiconductor substrate 100.

For example, the first conductivity type impurities may be n type or p type impurities.

The first conductivity type well NW may be laid out as a first transistor region TA and first and second capacitor regions CA1 and CA2.

The first transistor T1 is formed in the first transistor area TA of the first conductivity type well NW.

The first capacitor C1 electrically connected to the first transistor T1 is formed in the first capacitor region C1 of the first conductivity type well NW.

The source / drain region 220 of the first transistor T1 may be electrically connected to the capacitor lower electrode of the first capacitor C1.

The first capacitor C1 includes a capacitor lower electrode, a capacitor insulating layer 190, and a capacitor upper electrode 200.

For example, the first capacitor C1 removes an insulating layer in the device isolation trench 110 and sequentially forms the capacitor insulating layer 190 and the capacitor upper electrode 200 in the trench 110. can do.

For example, the capacitor lower electrode may be a first conductivity type well (NW) doped with the first conductivity type impurity. The capacitor insulating layer 190 may be an oxide film formed along a surface profile of the semiconductor substrate 100 on which the trench 110 is formed. The capacitor upper electrode 200 may be formed of a polysilicon film formed on the semiconductor substrate 100 including the trench 110.

The first capacitor C1 may be separated from the second capacitor C2 of the neighboring second capacitor region CA2 by the insulating pattern 180 formed on the bottom surface of the trench 110.

Although not shown, the second capacitor C2 may be electrically connected to the second transistor.

That is, the charge of the first transistor T1 may be stored in the first capacitor C1, and the charge of the second transistor (not shown) may be stored in the second capacitor C2.

The first capacitor C1 and the second capacitor C2 may be symmetrically formed with respect to the insulating pattern 180 inside the trench 110.

Although not shown, a common contact may be formed on the capacitor upper electrode 200. When a bias is applied to the common contact, an inversion layer is formed on the first capacitor C1 and is a capacitor. Can be used.

The insulating pattern 180 may be formed on the bottom surface of the trench 110 to have a predetermined thickness, and may electrically separate the first capacitor C1 and the second capacitor C2.

The reliability of the device may be secured by controlling the thickness of the insulating pattern 180 and isolating neighboring capacitors.

The thickness of the insulating pattern 180 may be optimized and the junction leakage of the first capacitor C1 and the second capacitor C2 may be prevented.

That is, since the trench 110 corresponding to the separation region of the first capacitor C1 and the second capacitor C2 becomes narrower toward the lower portion, the thickness of the insulating pattern 180 inside the trench 110 is controlled. By doing so, junction leakage can be prevented.

3 to 13, a method of optimizing the insulating pattern for the 1TRAM of the LDI device will be described in detail.

Referring to FIG. 3, the device isolation layer 160 is formed on the semiconductor substrate 100 by an STI process, and an active area AA and a field area FA are defined.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type or n-type impurities.

The active region A may be a region in which one transistor 1 Tr and one capacitor 1 Cap are formed to form a Logic DRAM (LDRAM) of an LCD driver IC (LDI) device.

In the process of forming the device isolation layer 160, first, a pad oxide layer 130 and a pad nitride layer 140 are formed on the semiconductor substrate 100. The pad oxide layer 130 and the pad nitride layer 140 may be selectively etched by a photoresist pattern (not shown) and selectively expose the surface of the semiconductor substrate 100 corresponding to a predetermined region of the device isolation layer.

A device having a predetermined depth in the semiconductor substrate 100 by using the pad oxide layer 130 and the pad nitride layer 140 as an etching mask and performing a reactive ion etching process on the semiconductor substrate 100. The isolation trench 120 is formed.

When the isolation trench 120 is formed, a capacitor trench 110 for forming an LDRAM (Logic DRAM) of an LCD driver IC (LDI) device may be simultaneously formed in the active region AA.

For example, the capacitor trench is referred to as a first trench 110 and the device isolation trench is referred to as a second trench 120.

Thereafter, an insulating film may be gap-filled in the first trench 110 and the second trench 120 by the HDP process, and planarized by the CMP process.

The insulating layer gap-filled in the first trench 110 and the second trench 120 may be an oxide layer.

Accordingly, the device isolation layer 160 may be formed in the second trench 120, and the insulating layer 150 may be gap-filled in the same manner as the device isolation layer 160 in the first trench 110.

An end point of polishing during the CMP process may be the pad nitride layer 140.

Additionally, the heat treatment process by the device isolation layer 160 may be further performed.

As described above, the device isolation layer 160 may be formed on the semiconductor substrate 100, and a field region FA and an active region AA may be defined.

In addition, the insulating layer 150 may be gap-filled in the first trench 110 in which the capacitor of the LDI device is to be formed.

Thereafter, the first conductivity type well NW may be formed by ion implanting n-type or p-type impurities into the semiconductor substrate 100 corresponding to the active region AA to form the well region of the semiconductor substrate 100. (See Figure 2)

Referring to FIG. 4, an oxide layer inside the first trench 110 may be removed and the first trench 110 may be exposed.

A first photoresist pattern 10 is formed on the semiconductor substrate 100 to selectively expose the semiconductor substrate 100 corresponding to the first trench 110.

The first photoresist pattern 10 may be formed to coat a photoresist layer on the semiconductor substrate 100 by a spin process, or to expose an upper region of the first trench 110 through a selective exposure and development process. Can be.

In addition, the first photoresist pattern 10 is used as an etching mask, and an etching process is performed on the exposed oxide layer.

The etching process may be a wet or dry etching process.

An oxide layer inside the first trench 110 may be selectively removed through the etching process, and the side and bottom surfaces of the first trench 110 may be exposed.

Referring to FIG. 5, the pad oxide layer 130 and the pad nitride layer 140 on the semiconductor substrate 100 are removed.

The pad oxide layer 130 and the pad nitride layer 140 may be removed through a wet or dry etching process.

When the pad oxide layer 130 and the pad nitride layer 140 are removed, the device isolation layer 160 may also be removed to a predetermined thickness.

The device isolation layer 160 may have the same surface height as the surface of the semiconductor substrate 100.

Alternatively, all of the pad oxide layer 130 and the pad nitride layer 140 may be removed through the planarization process of the device isolation layer 160, and the device isolation layer 160 may be formed in the second trench 120. have.

Accordingly, the first trench 110 for the capacitor may be exposed, and the device isolation layer 160 may be formed in the second trench 120.

Referring to FIG. 6, a barrier layer 170 is formed along a surface profile of the semiconductor substrate 100 including the device isolation layer 160 and the first trench 110.

That is, the barrier layer 170 may be formed along the surface of the semiconductor substrate 100 including the device isolation layer 160 and the side and bottom surfaces of the first trench 110.

The barrier layer 170 may be formed of a nitride film through a CVD process.

The barrier layer 170 may be formed to a thickness of 30 ~ 150Å.

Referring to FIG. 7, a seed photoresist pattern 21 is formed on the semiconductor substrate 100 to selectively expose the first trench 110.

The seed photoresist pattern 21 may apply a photoresist film on the semiconductor substrate 100 by spin coating, and expose the barrier layer 170 corresponding to the first trench 110 through an exposure and development process. You can.

Referring to FIG. 8, a reflow process is performed on the seed photoresist pattern 21 to form a second photoresist pattern 20.

The second photoresist pattern 20 may be reflowed to cover sidewalls of the barrier layer 170, and may selectively expose only the barrier layer 170 corresponding to the bottom surface of the first trench 110. .

The reflow process may be performed for 1 to 10 minutes at a temperature of 100 to 300 ° C. to form the second photoresist pattern 20.

That is, the seed photoresist pattern 21 is annealed, and the seed photoresist pattern 21 flows to the barrier layer 170 corresponding to the sidewall of the first trench 110. To cover the sidewalls of the first trench 110.

Accordingly, only the bottom of the first trench 110 may be selectively exposed by the second photoresist pattern 20.

9 and 10, a first etching process using the second photoresist pattern 20 as an etching mask is performed.

The first etching process may be an etching process for the barrier layer 170 exposed by the second photoresist pattern 20.

The first etching process may be a front surface etching process on the barrier layer 170.

Since the second photoresist pattern 20 is used as an etching mask, only the barrier layer 170 corresponding to the bottom surface of the first trench 110 may be selectively etched, and the barrier pattern 175 may be formed. have.

The semiconductor substrate 100 corresponding to the bottom surface of the first trench 110 may be exposed by the barrier pattern 175.

The barrier pattern 175 may remain in the form of a spacer on the sidewall of the first trench 110, and may protect the sidewall of the first trench 110 from an etching process.

Referring to FIG. 11, a secondary etching process using the barrier pattern 175 and the second photoresist pattern 20 as an etching mask is performed.

The secondary etching process may be a process of etching the semiconductor substrate 100 corresponding to the bottom surface of the first trench 110 exposed by the second photoresist pattern 20 and the barrier pattern 175. have.

The semiconductor substrate 100 corresponding to the bottom surface of the first trench 110 may be etched to a first depth D1 by the second etching process to form a recess trench 115.

In other words, the recess trench 115 may extend into the lower portion of the first trench 110.

The recess trench 115 may extend to a predetermined depth in the first trench 110, and may control the depth and the width according to the control of the etching process of the secondary etching process.

That is, although not shown, the width of the recess trench 115 may be formed to extend in a horizontal direction than the width of the first trench 110.

Meanwhile, when the recess trench 115 is formed, a polymer residue 30 is generated according to the etching of the semiconductor substrate 100, and the polymer residue 30 is formed on a sidewall of the recess trench 115. Can be formed.

Thereafter, the second photoresist pattern 20 may be removed through a general strip process.

Referring to FIG. 12, the polymer residue 30 may be removed and the side and bottom surfaces of the recess trench 115 may be exposed.

The polymer residue 30 may be removed through a third etching process.

The third etching process may be performed using DHF chemical.

For example, the tertiary etching process may be performed by using a DHF chemical and a thermal oxide etch target of 50 to 100 Pa. The ratio of the concentration of DHF to the DI water may be 100 to 200: 1.

HCL and O ₃ can be used to proceed the surface treatment process continuously.

Accordingly, the polymer residue 30 of the sidewalls of the recess trench 115 may be removed, and the semiconductor substrate 100 corresponding to the side and bottom surfaces of the recess trench 115 may be exposed.

The barrier pattern 175 may remain on the sidewall of the first trench 110 and the entire upper region of the semiconductor substrate 100, and only side and bottom surfaces of the recess trench 115 may be selectively exposed.

Sidewalls of the recess trench 115 extending below the first trench 110 may have a first depth D1 based on the bottom surface of the first trench 110.

That is, the depth of the first trench 110 and the recess trench 115 may have a depth deeper than that of the second trench 120 in which the device isolation layer 160 is formed.

Referring to FIG. 13, an insulating pattern 180 is formed in the recess trench 115.

The insulating pattern 180 may be formed through a thermal oxidation process on the semiconductor substrate 100 including the barrier pattern 175, the first trench 110, and the recess trench 115.

In the thermal oxidation process, an annealing process may be performed in an oxygen atmosphere, and an insulation pattern 180 may be formed in the recess trench 115.

The insulating pattern 180 may be silicon oxide formed by reacting silicon (Si) and oxygen (O ₂ ) corresponding to side and bottom surfaces of the recess trench 115 exposed in an oxygen and hydrogen atmosphere.

Only the semiconductor substrate 100 corresponding to the sidewalls and the bottom surface of the recess trench 110 may be selectively exposed by the barrier pattern 175, and the remaining region may cover the barrier pattern 175.

Therefore, the insulating pattern 180 may be selectively formed only in the recess trench 115.

The insulating pattern 180 may be formed to have the same thickness as the first depth D1. The insulating pattern may be formed to a thickness thicker than the first depth.

Since the insulating pattern 180 may be formed through the bottom and side surfaces of the recess trench 115, the width and thickness of the insulating pattern 180 may be constantly adjusted.

Accordingly, the thickness of the oxide film forming the insulating pattern 180 may be stably formed.

It is possible to easily manage the capacitance of the capacitor formed by the subsequent process.

Referring to FIG. 14, the barrier pattern 175 is removed.

The barrier pattern 175 may be selectively removed through a wet or dry etching process.

The barrier pattern 175 may be removed, and the upper surface of the semiconductor substrate 100 and the device isolation layer 160 may be exposed.

The barrier pattern 175 may be removed and sidewalls of the first trench 110 may be exposed.

The insulating pattern 180 is selectively formed only in the recess trench 115 corresponding to the lower region of the first trench 110.

Since the thickness and width of the insulating pattern 180 may be selectively adjusted, the first capacitor C1 and the second capacitor C2 formed in the first trench 110 may be subsequently formed. have.

Afterwards, referring to FIG. 15, an oxide film may be deposited inside the first trench 110 to form the capacitor insulating layer 190.

For example, the capacitor insulating layer 190 may have a thickness thinner than that of the insulating pattern 180. The thickness ratio of the capacitor insulating layer 190 and the insulating pattern 180 may be 1: 5 to 20.

In addition, the polysilicon layer may be formed to have the first trench 110 gap-filled and have a predetermined height on the semiconductor substrate 100.

The gate 210 may be formed in the transistor region through the selective patterning process for the polysilicon layer, and the capacitor upper electrode 200 may be formed on the capacitor regions CA1 and CA2.

In this case, the gate 210 and the capacitor upper electrode 200 may be patterned at the same time.

Referring back to FIG. 2, spacers 230 may be formed on sidewalls of the gate 210, and source / drain regions 220 may be formed in lower regions of the gate 220.

A silicide layer may be formed on the surface of the gate 210 and the surface of the source / drain region 220. A silicide layer may also be formed on the surface of the capacitor upper electrode 200.

 The PMD layer 240 including the contact plug is formed on the semiconductor substrate 100 including the first transistor T1 and the first capacitor C1. The contact plug may connect the bit line wire 250 and the first transistor T1.

In an embodiment, since the insulating pattern for capacitor isolation is selectively formed only on the bottom surface of the device isolation trench, isolation of the capacitor elements adjacent to each other can be stably achieved.

In addition, since the oxide layer of the insulating pattern may be grown only in the recess trench extending from the lower portion of the trench, the thickness and width of the insulating pattern may be optimized.

Accordingly, it is possible to prevent junction leakage of capacitors adjacent to each other and to improve the reliability of the device.

The present invention is not limited to the described embodiments and drawings, and various other embodiments are possible within the scope of the claims.

1 is a circuit diagram of a semiconductor device having one transistor and one capacitor according to an embodiment.

FIG. 2 is a cross-sectional view illustrating a structure of the semiconductor device illustrated in FIG. 1.

3 to 15 are cross-sectional views illustrating a process of manufacturing a semiconductor device according to the embodiment.

Claims (13)

Forming a first trench in the semiconductor substrate; Forming a barrier layer along a surface profile of the semiconductor substrate including the first trench; Forming a barrier pattern selectively exposing only a bottom surface of the first trench through an etching process on the barrier layer; Etching the semiconductor substrate to a first depth through the exposed bottom surface of the first trench and forming a recess trench; Forming an insulating pattern in the recess trench; And Removing the barrier pattern. The method of claim 1, Forming the barrier pattern, Forming a seed photoresist pattern on the semiconductor substrate to expose the barrier layer of the first trench; Forming a second photoresist pattern such that the barrier layer corresponding to the sidewall of the first trench is covered by a reflow process with respect to the seed photoresist pattern; And And using the second photoresist pattern as an etching mask and selectively removing the barrier layer formed on the bottom surface of the first trench. The method of claim 1, The reflow process is a semiconductor device manufacturing method comprising the proceeding at a temperature of 100 ~ 300 ℃. The method of claim 2, The recess trench is formed by using the barrier pattern as an etching mask and etching the bottom surface of the exposed first trench to a first depth. 5. The method of claim 4, The horizontal width of the bottom surface of the first trench is a first width, the horizontal width of the bottom surface of the recess trench is formed with a second width wider than the first width. 5. The method of claim 4, When forming the recess trench, a polymer residue is formed on the side and bottom of the recess trench, The method of manufacturing a semiconductor device comprising removing the polymer residue through a chemical process. The method of claim 6, Wherein the polymer residue is removed by DHF chemicals. The method of claim 6, Removing the polymer residue, and further comprising the step of performing a surface treatment process using HCl and O ₃ gas. The method of claim 1, The insulating pattern is a method of manufacturing a semiconductor device, characterized in that formed by an oxide film through a thermal oxidation process. The method of claim 1, A method of manufacturing a semiconductor device, characterized in that a dielectric film and a polysilicon film are formed on the first trench including the insulating pattern. The method of claim 1, The semiconductor substrate includes a conductive well doped with n-type or p-type impurities, And forming the first trench in the conductive well. The method of claim 1, And forming a transistor in the semiconductor substrate corresponding to the first trench and the second trench. The method of claim 1, Wherein the first trenches are formed at the same time when forming a device isolation trench in the semiconductor substrate, Gap-filling an oxide film in the first trench and the isolation trench to form an insulating film and an isolation film; Selectively removing the oxide film corresponding to the first trench and exposing the first trench.

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