KR20110074377A - Tft array substrate and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A TFT array substrate and a method for manufacturing the same are provided to reduce the production costs by using transparent conductive films which do not use indium. CONSTITUTION: A gate line(12c) and a data line(20b) are formed on a substrate. The gate line and the data line are arranged in order to define pixel area. A TFT(Thin Film Transistor) is formed on an intersection area in which the gate line and the data line is crossed. A pixel electrode(28a) is connected to the drain electrode of the TFT. The pixel electrode is arranged in the pixel region. The pixel electrode is formed with a transparent conductive film in which indium is not contained.

Description

Thin film transistor array substrate and its manufacturing method {TFT array substrate and Method for manufacturing the same}

The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a thin film transistor array substrate for a liquid crystal display device and a manufacturing method thereof.

Usually, a liquid crystal display device displays an image by adjusting the light transmittance of a liquid crystal having dielectric anisotropy using an electric field. In the liquid crystal display, a color filter substrate on which a color filter array is formed and a thin film transistor substrate on which a thin film transistor array is formed are bonded to each other with a liquid crystal interposed therebetween.

The thin film transistor array substrate includes a thin film transistor and a pixel electrode formed in each cell region defined by the intersection of the gate line and the data line on the substrate. A thin film transistor (hereinafter referred to as TFT) supplies a data signal from the data line to the pixel electrode in response to the gate signal from the gate line. The pixel electrode formed of the transparent conductive layer supplies the data signal from the TFT to drive the liquid crystal. The liquid crystal is rotated according to the electric field formed by the data signal of the pixel electrode and the common voltage of the common electrode, thereby adjusting grayscale. In this case, the common electrode is supplied with a common voltage which is a reference when driving the liquid crystal, and may be formed on any one of the thin film transistor array substrate and the color filter array substrate.

In this case, the pixel electrode is formed using a transparent conductive layer such as indium thin oxide (ITO) or indium zinc oxide (IZO).

However, as the demand for the liquid crystal display device has recently increased, the cost is rising due to the depletion of indium, which is a material of the pixel electrode, and thus the manufacturing cost is being reduced.

Accordingly, in order to meet the demand for reducing manufacturing costs, a method of forming a pixel electrode of a thin film transistor array substrate included in a liquid crystal display using a low cost material has been studied.

An object of the present invention for solving the above problems is to provide a thin film transistor array substrate and a manufacturing method thereof that can reduce the manufacturing cost.

A thin film transistor array substrate according to the present invention for achieving the above object is formed on the substrate, the gate line and data line arranged to cross each other to define a pixel region, and the portion where the gate line and the data line intersect And a pixel electrode connected to the thin film transistor and a drain electrode of the thin film transistor, and arranged in the pixel region, wherein the pixel electrode is formed of a transparent conductive film containing no indium.

The semiconductor device may further include a common electrode disposed alternately with the pixel electrode in the pixel region to generate a transverse electric field, and formed of a transparent conductive film containing no indium.

According to an aspect of the present invention, a method of manufacturing a thin film transistor array substrate includes forming a gate line and a gate electrode on a substrate, and forming a gate insulating film on the substrate on which the gate line and the gate electrode are formed. Forming a data line, a source, and a drain electrode on the substrate on which the gate insulating film is formed; forming a pixel electrode in contact with the drain electrode by using a transparent conductive film containing no indium component; Forming a protective film on the formed substrate, and forming a common electrode on the protective film using a transparent conductive film containing no indium component.

According to an aspect of the present invention, a method of manufacturing a thin film transistor array substrate includes forming a gate line and a gate electrode on a substrate, and forming a gate insulating film on the substrate on which the gate line and the gate electrode are formed. Forming a data line, a source, and a drain electrode on the substrate on which the gate insulating layer is formed; forming a passivation layer on the substrate on which the data line, the source, and drain electrodes are formed; and exposing the drain electrode on the passivation layer. Forming a contact hole, and forming a pixel electrode contacting the drain electrode through the contact hole by using a transparent conductive film not including an indium component.

The pixel electrode and the common electrode

It is formed of any one selected from the group consisting of Al doped ZnO (ZAO), Ga doped ZnO (ZGO), Zinc Oxide (ZnO), Zinc Tin Oxide (ZTO) and Fluorine doped Tin Oxide (FTO).

As described above, the thin film transistor array substrate and the method of manufacturing the same may use the pixel electrode and the transparent electrode used as the transparent electrode as the transparent conductive film containing no indium, thereby reducing the manufacturing cost.

Hereinafter, a thin film transistor array substrate and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

1A is a cross-sectional view illustrating a thin film transistor array substrate according to a first embodiment of the present invention.

As shown in FIG. 1A, in the thin film transistor array substrate according to the present invention, a gate line 12c and a data line 20b are formed on the substrate 10 to define a pixel region. A thin film transistor, which is a switching element, is formed in an intersection region of the gate line 12c and the data line 20b, and a common electrode 22 and a pixel electrode 28a for generating a transverse electric field to drive the liquid crystal in the pixel region. This is arranged.

The thin film transistor includes a gate electrode 12a integrally formed with the gate line 12b, a drain electrode 20e formed to face the source electrode 20f connected to the data line 20c, and the source electrode 20f. And an active layer 18d forming a channel region between the source electrode 20f and the drain electrode 20e by the gate voltage supplied to the gate electrode 12a.

The gate line 12b and the data line 20c extend toward the driving circuit part and are connected to the corresponding gate pad 12c and the data pad 20b, respectively, and the gate pad 12c is driven through the gate contact hole. Electrically connected to a gate pad electrode 28b receiving a scan signal from a circuit portion, and the data pad 20b is electrically connected to a data pad electrode 28c receiving a data signal from the driving circuit through a data contact hole. do.

The pixel electrode 22, the common electrode 28a, the gate pad electrode 28b, and the data pad electrode 28c are formed of a transparent conductive oxide that does not contain indium.

The transparent conductive film containing no indium may be formed of a group consisting of Al doped ZnO (ZAO), Ga doped ZnO (ZGO), Zinc Oxide (ZnO), Zinc Tin Oxide (ZTO), and Fluorine doped Tin Oxide (FTO). It can be made of any one selected, in addition to the group consisting of ZAO (Al doped ZnO), ZGO (Ga doped ZnO), ZnO (Zinc Oxide), ZTO (Zinc Tin Oxide) and FTO (Fluorine doped Tin Oxide) ZnO It is formed by using as a main component, one or more kinds of oxides having a divalent tetravalent valence of 0.1 to 6%.

The indium-free transparent conductive film is formed to a thickness of about 400 ~ 700Å by the DC magnetron sputtering method.

Such a transparent conductive film that does not contain indium has an average transmittance in the visible light region (400-700 nm wavelength range) compared to that of ITO and IZO, which is used as a conventional transparent electrode.

As described above, the thin film transistor array substrate may reduce manufacturing costs by using the pixel electrode and the transparent electrode used as the transparent electrode as the transparent conductive film containing no indium.

The first embodiment according to the present invention as described above is used in a horizontal field type liquid crystal display device in which both a pixel electrode and a common electrode are formed on a thin film transistor array substrate, and the second embodiment according to the present invention to be described below is a thin film transistor. A pixel electrode is formed on an array substrate and a common electrode is formed on a color filter array substrate (not shown) facing the thin film transistor array substrate.

Hereinafter, a thin film transistor array substrate used in a vertical field type liquid crystal display device will be described.

1B is a cross-sectional view illustrating a thin film transistor array substrate according to a second embodiment of the present invention.

As shown in FIG. 1B, the thin film transistor array substrate according to the present invention includes a substrate 10, a gate line 12c, a data line 20b, a gate pad 12c, a data pad 20b, and a gate pad electrode ( A thin film transistor formed of the data pad electrode 28c, the gate insulating film 14, the protective film 24 and the gate electrode 12a, the source electrode 20f, the drain electrode 20e, and the active layer 18d. Although they are formed to have the same structure as the thin film transistor array substrate shown in FIG. 1A, detailed description thereof will be omitted since it is redundant.

In order to form a vertical electric field, a pixel electrode 28a facing a common electrode (not shown) formed on the color filter array substrate is formed in the pixel region.

The pixel electrode 28a, the gate pad electrode 28b, and the data pad electrode 28c are formed of a transparent conductive oxide that does not contain indium.

The transparent conductive film containing no indium may be formed of a group consisting of Al doped ZnO (ZAO), Ga doped ZnO (ZGO), Zinc Oxide (ZnO), Zinc Tin Oxide (ZTO), and Fluorine doped Tin Oxide (FTO). It can be made of any one selected, in addition to the group consisting of ZAO (Al doped ZnO), ZGO (Ga doped ZnO), ZnO (Zinc Oxide), ZTO (Zinc Tin Oxide) and FTO (Fluorine doped Tin Oxide) ZnO It is formed by using as a main component, one or more kinds of oxides having a divalent tetravalent valence of 0.1 to 6%.

The indium-free transparent conductive film is formed to a thickness of about 400 ~ 700Å by the DC magnetron sputtering method.

Such a transparent conductive film that does not contain indium has an average transmittance in the visible light region (400-700 nm wavelength range) compared to that of ITO and IZO, which is used as a conventional transparent electrode.

As described above, the thin film transistor array substrate may reduce manufacturing costs by using the pixel electrode and the transparent electrode used as the transparent electrode as the transparent conductive film containing no indium.

Next, a method of manufacturing the thin film transistor array substrate according to the first and second embodiments will be described in detail.

2A to 2I are process flowcharts sequentially illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

In this case, the thin film transistor array substrate disclosed in the first embodiment of the present invention is used in a transverse field type liquid crystal display device in which both a common electrode and a pixel electrode are formed.

First, as shown in FIG. 2A, a gate electrode 12a, a gate line 12b, and a gate pad 12c are formed on the substrate 10.

The substrate 10 may include a region G-Pad in which a gate pad is formed, a region D-Pad in which a data pad is formed, a region D-line in which a data line is formed, and a region in which a gate line is formed. (G-line), the pixel region (PXL), and the region (TFT) in which the thin film transistor is formed.

The gate electrode 12a, the gate line 12b, and the gate pad 12c form a gate metal film on the substrate 10 and a first photoresist pattern (not shown) on the gate metal film. Subsequently, the gate metal film is etched using the first photoresist pattern (not shown) as an etching mask.

The first photoresist pattern (not shown) is formed by forming a photoresist on the gate metal film and performing a photolithography process using the first mask on the photoresist.

Subsequently, as shown in FIG. 2B, the gate insulating layer 16, the semiconductor layer 18a, and the metal for data are formed on the substrate 10 on which the gate electrode 12a, the gate line 12b, and the gate pad 12c are formed. The film 20a is formed sequentially.

At this time, the semiconductor layer 18a is formed of an amorphous silicon layer and an n + amorphous silicon layer.

Next, as shown in FIG. 2C, second photoresist patterns 204a to 204c are formed on the substrate 10 on which the data metal film 20a is formed.

The second photoresist patterns 204a to 204c include a photoresist pattern 204a for forming a data pad, a photoresist pattern 204b for forming a data line, and a photoresist pattern 204c for forming a source / drain electrode.

The second photoresist patterns 204a to 204c are formed by a photo process using a second mask (not shown) after forming a photoresist on the data metal film 20a. In this case, the second mask uses a mask having three different transmittances including a transmission region for transmitting light, a semi-transmission region for transmitting a portion of light and blocking a portion of the light, and a blocking region for blocking light. The photoresist remains as it is in the blocking region. The photoresist remains in a semi-transmissive region at a thickness lower than that of the blocking region, and no photoresist remains in the transmissive region.

Therefore, in the second photoresist patterns 204a to 204c, since the data pad forming photoresist pattern 204a and the data line forming photoresist pattern 204b are disposed in the blocking region, the photoresist remains as it is, and the source Since the region where the source / drain electrode is to be formed in the photoresist pattern 204c for forming the drain / drain electrode is disposed in the blocking region, the photoresist remains as it is, and the region in which the channel region is to be formed corresponds to the transflective region. Remain at a lower thickness than the photoresist.

Subsequently, as illustrated in FIG. 2D, the data pads 18b and 20b, the data lines 18c and 20c, and the source / drain electrode patterns may be formed on the substrate 10 on which the second photoresist patterns 204a to 204c are formed. 18d, 20d).

The data pads 18b and 20b, the data lines 18c and 20c, and the source / drain electrode patterns 18d and 20d may use the second photoresist patterns 204a through 204c as an etch mask to form the data metal film 20a, The semiconductor layer 18a is formed by etching.

Subsequently, as illustrated in FIG. 2E, the second photoresist patterns 204a to 204c are ashed to form third photoresist patterns 206a to 206c.

At this time, the photoresist pattern 204c for forming the source / drain electrodes remaining in the region where the channel is to be formed is removed during the ashing process, and the data metal film 20d for the data of the source / drain electrode pattern formed in the region where the channel is to be formed. The exposed third photoresist pattern 206c is formed.

Subsequently, the source / drain electrodes 20e and 20f are formed by etching the data metal film 20d of the source / drain electrode pattern in which the third photoresist patterns 206a to 206c are exposed as an etching mask.

As shown in FIG. 2F, the third photoresist patterns 206a to 206c are removed by performing a strip process on the substrate on which the source / drain electrodes 20e and 20f are formed.

Subsequently, as illustrated in FIG. 2G, the pixel electrode 22 is formed on the substrate 10 on which the source / drain electrodes 20e and 20f are formed.

The pixel electrode 22 forms a transparent conductive oxide that does not include indium on the substrate on which the source / drain electrodes 20e and 20f are formed, and does not include indium. After forming the fourth photoresist pattern (not shown) on the conductive film, the fourth photoresist pattern (not shown) is formed by etching the transparent conductive film with an etching mask.

The fourth photoresist pattern (not shown) is formed by forming a photoresist on a transparent conductive film containing no indium and performing a photolithography process using a third mask on the photoresist.

The transparent conductive film containing no indium may be formed of a group consisting of Al doped ZnO (ZAO), Ga doped ZnO (ZGO), Zinc Oxide (ZnO), Zinc Tin Oxide (ZTO), and Fluorine doped Tin Oxide (FTO). It can be made of any one selected.

Subsequently, as shown in FIG. 2H, a passivation layer 24 is formed on the substrate 10 on which the pixel electrode 22 is formed, and the gate pad contact hole 26a and the data pad contact hole are formed in the passivation layer 24. 26b).

The gate pad contact hole 26a and the data pad contact hole 26b are formed by forming a fifth photoresist pattern on the passivation layer 24 and then etching the passivation layer 24 using the fifth photoresist pattern as an etch mask. .

The fifth photoresist pattern is formed by a photo process using a fourth mask (not shown) after the photoresist is formed on the passivation layer 24.

Subsequently, as shown in FIG. 2I, the common electrode 28a, the gate pad terminal portion 28b, and the data pad terminal portion (on the substrate 10 on which the gate pad contact hole 26a and the data pad contact hole 26b are formed) are formed. This step is completed by forming 28c).

The common electrode 28a, the gate pad terminal portion 28b, and the data pad terminal portion 28c do not include indium on the substrate 10 on which the gate pad contact hole 26a and the data pad contact hole 26b are formed. A transparent conductive film, a sixth photoresist pattern is formed on the transparent conductive film that does not contain indium, and then the transparent conductive film is etched using the sixth photoresist pattern as an etching mask. Form.

The sixth photoresist pattern is formed by forming a photoresist on a transparent conductive film containing no indium and performing a photolithography process using a fifth mask on the photoresist.

The transparent conductive film containing no indium may be formed of a group consisting of Al doped ZnO (ZAO), Ga doped ZnO (ZGO), Zinc Oxide (ZnO), Zinc Tin Oxide (ZTO), and Fluorine doped Tin Oxide (FTO). It can be made of any one selected, in addition to the group consisting of ZAO (Al doped ZnO), ZGO (Ga doped ZnO), ZnO (Zinc Oxide), ZTO (Zinc Tin Oxide) and FTO (Fluorine doped Tin Oxide) ZnO It is formed by using as a main component, one or more kinds of oxides having a divalent tetravalent valence of 0.1 to 6%.

The indium-free transparent conductive film is formed to a thickness of about 400 ~ 700Å by the DC magnetron sputtering method.

Such a transparent conductive film that does not contain indium has an effect of increasing the average transmittance in the visible light region (wavelength of 400 ~ 700nm) compared to ITO and IZO, which is used as a conventional transparent electrode.

As described above, in the method of manufacturing the thin film transistor array substrate, the manufacturing cost can be reduced by using the pixel electrode and the transparent electrode used as the transparent electrode as the transparent conductive film containing no indium.

3A to 3C are process flowcharts sequentially illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

As shown in FIG. 3A, a gate electrode 12a, a gate line 12b, a gate pad 12c, a data pad 18b and 20b, a data line 18c and 20c, and a storage capacitor are disposed on a substrate 10. Upper electrodes 18d and 20d and source / drain electrode patterns 18e and 20e are formed. Gate electrodes 12a, gate lines 12b, gate pads 12c, data pads 18b and 20b, data lines 18c and 20c, upper electrodes 18d and 20d of storage capacitors, and the sources disclosed in FIG. Since the / drain electrode patterns 18e and 20e are formed through the same process as that of FIGS. 2A to 2F of the first embodiment of the present invention, description thereof will be omitted.

As shown in FIG. 3B, the gate electrode 12a, the gate line 12b, the gate pad 12c, the data pads 18b and 20b, the data lines 18c and 20c, the source / drain electrode patterns 18d, A protective film 24 is formed on the substrate 10 having the 20d), and a drain contact hole 26c, a gate pad contact hole 26a, and a data pad contact hole 26b are formed in the protective film 24.

The drain contact hole 26c, the gate pad contact hole 26a, and the data pad contact hole 26b form a fifth photoresist pattern on the passivation layer 24, and then use the first photoresist pattern as an etching mask. 24) is formed by etching.

The first photoresist pattern is formed by a photo process using a fourth mask (not shown) after the photoresist is formed on the passivation layer 24.

Subsequently, as illustrated in FIG. 3C, the pixel electrode 28a and the gate pad terminal portion (not shown) are formed on the substrate 10 on which the drain contact hole 26c, the gate pad contact hole 26a, and the data pad contact hole 26b are formed. 28b), this step is completed by forming the data pad terminal portion 28c.

The pixel electrode 28a, the gate pad terminal portion 28b, and the data pad terminal portion 28c do not include indium on the substrate 10 on which the gate pad contact hole 26a and the data pad contact hole 26b are formed. A transparent conductive film, a sixth photoresist pattern is formed on the transparent conductive film not containing indium, and the second conductive layer is etched using the second photoresist pattern as an etching mask. Form.

The second photoresist pattern is formed by forming a photoresist on a transparent conductive film containing no indium and performing a photolithography process using a fifth mask on the photoresist.

The transparent conductive film containing no indium may be formed of a group consisting of Al doped ZnO (ZAO), Ga doped ZnO (ZGO), Zinc Oxide (ZnO), Zinc Tin Oxide (ZTO), and Fluorine doped Tin Oxide (FTO). It can be made of any one selected, in addition to the group consisting of ZAO (Al doped ZnO), ZGO (Ga doped ZnO), ZnO (Zinc Oxide), ZTO (Zinc Tin Oxide) and FTO (Fluorine doped Tin Oxide) ZnO It is formed by using as a main component, one or more kinds of oxides having a divalent tetravalent valence of 0.1 to 6%.

The indium-free transparent conductive film is formed to a thickness of about 400 ~ 700Å by the DC magnetron sputtering method.

Such a transparent conductive film that does not contain indium has an effect of increasing the average transmittance in the visible light region (wavelength of 400 ~ 700nm) compared to ITO and IZO used as a conventional transparent electrode.

As described above, the manufacturing method of the thin film transistor can reduce the manufacturing cost by using the pixel electrode and the transparent electrode used as the transparent electrode as a transparent conductive film containing no indium.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1A is a cross-sectional view illustrating a thin film transistor array substrate according to a first embodiment of the present invention.

1B is a cross-sectional view illustrating a thin film transistor array substrate according to a second embodiment of the present invention.

2A to 2I are process flowcharts sequentially illustrating a method of manufacturing a thin film transistor array substrate according to a first embodiment of the present invention.

3A to 3C are process flowcharts sequentially illustrating a method of manufacturing a thin film transistor array substrate according to a second embodiment of the present invention.

Claims (7)

A gate line and a data line formed on the substrate and arranged to cross each other to define a pixel region; A thin film transistor formed at a portion where the gate line and the data line cross each other; A pixel electrode connected to the drain electrode of the thin film transistor and arranged in the pixel region; The pixel electrode is a thin film transistor array substrate, characterized in that formed of a transparent conductive film containing no indium (Indium). The thin film transistor array substrate of claim 1, further comprising a common electrode formed by alternating with the pixel electrode in the pixel region to generate a transverse electric field, and formed of a transparent conductive film containing no indium. The display device of claim 1, wherein the pixel electrode and the common electrode Thin film transistor array characterized in that it is formed of any one selected from the group consisting of ZAO (Al doped ZnO), ZGO (Ga doped ZnO), ZnO (Zinc Oxide), ZTO (Zinc Tin Oxide) and FTO (Fluorine doped Tin Oxide) Board. Forming a gate line and a gate electrode on the substrate; Forming a gate insulating film on the substrate on which the gate line and the gate electrode are formed; Forming a data line, a source, and a drain electrode on the substrate on which the gate insulating film is formed; Forming a pixel electrode in contact with the drain electrode by using a transparent conductive film containing no indium component; Forming a protective film on the substrate on which the pixel electrode is formed; A method of manufacturing a thin film transistor array substrate, the method comprising: forming a common electrode on the protective film using a transparent conductive film containing no indium component. The method of claim 4, wherein the pixel electrode and the common electrode Thin film transistor array characterized in that it is formed of any one selected from the group consisting of ZAO (Al doped ZnO), ZGO (Ga doped ZnO), ZnO (Zinc Oxide), ZTO (Zinc Tin Oxide) and FTO (Fluorine doped Tin Oxide) Method of manufacturing a substrate. Forming a gate line and a gate electrode on the substrate; Forming a gate insulating film on the substrate on which the gate line and the gate electrode are formed; Forming a data line, a source, and a drain electrode on the substrate on which the gate insulating film is formed; Forming a protective film on the substrate on which the data line and the source and drain electrodes are formed; Forming a contact hole exposing the drain electrode in the passivation layer; And forming a pixel electrode in contact with the drain electrode through the contact hole using a transparent conductive film containing no indium component. The method of claim 6, wherein the pixel electrode Thin film transistor array characterized in that it is formed of any one selected from the group consisting of ZAO (Al doped ZnO), ZGO (Ga doped ZnO), ZnO (Zinc Oxide), ZTO (Zinc Tin Oxide) and FTO (Fluorine doped Tin Oxide) Method of manufacturing a substrate.

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