KR20110053034A - Liquid crystal display device for cot type and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A COT(Color Filter on TFT) type liquid crystal display device and a method for manufacturing the same are provided to increase the storage capacitance. CONSTITUTION: A COT type liquid crystal display device comprises data line(20b) which defines pixel regions, a TFT formed on the pixel regions, a first protective layer(22) formed in the front side of the TFT, a color filter layer(24) formed on the first protective layer coping with the pixel region, a second protective layer(26) including a contact hole(28a) for exposing a drain electrode of the TFT, and a pixel electrode(30b) formed on the pixel region and connected with a drain electrode(18bD) through the drain contact hole.

Description

Liquid crystal display device for COT type and Method for manufacturing the same

The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly to a COT type liquid crystal display device and a manufacturing method thereof.

Generally, the driving principle of a liquid crystal display device utilizes the optical anisotropy and polarization properties of a liquid crystal. Since the liquid crystal is thin and long in structure, the liquid crystal has directivity in the arrangement of molecules, and the direction of the molecular arrangement can be controlled by artificially applying an electric field to the liquid crystal.

Accordingly, if the molecular arrangement direction of the liquid crystal is arbitrarily adjusted, the molecular arrangement of the liquid crystal is changed, and light is refracted in the molecular arrangement direction of the liquid crystal due to optical anisotropy to express image information.

Currently, an active matrix liquid crystal display device (AM-LCD: abbreviated as an active matrix LCD, abbreviated as a liquid crystal display device) in which a thin film transistor and pixel electrodes connected to the thin film transistor are arranged in a matrix manner has the best resolution and video performance. It is attracting attention.

The liquid crystal display includes an upper substrate on which color filters, a common electrode, etc. are formed, a lower substrate on which switching elements, pixel electrodes, etc. are formed, and a liquid crystal interposed between the two substrates. The liquid crystal is driven by an electric field applied up and down between the electrodes, and thus the characteristics such as transmittance and aperture ratio are excellent.

In addition, a technique for forming a color filter and a switching element formed on each of the upper and lower substrates on the same substrate has been proposed. This is a so-called COT (Color filter On TFT) type, and is configured to form a color filter on the lower substrate on which the switching element is formed. This aims to improve the aperture ratio by reducing the bonding margin considered in the process of bonding the upper and lower substrates.

On the other hand, the COT type liquid crystal display device includes a storage capacitor which maintains the image signal transmitted to one pixel cell for a predetermined period until the image signal is input at the next scan.

The storage capacitor Cst of such a storage capacitor can be expressed as ε × A / d (ε: dielectric constant, A: overlapping area of two electrodes of the storage capacitor, and d: thickness of the dielectric region). Thus, it can be seen that it is inversely proportional to the thickness of the dielectric region.

However, the conventional COT type liquid crystal display uses a gate insulating film as the dielectric region, and thus has a limit in increasing the storage capacitor storage capacity.

The present invention for solving the above problems is to provide a COT type liquid crystal display device and a manufacturing method thereof so that the storage capacitance of the storage capacitor can be increased.

According to an embodiment of the present invention, a COT type liquid crystal display device is formed on a substrate, and includes a gate line and a data line intersecting each other to define a pixel region, and a thin film transistor formed at an intersection of the pixel region. And a first passivation layer formed on the entire surface of the thin film transistor, a color filter layer formed to correspond to the pixel area on the first passivation layer, and a first passivation layer on which the color filter layer is formed. A second passivation layer having a drain contact hole exposing, a pixel electrode connected to the drain electrode through the drain contact hole, and formed in the pixel region, and a common electrode forming a horizontal electric field with the pixel electrode in the pixel region. And a storage capacitor formed integrally with the drain electrode with the first and second passivation layers therebetween. And a storage capacitor formed by overlapping a lower electrode and a storage capacitor upper electrode formed integrally with the common electrode.

According to an aspect of the present invention, there is provided a method of manufacturing a COT type liquid crystal display device, including forming a gate electrode on a substrate, forming a gate insulating film on the substrate on which the gate electrode is formed, and forming the gate insulating film. Forming a semiconductor pattern, a drain electrode, a source electrode, and a storage capacitor lower electrode on the formed substrate; and forming a first passivation layer on the substrate on which the semiconductor pattern, drain electrode, source electrode, and storage capacitor lower electrode are formed. Forming a color filter layer including a red color filter, a blue color filter, and a green color filter on the first passivation layer; forming a second passivation layer on a substrate on which the color filter layer is formed; Forming a drain contact hole exposing the drain electrode in the second passivation layer and the first passivation layer; Forming a pixel electrode, a common electrode, and a storage capacitor upper electrode on the formed substrate.

The storage capacitor upper electrode forms a storage capacitor with the storage capacitor lower electrode interposed between the first passivation layer and the second passivation layer.

The first passivation layer is formed to a thickness of 1200 ~ 1300Å, the second passivation film is formed to a thickness of 1200 ~ 1300Å.

As described above, the COT type liquid crystal display and the method of manufacturing the same according to the present invention use the first and second passivation layers instead of the gate insulating layer as the dielectric region of the storage capacitor, so that the thickness of the dielectric region is higher than when the gate insulating layer is used as the dielectric region. As a result, the storage capacity of the storage capacitor can be increased.

Hereinafter, a liquid crystal display and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view showing a COT type liquid crystal display device according to the present invention, Figure 2 is a line I-I ', II-II', III-III ', IV-IV', V-V 'of FIG. It is sectional drawing cut along.

1 and 2, the gate line 12c and the data line 20b formed to cross each other on the substrate 10, the thin film transistor T formed at each intersection thereof, and the crossing structure thereof. A pixel electrode 30b and a common electrode 30c formed to form a horizontal electric field in the provided pixel region are provided, and a common line 30d connected to the common electrode 30c is provided.

The substrate 10 includes a storage capacitor Cst formed by overlapping the storage capacitor lower electrode 20a and the storage capacitor upper electrode 30f, the gate pad 12c connected to the gate line 12b, A data pad 20c connected to the data line 20b and a common pad connected to the common line 30d and the common electrode 30c are further provided.

The gate line 12c for supplying the gate signal and the data line 20b for supplying the data signal are formed in an intersecting structure to define a pixel area.

In addition, the thin film transistor T formed at each crossing portion maintains the pixel signal of the data line 20b charged to the pixel electrode 30b in response to the gate signal of the gate line 12c. To this end, the thin film transistor T includes a gate electrode 12a connected to the gate line 12c, a source electrode 18bS connected to the data line 20b, and a drain electrode facing the source electrode 18bS. 18bD and a semiconductor pattern 16bc overlapping the gate electrode 12a with the gate insulating film 14 therebetween to form a channel between the source electrode 18bS and the drain electrode 18bD, and the source electrode 18bS. ) And an ohmic contact layer (not shown) formed on the semiconductor pattern 16bc except for the channel for ohmic contact between the drain electrode 18bD and the drain electrode 18bD.

The first passivation layer 22 is entirely deposited on the thin film transistor, and a color filter layer 24 having a structure in which red, blue, and green color filters are sequentially arranged for each pixel area is formed on the first passivation layer 22. And a second passivation layer 26 formed on the first passivation layer 22 on which the color filter layer 24 is formed, and having a drain contact hole 28a exposing the drain electrode, and forming the drain contact hole 28a. The pixel electrode 30b connected to the drain electrode 18bD is formed through the pixel electrode 30b. The pixel electrode 30b forms a horizontal electric field with the common electrode 30c in the pixel region.

The common line 30d and the common electrode 30c supply a reference voltage for driving the liquid crystal. The common line 30d includes a first common line formed in parallel with the data line 20b in the display area and a second common line formed in parallel with the gate line 12c in the display area. The common electrode 30c extends from the second common line toward the pixel area in a finger shape.

As a result, a horizontal electric field is formed between the pixel electrode 30b supplied with the pixel signal through the thin film transistor T and the common electrode 30c supplied with the reference voltage through the common line 30d. By the horizontal electric field, liquid crystal molecules arranged in the horizontal direction between the pixel electrode 30b and the common electrode 30c are rotated by dielectric anisotropy.

The gate line 12c is connected to a gate driver (not shown) through the gate pad 12b, and the data line 20b is connected to a data driver (not shown) through the data pad 20c.

In this case, the data pad 20b contacts the data pad terminal 30d through the data pad contact hole 28b, and the gate pad 12b contacts the gate pad terminal 30e through the gate pad contact hole 28c. ).

The storage capacitor Cst includes the storage capacitor lower electrode 20a integrally formed with the drain electrode with the first and second passivation layers 22 and 26 therebetween, the common line 30d and the common electrode 30c. An integrated storage capacitor upper electrode 30f is formed to overlap.

In this case, the first passivation layer 22 is formed to a thickness of 1200 to 1300 kPa, and the second passivation layer 26 is formed to a thickness of 1200 to 1300 kPa.

As such, when the first and second passivation layers having a thickness of about 2400 to 2600 μs are used as the dielectric regions of the storage capacitor, the thickness of the dielectric regions may be reduced than when the gate insulating layer having the thickness of 4000 μs or more is used as the dielectric region. This can increase the storage capacitor storage capacity.

Looking at the manufacturing method of the COT type liquid crystal display device according to the present invention in detail as follows.

Meanwhile, in the accompanying drawings, a region in which a thin film transistor is formed is denoted by a TFT, a region in which a storage capacitor is formed is denoted by Cst, a pixel region is denoted by PXL, and a region in which a data line is formed is D-line. Denotes G-Pad for the region where the gate pad is formed, and denotes D-Pad for the region where the data pad is formed.

3A and 3B are plan views and cross-sectional views for describing a first mask process in the method of manufacturing a COT type liquid crystal display device according to an exemplary embodiment of the present invention.

As shown in FIGS. 3A and 3B, a gate electrode 12a, a gate line 12b, and a gate pad 12b are formed on the substrate 10 through a first mask process.

The gate electrode 12a, the gate line 12b, and the gate pad 12b sequentially form a first metal layer and a photoresist on the substrate 10, and perform a photo process using the first mask on the photoresist. The first photoresist pattern (not shown) is formed, and the first metal layer is etched using the etching mask.

The first photoresist pattern (not shown) is removed by performing a strip process on the substrate 10 on which the gate electrode 12a, the gate line 12b, and the gate pad 12b have been formed.

4A and 4B are plan views and cross-sectional views illustrating a second mask process in the method for manufacturing a COT type liquid crystal display device according to an exemplary embodiment of the present invention, and FIGS. 5A to 5D illustrate the second mask process in detail. Sections for explaining.

As shown in FIGS. 4A and 4B, a gate insulating film 14 is formed on the substrate 10 on which the gate electrode 12a, the gate line 12b, and the gate pad 12b are formed, and the gate insulating film 14 is formed. The semiconductor pattern 16bc, the drain electrode 18bD, the source electrode 18bS, the storage capacitor lower electrode 20a, the data line 20b, and the data pad 20c through the second mask process on the formed substrate 10. ) Is formed.

Specifically, as shown in FIG. 5A, the semiconductor layer 16a and the second metal layer 18a are sequentially formed on the substrate 10 on which the gate insulating layer 14 is formed, and then on the second metal layer 18a. The second photoresist pattern 100a is formed on the substrate.

The second photoresist pattern 100a is formed by forming a photoresist on the second metal layer 18a and performing a photolithography process using the second mask on the photoresist.

In this case, the mask uses a mask having three different transmittances, including a transmissive region for transmitting light, a transflective region for transmitting and blocking a portion of the light, and a blocking region for blocking the light. In this case, the semi-transmissive region is a region having a higher transmittance than the blocking region, and the thickness of the photoresist pattern in the semi-transmissive region formed through the photolithography process is lower than the thickness of the photoresist pattern in the blocking region.

Accordingly, the blocking region is formed of a region corresponding to the source and drain electrodes of the region TFT in which the thin film transistor is formed, the region Cst in which the storage capacitor is formed, the region D-line in which the data line is formed, and the data pad. The transflective region is disposed in a region corresponding to the gate electrode of the TFT where the thin film transistor is formed, and the transmissive region is other than the region in which the blocking region and the transflective region are disposed. The remaining area is arranged.

Subsequently, as shown in FIG. 5B, the second metal layer 18a and the semiconductor layer 16a are etched using the second photoresist pattern 100a formed on the substrate 10 as an etching mask. ), The storage capacitor lower electrode 20a, the data line 20b, and the data pad 20c are formed.

The TFT pattern 20d, the storage capacitor lower electrode 20a, the data line 20b, and the data pad 20c each use the second photoresist pattern 100a as an etch mask, and the second metal layer 18a and the semiconductor layer 16a. Is formed by etching. As a result, the TFT pattern 20d, the storage capacitor lower electrode 20a, the data line 20b, and the data pad 20c are patterned with the second metal pattern 18b on which the second metal layer 18a and the semiconductor layer 16a are patterned. ) And the semiconductor pattern 16b are laminated.

Subsequently, an ashing process is performed on the substrate 10 on which the TFT pattern 20d, the storage capacitor lower electrode 20a, the data line 20b, and the data pad 20c are formed to form a third photoresist pattern 100b. To form. In this case, the third photoresist pattern 100b is formed to expose the second metal pattern 18b of the region where the channel region of the thin film transistor is to be formed.

Subsequently, as shown in FIG. 5C, a portion of the second metal pattern 18b and the semiconductor pattern 16b of the TFT pattern 20d is etched using the third photoresist pattern 100b as an etch mask to etch a thin film transistor. Semiconductor pattern 16bc, drain electrode 18bD, and source electrode 18bS are formed.

As shown in FIG. 5D, the strip for removing the third photoresist pattern 100b on the substrate 10 on which the semiconductor pattern 16bc, the drain electrode 18bD, and the source electrode 18bS of the thin film transistor are formed. By performing the process, the second mask process shown in FIG. 4B is completed.

6A and 6B are a plan view and a cross-sectional view for describing a third mask, a fourth mask, and a fifth mask process in a method of manufacturing a COT type liquid crystal display according to an exemplary embodiment of the present invention.

 6A and 6B, the semiconductor pattern 16bc, the drain electrode 18bD, the source electrode 18bS, the storage capacitor lower electrode 20a, the data line 20b, and the data pad 20c are formed. The first passivation layer 22 is formed on the entire surface of the substrate 10, and the red color filter 24R, the blue color filter 24B, and the green color filter (not shown) are formed through the third mask, the fourth mask, and the fifth mask process. ) Is formed a color filter layer 24 is formed.

The first passivation layer 22 is formed to a thickness of about 1200 ~ 1300Å.

The red color filter 24R is formed by applying a red color resist and performing a photo process using a third mask on the red color resist, and the blue color filter 24B is also coated with a blue color resist and a fourth mask on the blue color resist. It is formed by performing a photo process using, the green color filter is also formed by applying a green color resist and performing a photo process using a fifth mask on the green color resist.

The order of forming the red color filter, the blue color filter, and the green color filter may be any color filter formed first.

7A and 7B are a plan view and a cross-sectional view for describing a sixth mask process in the method of manufacturing a COT type liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIGS. 7A and 7B, the second passivation layer 26 is formed on the substrate 10 on which the color filter layer 24 is formed, and through the sixth mask process, the contact hole 28c for the gate pad and the data are formed. A pad contact hole 28b and a drain contact hole 28a are formed.

Specifically, a fourth photoresist pattern (not shown) is formed on the substrate 10 on which the second passivation layer 26 is formed.

The fourth photoresist pattern (not shown) is formed by forming a photoresist on the second passivation layer 26 and performing a photolithography process using the sixth mask on the photoresist.

Subsequently, the second passivation layer 26 and the first passivation layer 22 are etched using the fourth photoresist pattern (not shown) as an etching mask to form a drain contact hole 28a exposing the drain electrode 18bD. The first and second passivation layers 22 and 26 are etched using a photoresist pattern (not shown) as an etch mask to form a data pad contact hole 28b exposing the data pad 20c, and a fourth photoresist. The first and second passivation layers 22 and 26 and the gate insulating layer 14 are etched using a pattern (not shown) as an etch mask to form a gate pad contact hole 28c exposing the gate pad 12b.

The second passivation layer 26 is formed to a thickness of about 1200 ~ 1300Å.

8A and 8B are a plan view and a cross-sectional view for describing a seventh mask process in the method for manufacturing a COT type liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 9A to 9B illustrate the seventh mask process in detail. Sections for explaining.

As shown in FIGS. 8A and 8B, the pixel electrode 30b is formed on the substrate 10 on which the gate pad contact hole 28c, the data pad contact hole 28b, and the drain contact hole 28a are formed. An electrode 30c, a data pad terminal 30d, a gate pad terminal 30e, and a storage capacitor upper electrode 30f are formed.

Specifically, as shown in FIG. 9A, the transparent conductive film 20a is formed on the substrate 10 on which the gate pad contact hole 28c, the data pad contact hole 28b, and the drain contact hole 28a are formed. The fifth photoresist pattern 200a is formed on the transparent conductive film 30a.

The fifth photoresist pattern 200a is formed by forming a photoresist on the transparent conductive film 30a and performing a photolithography process using the seventh mask on the photoresist.

Subsequently, the transparent conductive layer 30a is etched using the fifth photoresist pattern 200a as an etch mask to thereby etch the pixel electrode 30b, the common electrode 30c, the data pad terminal 30d, the gate pad terminal 30e, and a storage capacitor. The upper electrode 30f is formed.

The pixel electrode 30b contacts the drain electrode 18bD through the drain contact hole 28a, and the data pad terminal 30d contacts the data pad 20c through the data pad contact hole 28b. The gate pad terminal 30e contacts the gate pad 12b through the gate pad contact hole 28c.

The storage capacitor upper electrode 30f is formed with the storage capacitor lower electrode 20a and the first and second passivation layers 22 and 26 interposed therebetween.

Such a COT type liquid crystal display device and a manufacturing method thereof according to the present invention uses first and second passivation layers formed to have a thickness of about 2400 to 2600 mV instead of a gate insulating layer formed to a thickness of 4000 mV or more as a dielectric region of the storage capacitor. When the gate insulating layer is used as the dielectric region, the thickness of the dielectric region is reduced, thereby increasing the storage capacitance of the storage capacitor.

1 is a plan view showing a COT type liquid crystal display device according to the present invention

FIG. 2 is a cross-sectional view taken along lines II ′, II-II ′, III-III ′, IV-IV ′, and V-V ′ of FIG. 1.

3A and 3B are a plan view and a cross-sectional view for explaining a first mask process in a method of manufacturing a COT type liquid crystal display according to an exemplary embodiment of the present invention.

4A and 4B are a plan view and a cross-sectional view for explaining a second mask process in a method of manufacturing a COT type liquid crystal display according to an exemplary embodiment of the present invention.

5A through 5D are cross-sectional views for describing the second mask process in detail.

6A and 6B are a plan view and a cross-sectional view for describing a third mask, a fourth mask, and a fifth mask process in a method of manufacturing a COT type liquid crystal display according to an exemplary embodiment of the present invention.

7A and 7B are a plan view and a cross-sectional view for explaining a sixth mask process in the method of manufacturing the COT type liquid crystal display according to the embodiment of the present invention.

8A and 8B are a plan view and a cross-sectional view for describing a seventh mask process in the method of manufacturing a COT type liquid crystal display according to an exemplary embodiment of the present invention.

9A to 9B are cross-sectional views for describing the seventh mask process in detail.

Claims (5)

A gate line and a data line formed on the substrate and crossing each other to define a pixel region; A thin film transistor formed at an intersection of the pixel region; A first passivation layer formed on the entire surface of the thin film transistor; A color filter layer formed to correspond to the pixel area on the first passivation layer; A second passivation layer formed on the first passivation layer on which the color filter layer is formed, and having a drain contact hole exposing the drain electrode of the thin film transistor; A pixel electrode connected to the drain electrode through the drain contact hole and formed in the pixel region; A common electrode forming a horizontal electric field with the pixel electrode in the pixel region; A storage capacitor formed by overlapping a storage capacitor lower electrode formed integrally with the drain electrode with the first and second passivation layers interposed therebetween, and a storage capacitor upper electrode formed integrally with the common electrode; LCD display device. The COT type liquid crystal display device of claim 1, wherein the first passivation layer is formed to a thickness of 1200 to 1300 GPa, and the second passivation layer is formed to a thickness of 1200 to 1300 GPa. Forming a gate electrode on the substrate; Forming a gate insulating film on the substrate on which the gate electrode is formed; Forming a semiconductor pattern, a drain electrode, a source electrode, and a storage capacitor lower electrode on the substrate on which the gate insulating layer is formed; Forming a first passivation layer on the semiconductor pattern, the drain electrode, the source electrode, and the storage capacitor lower electrode; Forming a color filter layer including a red color filter, a blue color filter, and a green color filter on the first passivation layer; Forming a second passivation layer on the substrate on which the color filter layer is formed; Forming a drain contact hole exposing the drain electrode in the second passivation layer and the first passivation layer; And forming a pixel electrode, a common electrode, and a storage capacitor upper electrode on the substrate on which the drain contact hole is formed. The method of claim 3, wherein the storage capacitor upper electrode And forming a storage capacitor between the storage capacitor lower electrode, the first passivation layer, and the second passivation layer. The method of claim 3, Wherein the first passivation layer is formed to a thickness of 1200 to 1300 GPa, and the second passivation layer is formed to a thickness of 1200 to 1300 GPa.

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