KR20110023038A - A fabricating method of inner layer substrate - Google Patents

Abstract

PURPOSE: An inner layer substrate manufacturing method is provided to implement the minute circuit by forming the inner layer circuit layer by applying the external layer circuit forming method to the prepreg. CONSTITUTION: An insulating layer(104) is laminated on the surface of a prepreg(102). A via hole is formed on the prepreg on which the insulating layer is laminated. An electro-less plating layer(108) including the inner wall of the via hole is formed on the surface of the insulating layer. An electrolytic plating layer(112) is formed on the electro-less plating layer the inside of the via hole.

Description

A fabricating method of inner layer substrate

The present invention relates to a method for producing an inner layer substrate.

In general, a printed circuit board is wired to one side or both sides of a board made of various thermosetting synthetic resins, and then an IC or an electronic component is disposed and fixed on the board and coated with an insulator by implementing electrical wiring therebetween.

In recent years, with the development of the electronics industry, the demand for high functionalization and light weight reduction of electronic components is rapidly increasing. To cope with this trend, printed circuit boards equipped with electronic components are also required to have high density wiring and thinning, and in particular, Research on high integration has been actively conducted.

 1 to 7 are process cross-sectional views showing a method of manufacturing an inner layer substrate using an etching method according to the prior art in the process order. Hereinafter, a manufacturing method of an inner layer substrate will be described with reference to the drawings.

First, as shown in FIG. 1, the double-sided copper clad laminate (CCL) 10 by which the copper foil layers 14a and 14b were laminated on both surfaces of the insulating layer 12 is prepared.

Next, as shown in Fig. 2, via holes 16 for interlayer connection are machined using mechanical drilling means.

Next, as shown in FIG. 3, the electroless plating layer 18 is formed on the copper foil layers 14a and 14b including the inner wall of the via hole 16.

Next, as shown in FIG. 4, the electroplating layer 20 is formed in the electroless plating layer 18, and the plugging ink 22 is filled in the via hole 16 to improve reliability.

Next, as shown in FIG. 5, the plugging ink 22 protruding out of the via hole 16 is removed using the polishing apparatus 24.

Next, as shown in FIG. 6, after the dry film (DF) 26 is applied to the electroplating layer 20, the dry plum 26 is removed except for the circuit forming region through an exposure and development process. Remove

Finally, as shown in FIG. 7, as the dry film 26 is removed, the exposed copper foil layers 14a and 14b, the electroless plating layer 18, and the electrolytic plating layer 20 are removed by etching to form an inner layer circuit. The layers 28a and 28b are formed, and the dry film 26 is removed to complete the inner layer substrate.

However, in the method of manufacturing the inner layer substrate according to the related art, the formation of the inner layer circuit layers 28a and 28b is performed based on the double-sided copper-clad laminate 10 having a predetermined thickness or more, thereby limiting the fine circuitization.

Structurally, since the inner circuit layers 28a and 28b are composed of the copper foil layers 14a and 14b, the electroless plating layer 18, and the electrolytic plating layer 20, there is a limit to the fine circuitization and the etching is performed by etching. It takes a long time in the removal process, there is a problem that the undercut (undercut) occurs and the delamination from the insulating layer 12 occurs.

In order to solve this problem, various methods such as the use of separate design rules, the thickness control of the copper foil layers 14a and 14b, and the development of a dedicated anisotropic etchant have been attempted. Due to the lack of design flexibility, the innerlayer board is unable to escape the ground role.

The present invention has been made to solve the above problems, an object of the present invention is to provide a method for manufacturing an inner layer substrate that can implement a fine pattern by a simple process.

In the method of manufacturing an inner layer substrate according to a preferred embodiment of the present invention, (A) stacking an insulating layer on the surface of the prepreg, and forming a via hole, (B) the surface of the insulating layer including the inner wall of the via hole Forming an electroless plating layer on the electroless plating layer, including the inside of the via hole, and patterning the electroless plating layer and the electrolytic plating layer to form an inner circuit layer. It is characterized by including.

In this case, the insulating layer is characterized in that the build-up layer interlayer insulating film (ABF).

In addition, the step (C), (C1) applying a plating resist having an open portion for exposing the circuit forming region to the electroless plating layer, (C2) including the inside of the via hole to the electrolytic plating layer on the open portion Forming (C3) removing the plating resist, and (C4) removing the electroless plating layer exposed by the removal of the plating resist.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to this, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may appropriately define the concept of a term in order to best describe its invention The present invention should be construed in accordance with the spirit and scope of the present invention.

According to the present invention, since the inner circuit layer is formed by applying the outer circuit forming method to the prepreg, the microcircuit can be realized.

In addition, according to the present invention, by using a prepreg without using a thick double-sided copper clad laminate, it is possible to reduce the thickness of the inner layer substrate, and to secure sufficient adhesion to the electroless plating layer by laminating an insulating layer on the prepreg. Will be.

In addition, according to the present invention, a via hole having a small diameter can be processed, and thus an electroplating layer can be formed at a time in the via hole in the electrolytic plating process, thereby eliminating the need for a separate plugging ink injection process.

In addition, according to the present invention, since the inner circuit layer is formed of an electroless plating layer and an electrolytic plating layer, and the thickness thereof is thin, it is possible to minimize the occurrence of an undercut phenomenon in the process of forming the electroless plating layer.

The objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and the preferred embodiments associated with the accompanying drawings. In the present specification, in adding reference numerals to the components of each drawing, it should be noted that the same components as possible, even if displayed on different drawings have the same number as possible. In addition, in describing the present invention, if it is determined that the detailed description of the related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

 Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

8 to 14 are process cross-sectional views showing the manufacturing method of the inner layer substrate according to the preferred embodiment of the present invention in the process order. Hereinafter, a method of manufacturing the inner layer substrate according to the present embodiment will be described with reference to this.

First, as shown in FIG. 8, the insulating layer 104 is laminated on the prepreg 102.

Here, the prepreg 102 is a material for maintaining electrical insulation, mechanical strength and stiffness, and dimensional stability to a resin material having excellent electrical properties, by weaving a fiber bundle consisting of short fibers of 5 ~ 9㎛ diameter The glass fiber made has a structure impregnated as a reinforcing base material.

In addition, the insulating layer 104 is a member laminated to the prepreg 102 to prevent the adhesion of the electroless plating layer 108 to the prepreg 102, for example, build-up layer interlayer insulating film (ABF) This is used.

In this step, the prepreg 102 in which the insulating layer 104 which has a thin thickness compared with the thick double-sided copper clad laminated board used conventionally is laminated | stacked is formed.

Next, as shown in FIG. 9, the via hole 106 is processed in the prepreg 102 in which the insulating layer 104 is laminated.

At this time, the via hole 106 is processed by a drilling operation such as a CNC drill (Computer Numerial Control drill), CO ₂ or Yag laser drill. After the hole processing, deburring and desmear are performed to remove burrs and smears of the copper foil generated by the drilling operation.

On the other hand, the prepreg 102 in which the insulating layer 104 is laminated is thinner than the conventional double-sided copper clad laminate, so that the via hole 106 can be easily processed, and the via hole 106 having a small diameter can be processed. Will be.

Next, as shown in FIG. 10, an electroless plating process is performed on the insulating layer 104 including the inner wall of the via hole 106 to form an electroless plating layer 108.

In this case, the electroless plating layer 108 may include, for example, a degreasing process, a soft etching process, a pre-catalyst process, a catalyst treatment process, an activation process, and an electroless plating process. Process, and a general catalyst precipitation method including an oxidation treatment process. Detailed description of the catalyst precipitation method, which is a known technique, will be omitted.

In this step, since the electroless plating process is performed on the insulating layer 104, sufficient adhesion to the electroless plating layer 108 can be ensured, thereby preventing the electroless plating layer 106 from being delaminated. It becomes possible.

Next, as shown in FIG. 11, a plating resist 110 having an open portion in the circuit formation region is applied to the electroless plating layer 108.

In this case, as the plating resist 110, a photosensitive resist such as a dry film or a positive liquid photo resist (P-LPR) may be used, and the photosensitive resist is applied to the electroless plating layer 108. Thereafter, an open portion can be formed by exposing ultraviolet rays to a portion corresponding to the circuit formation region and removing the exposed portion using a developer.

Next, as shown in FIG. 12, an electroplating process is performed on the open portion of the plating resist 110 including the inside of the via hole 106 to form an electroplating layer 112.

In the present invention, since the via hole 106 has a smaller diameter than the prior art, the electroplating layer 112 is also formed in the via hole 106. Therefore, the filling and polishing processes of the plugging ink inside the via hole 106 need not be performed as in the related art, thereby simplifying the process.

Next, as shown in FIG. 13, the plating resist 110 is removed using a stripping solution such as sodium hydroxide (NaOH) or potassium hydroxide (KOH).

Finally, as shown in FIG. 14, the electroless plating layer 108 exposed by removing the plating resist 110 is removed by quick etching or flash etching to remove the electroless plating layer 108 and the electroplating layer. An inner circuit layer 114 of 112 is formed.

Although the present invention has been described in detail through specific examples, this is for explaining the present invention in detail, and the method of manufacturing the inner layer substrate according to the present invention is not limited thereto, and it is common in the art within the technical spirit of the present invention. It is clear that modifications and improvements are possible by those with knowledge of the world.

All simple modifications and variations of the present invention fall within the scope of the present invention, and the specific scope of protection of the present invention will be apparent from the appended claims.

 1 to 7 are process cross-sectional views showing a method of manufacturing an inner layer substrate using an etching method according to the prior art in the process order.

8 to 14 are process cross-sectional views showing the manufacturing method of the inner layer substrate according to the preferred embodiment of the present invention in the process order.

<Description of the symbols for the main parts of the drawings>

102: prepreg 104: insulating layer

106: via hole 108: electroless plating layer

110: plating resist 112: electrolytic plating layer

114: inner circuit layer

Claims (3)

(A) stacking an insulating layer on the surface of the prepreg and forming a via hole; (B) forming an electroless plating layer on the surface of the insulating layer including the inner wall of the via hole; And (C) forming an electrolytic plating layer on the electroless plating layer including the inside of the via hole, and patterning the electroless plating layer and the electrolytic plating layer to form an inner circuit layer. Method of manufacturing an inner layer substrate comprising a. The method according to claim 1, The insulating layer is a manufacturing method of the inner layer substrate, characterized in that the build-up layer interlayer insulating film (ABF). The method according to claim 1, Step (C) is (C1) applying a plating resist having an open portion to expose a circuit formation region to the electroless plating layer; (C2) forming an electrolytic plating layer on the open part including the inside of the via hole; (C3) removing the plating resist; And (C4) removing the electroless plating layer exposed by removing the plating resist Method of manufacturing an inner layer substrate comprising a.

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