KR20100138087A - Image sensor and method for manufacuring thereof - Google Patents

Image sensor and method for manufacuring thereof Download PDF

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Publication number
KR20100138087A
KR20100138087A KR1020090056452A KR20090056452A KR20100138087A KR 20100138087 A KR20100138087 A KR 20100138087A KR 1020090056452 A KR1020090056452 A KR 1020090056452A KR 20090056452 A KR20090056452 A KR 20090056452A KR 20100138087 A KR20100138087 A KR 20100138087A
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South Korea
Prior art keywords
trench
device isolation
layer
forming
isolation layer
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KR1020090056452A
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Korean (ko)
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오영선
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주식회사 동부하이텍
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Priority to KR1020090056452A priority Critical patent/KR20100138087A/en
Publication of KR20100138087A publication Critical patent/KR20100138087A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14689—MOS based technologies

Abstract

PURPOSE: An image sensor and a method for manufacturing the same are provided to improve a channel stop property and a dark current property of a pixel region by forming a barrier layer in the trench of the pixel region and a device isolation layer in the trench of the logic region. CONSTITUTION: A semiconductor substrate(100) comprises a logic region(L) and a pixel region(P). A first trench(T1) is formed in the logic region and a second trench(T2) is formed in the pixel area. A first device isolation layer(135) is formed in the first trench and has a dense film by an annealing process. A barrier layer(140) is formed to surround the side and the lower side of the second trench. A second device isolation layer(155) is formed in the second trench.

Description

Image sensor and manufacturing method thereof {IMAGE SENSOR AND METHOD FOR MANUFACURING THEREOF}

Embodiments relate to an image sensor and a method of manufacturing the same.

An image sensor is a semiconductor device that converts an optical image into an electrical signal, and is mainly a charge coupled device (CCD) and CMOS (Complementary Metal Oxide Silicon) image sensor (CIS). ).

The CMOS image sensor implements an image by sequentially detecting an electrical signal of each unit pixel in a switching method of forming a photodiode and a MOS transistor in the unit pixel.

The image sensor includes a pixel area that receives light and converts it into electronic data, and a logical area that functions as I / O, signal processing, and data storage.

The pixel region includes a light receiving unit that receives light to generate electric charges, and a pixel device unit which electrically processes the electric charges of the light receiving unit.

In particular, since the function of the element in the pixel region is different from that of the general logic region, the desired characteristic of the desired element is different. In particular, shallow trench isolation (STI) used as an isolation layer requires different characteristics in a pixel region and a logic region.

1 to 5 are cross-sectional views illustrating a process of forming an isolation layer in a logic region and a pixel region of a general image sensor.

1 through 5, trenches T1 and T2 are formed in the logic region L and the pixel region P of the semiconductor substrate 10 using the pad insulating layers 20 and 30. After forming the mask 1 covering the logic region L, an impurity ion implantation process is performed in the trench T2 corresponding to the pixel region P to form the barrier region 40.

After filling the trenches T1 and T2 with an insulating material, a planarization process is performed to form device isolation layers 60 and 70 in the logic region L and the pixel region P, respectively, and to form the pad mask 30. Remove

In order to stabilize the gapfill material of the device isolation layers 60 and 70, an annealing process should be performed. In this case, since the ions 40 of the barrier region formed on the sidewall and the bottom of the device isolation layer 70 are diffused, an ion implantation effect is achieved. Disappears.

For this reason, the HDP annealing process, which is an annealing of the gap fill material, may not be performed. However, if the annealing process is not performed, the film quality of the trench gap fill material is not good. Degradation and deterioration of the device may occur.

In addition, since the high temperature thermal process that is to be performed before and after the formation of the STI in addition to the HDP annealing is somewhat difficult, the characteristics of the logic device may be changed.

The embodiment provides an image sensor and a method of manufacturing the same, in which different device isolation layers are applied to a pixel region and a peripheral circuit region.

An image sensor according to an embodiment includes a semiconductor substrate including a logic region and a pixel region; A first trench formed in the logic region and a second trench formed in the pixel region; A first isolation layer formed in the first trench and having a dense film quality by annealing; A barrier layer formed to surround side and bottom surfaces of the second trench; And a second device isolation layer formed on the second trench.

In accordance with another aspect of the present invention, a method of manufacturing an image sensor includes: preparing a semiconductor substrate in which a logic region and a pixel region are defined; Forming a first trench in the logic region; Forming a first device isolation layer having a dense film inside the first trench; Forming a second trench in the pixel region; Forming a barrier layer to surround side and bottom surfaces of the second trench; And forming a second device isolation layer in the second trench.

According to the image sensor and the manufacturing method thereof according to the embodiment, it is possible to form a device isolation film suitable for the characteristics of the logic region and the pixel region.

That is, the device isolation film subjected to the heat treatment process may be formed in the trench of the logic region, thereby improving film quality. In addition, a barrier layer may be formed in the trench of the pixel region to improve channel stop and dark current characteristics of the pixel region.

In addition, since it is not necessary to perform a separate mask process for forming the barrier layer, the reliability of the image sensor may be improved.

In addition, the trench in the pixel region may be formed in the form of a deep trench to improve the cross talk characteristic.

In addition, a linear nitride layer may be formed in the trench of the logic region or the pixel region to improve leakage current and mort characteristics.

An image sensor and a method of manufacturing the same according to an embodiment will be described in detail with reference to the accompanying drawings.

In the description of the embodiments, where described as being formed "on / over" of each layer, the on / over may be directly or through another layer ( indirectly) includes everything formed.

14, 15 and 16 are cross-sectional views illustrating an image sensor according to an embodiment.

Referring to FIG. 14, a semiconductor substrate 100 including a logic region L and a pixel region P, a first trench T1 formed in the logic region L, and a pixel region P may be formed. A first device isolation layer 135 formed on a second trench T2, the first trench T1, and having a dense film quality by annealing, and surrounding side surfaces and a bottom surface of the second trench T2. And a barrier layer 140 formed in the semiconductor substrate 100 and a second device isolation layer 155 formed in the second trench T2.

The first device isolation layer 135 and the second device isolation layer 155 may be formed of an insulating layer. For example, the first device isolation layer 135 and the second device isolation layer 155 may be formed of an HDP oxide layer.

In this case, the first device isolation layer 135 may be annealed to have a denser film quality than the second device isolation layer 155.

The barrier layer 140 may be formed of n-type or p-type impurities. By the barrier layer 140, the pixel region P may improve channel stop and dark current characteristics.

As illustrated in FIG. 15, a first linear nitride film 170 is formed between the first trench T1 and the first device isolation layer 135.

As illustrated in FIG. 16, a second linear nitride layer 180 is formed between the second trench T2 and the second device isolation layer 155.

Alternatively, although not shown in the drawing, both the first and second linear nitride films 170 and 180 may be formed in the first trench T1 and the second trench T2.

The first and second linear nitride layers 170 and 180 may be formed on the device isolation layer having an STI structure to reduce leakage current and to control mortise characteristics of the field region.

6 to 13, a manufacturing method of an image sensor according to an embodiment will be described.

Referring to FIG. 6, a semiconductor substrate 100 in which a logic area L and a pixel area P is defined is prepared.

The semiconductor substrate 100 may be a single crystal or polycrystalline silicon substrate, and may be a substrate doped with p-type or n-type impurities. For example, the semiconductor substrate 100 may be a p-type substrate.

Although not shown, a low concentration p-type epitaxial layer (p-epi) may be formed on the semiconductor substrate 100 by performing an epitaxial process.

The logic region L defined in the semiconductor substrate 100 is a region in which logic elements serving as input / output, signal processing, and data storage are formed. The pixel region P is a region in which a pixel device including a photodiode for processing charge generated by incident light as an electric signal is formed.

A device isolation film forming process is required to define active regions in the logic region L and the pixel region P. FIG. The device isolation layer may be formed by a shallow trench isolation (STI) process.

Referring to FIG. 6 again, a first trench T1 is formed in the semiconductor substrate 100 corresponding to the logic region L. Referring to FIG.

In order to form the first trenches T1, first, a pad oxide film 110 and a pad nitride film 120 are formed on the semiconductor substrate 100 to expose a first trench predetermined region.

The pad oxide layer 110 and the pad nitride layer 120 sequentially deposit an oxide layer SiO 2 (not shown) and a nitride layer Si 3 N 4 (not shown) on the semiconductor substrate 100. In addition, a TEOS layer may be further formed on the nitride film.

In addition, a first photoresist pattern 3 is formed on the nitride layer to expose a trench region of the logic region L. The pad oxide layer 110 and the pad nitride layer 120 exposing the first trench predetermined region on the semiconductor substrate 100 by selectively etching the nitride layer and the oxide layer using the first photoresist pattern 3 as an etching mask. Can be formed. The first trench T1 may be formed by using the pad oxide layer 110 and the pad nitride layer 120 to etch the semiconductor substrate 100 to a predetermined depth.

Meanwhile, the pad oxide layer 110 and the pad nitride layer 120 may serve as hard masks when etching the semiconductor substrate 100 to form trenches for device isolation.

7 and 8, a first insulating layer 130 such as an oxide film or a nitride film is deposited on the semiconductor substrate 100 so that the first trench T1 is gap-filled. For example, the first insulating layer 130 may be formed of an HDP oxide layer (High Density Plasma).

The planarization process is performed on the first insulating layer 130 to form a first isolation layer 135 in the first trench T1. For example, the planarization process may be a CMP process, and the pad nitride layer 120 may be used as the polishing endpoint.

Therefore, the first device isolation layer 135 is formed to have the same surface height as the pad nitride layer 120.

Meanwhile, a linear nitride layer 170 may be formed along the surface of the first trench T1 before forming the first insulating layer 130 in the first trench T1. 15)

9, a heat treatment process is performed on the first device isolation layer 135. For example, the heat treatment process may be performed at a temperature of 200 ~ 1500 ℃.

The heat treatment process may be selectively performed only on the first device isolation layer 135 corresponding to the logic region L. FIG.

That is, since the pad oxide film 110 and the pad nitride film 120 serve as a protective film in the pixel region P, the pad oxide film 110 and the pad nitride film 120 are not affected by the heat treatment process.

Accordingly, the quality of the first device isolation layer 135, which serves as device isolation in the logic region L, may be improved, thereby reducing leakage current and improving moat characteristics.

Referring to FIG. 10, a second trench T2 is formed in the pixel area P. Referring to FIG.

The second trench T2 may be formed by performing a photolithography and etching process on the pad oxide layer 110 and the pad nitride layer 120.

For example, the second trench T2 forms a second photoresist pattern 5 on the pad nitride layer 120 to expose the trench region of the pixel area P. By using the second photoresist pattern 5 as an etching mask, the pad nitride layer 120 and the pad oxide layer 110 may be selectively etched to expose the semiconductor substrate 100 corresponding to the second trench predetermined region. .

The second trench T2 may be formed by using the pad oxide layer 110 and the pad nitride layer 120 to etch the semiconductor substrate 100 to a predetermined depth.

Referring to FIG. 11, a barrier layer 140 is formed to surround sidewalls and a bottom surface of the second trench T2. The barrier layer 140 may be formed through an ion implantation process.

For example, the barrier layer 140 may be formed by an implant process using n-type or p-type impurities as a dopant.

The barrier layer 140 may be formed on side and bottom surfaces of the second trench T2. Therefore, it may serve as a dark current prevention and a channel stop in the pixel region P. FIG.

The barrier layer 140 may be formed only in the second trench T2. That is, since the pad nitride layer 120 is formed on the logic region L, and the pad nitride layer 120 serves as a protective layer, ions are prevented from being injected into the semiconductor substrate 100 of the logic region L. can do.

Accordingly, since the pad nitride layer 120 serves as an ion implantation blocking layer, a separate passivation layer for protecting the first device isolation layer 135 may be omitted.

In addition, since the pad nitride layer 120 serves as an ion implantation mask, an additional ion implantation mask for forming the barrier layer 140 in the second trench T2 may be omitted.

12 and 13, a second insulating layer 150, such as an oxide film or a nitride film, is deposited on the semiconductor substrate 100 so that the second trench T2 is gap-filled. For example, the second insulating layer 150 may be formed of an HDP oxide film (High Density Plasma).

The planarization process is performed on the second insulating layer 150 to form a second device isolation layer 155 in the second trench T2. For example, the planarization process may be a CMP process, and the pad nitride layer 120 may be used as the polishing endpoint.

Therefore, the second device isolation layer 155 may have the same height as the upper surface height of the pad nitride layer 120.

Although not shown, a linear nitride layer 180 may be formed before forming the second insulating layer 150 in the second trench T1 (see FIG. 16).

Referring to FIG. 14, the pad nitride layer 120 formed on the semiconductor substrate 100 is removed. The pad nitride layer 120 may be selectively removed by a dry or wet etching process.

Therefore, a first device isolation layer 135 is formed in the logic region L of the semiconductor substrate 100, and a second device isolation layer 155 is formed in the pixel region P.

The first device isolation layer 135 may be formed by a selective heat treatment process and may have a dense film quality, thereby improving moat characteristics and leakage current characteristics.

A barrier layer 140 may be formed around the second device isolation layer 155 to improve channel stop and dark current characteristics.

In particular, a separate mask and photo process for forming the barrier layer may be omitted, and productivity may be improved.

In addition, by forming a trench and a gap fill process for the pixel region separately, a device isolation layer structure specialized for the pixel region may be formed without changing the characteristics of the logic region.

21 is a sectional view showing an image sensor of another embodiment.

Referring to FIG. 21, a semiconductor substrate 200 including a logic region L and a pixel region P, a first trench T1 and a pixel region P formed in the logic region L may be formed. 2 trenches T2, a first device isolation layer 235 formed in the first trenches T1 and having a dense film quality by annealing, and surrounding side surfaces and a bottom surface of the second trenches T2. The barrier layer 240 and the second device isolation layer 255 formed in the second trench T2 are included.

The first device isolation layer 235 may be formed to have a first depth D1, and the second device isolation layer 255 may be formed to have a second depth D2 that is deeper than the first depth D1.

For example, the depth of the first device isolation layer 235 and the second device isolation layer 255 may have a ratio of about 1: 3 to about 10.

That is, the first device isolation layer 235 may be formed in the shallow trench, and the second device isolation layer 255 may be formed in the deep trench.

The first device isolation layer 235 may be formed of an insulating film such as an oxide film or a nitride film. The second device isolation layer 255 may be formed of a material having excellent gap fill capability such as polysilicon. Alternatively, the second device isolation layer 255 may be formed of an oxide film or a nitride film.

17 to 21 are sectional views showing the manufacturing process of the image sensor of another embodiment.

Referring to FIG. 17, a semiconductor substrate 200 in which a logic region L and a pixel region P are defined is prepared.

The semiconductor substrate 200 may be a single crystal or polycrystalline silicon substrate and may be a substrate doped with p-type or n-type impurities. For example, the semiconductor substrate 200 may be a p-type substrate.

Although not shown, a low concentration p-type epitaxial layer (p-epi) may be formed on the semiconductor substrate 200 by performing an epitaxial process.

The logic region L defined in the semiconductor substrate 200 is a region in which logic elements serving as input / output, signal processing, and data storage are formed. The pixel region P is a region in which a pixel device including a photodiode for processing charge generated by incident light as an electric signal is formed.

A device isolation film forming process is required to define active regions in the logic region L and the pixel region P. FIG. The device isolation layer may be formed by a shallow trench isolation (STI) process.

Referring to FIG. 17 again, a first trench T1 is formed in the semiconductor substrate 200 corresponding to the logic region L. Referring to FIG.

In order to form the first trenches T1, first, a pad oxide layer 210 and a pad nitride layer 220 are formed on the semiconductor substrate 200 to expose a first trench predetermined region.

The pad oxide film 210 and the pad nitride film 220 sequentially deposit an oxide film SiO 2 (not shown) and a nitride film Si 3 N 4 (not shown) on the semiconductor substrate 200. A pad theos film may be further formed on the nitride film.

A first photoresist pattern 7 is formed on the nitride layer to expose the trench predetermined region. The pad oxide layer 210 and the pad nitride layer 220 exposing the first trench predetermined region on the semiconductor substrate 200 by selectively etching the nitride layer and the oxide layer using the first photoresist pattern 7 as an etching mask. Can be formed.

The first trench T1 may be formed by etching the semiconductor substrate 200 to a predetermined depth by using the pad oxide layer 210 and the pad nitride layer 220.

For example, the first trench T1 may have a first depth D1 corresponding to 200˜1000 μs.

The pad oxide layer 210 and the pad nitride layer 20 may serve as hard masks during etching of the semiconductor substrate 200 for forming trenches for device isolation.

Referring to FIG. 18, an insulating film is gap-filled in the first trench T1, and a first device isolation film 235 is formed.

The first device isolation layer 235 may be formed by depositing a first insulating film (not shown) such as an oxide film or a nitride film on the semiconductor substrate 200, and then performing a planarization process on the first insulating film.

For example, the first device isolation layer 235 may be an HDP oxide layer.

Although not shown, a heat treatment process may be performed on the first device isolation layer 235. That is, as shown in FIG. 9, a heat treatment process may be applied to the first device isolation layer 135.

The heat treatment process may be selectively performed only on the first device isolation layer 235 corresponding to the logic region L. FIG. Therefore, the film quality of the first device isolation layer 235 may be improved to reduce leakage current and to improve moat characteristics.

Referring to FIG. 19, a second trench T2 is formed in the pixel area P. Referring to FIG.

The second trench T2 may be formed by performing a photolithography and etching process on the pad oxide layer 210 and the pad nitride layer 220.

For example, the second trench T2 forms a second photoresist pattern 9 exposing the trench region of the pixel region P on the pad nitride layer 220. The pad nitride layer 220 and the pad oxide layer 210 may be selectively etched using the second photoresist pattern 9 as an etch mask to expose the semiconductor substrate 200 corresponding to the second trench predetermined region. .

The second trench T2 may be formed by using the pad oxide layer 210 and the pad nitride layer 220 by using an etching mask and etching the semiconductor substrate 200 to a predetermined depth. The second trench T2 may be formed in the form of a deep trench.

That is, the second trench T2 may be formed to have a high aspect ratio. For example, the aspect ratio of the second trench T2 may be 1: 4 to 10 or more. The second trench T2 may have a second depth D2 corresponding to 1000˜4000 μs.

The second trench T2 may be formed in a deep trench shape to prevent electrical cross talk in the pixel region P. Referring to FIG.

That is, the second trench T2 may block electrons generated in the deep region of the semiconductor substrate 200 from passing to adjacent pixels.

Referring to FIG. 20, a barrier layer 240 is formed on sidewalls and a bottom surface of the second trench T2. The barrier layer 240 may be formed through an ion implantation process.

For example, the barrier layer 240 may be formed by an implant process using n-type or p-type impurities as a dopant.

The barrier layer 240 may be formed on sidewalls and bottom surfaces of the second trench T2. Therefore, it may serve as a dark current prevention and a channel stop in the pixel region P. FIG.

The barrier layer 240 may be formed only in the second trench T2. That is, since the pad nitride film 220 is formed on the logic region L, and the pad nitride film 220 serves as a protective layer, ions are injected into the semiconductor substrate 100 of the logic region L. Can be prevented.

Therefore, since the pad nitride layer 220 serves as an ion implantation blocking layer, an additional ion implantation mask for forming the barrier layer 240 in the second trench T2 may be omitted.

Meanwhile, the barrier layer 240 may not be formed.

Next, the second trench T2 is gap-filled to form a second device isolation layer 255.

The second device isolation layer 255 may be formed of an insulating material having excellent gap fill capability.

For example, the second device isolation layer 255 may be formed of polysilicon. Polysilicon has a good gap fill ability to fill the second trench T2 having a high aspect ratio. When the gap fill is made of such polysilicon, a liner oxide film and a liner nitride film may be first formed in the second trench T2.

In addition, the second device isolation layer 255 may be formed of Spin on Dielectric (SOD) or Spin on Glass (SOG). In the SOD and SOG methods, a silicon oxide-type material having a late viscosity is spin-coated to fill the second trench T2, and then the second device isolation layer 255 is thermally treated. Can be formed.

In addition, the second device isolation layer 255 may be formed in an HDP stacked structure. In the HDP method, an HDP oxide film may be deposited by performing a multistep process on the second trench T2.

In addition, the second device isolation layer 255 may be formed of Selective Epitaxial Growth (SEG). That is, after forming a pattern that becomes a seed of epitaxial growth at the lower end of the second trench T2, epi-silicon is grown on the second device isolation layer 255. ) Can be formed.

Referring to FIG. 21, the pad nitride film 220 formed on the semiconductor substrate 200 is removed. The pad nitride layer 220 may be selectively removed by a dry or wet etching process.

Therefore, a first device isolation layer 235 is formed in the logic region L of the semiconductor substrate 200, and a second device isolation layer 255 is formed in the pixel region P. In FIG.

The first device isolation layer 235 and the second device isolation layer 255 are formed by different processes.

That is, since the first device isolation layer 235 may be formed by a selective heat treatment process, and may have a dense film quality, the moat characteristic and the leakage current characteristic may be improved.

In addition, a barrier layer 240 may be formed around the second device isolation layer 255 to improve channel stop and dark current characteristics.

In addition, the second device isolation layer 255 may be formed to have a high aspect ratio, thereby preventing crosstalk of the image sensor.

 Accordingly, device isolation layers 235 and 255 that satisfy the characteristics of the logic region L and the pixel region P may be formed.

In addition, a separate mask and photo process for forming the barrier layer 240 may be omitted, and productivity may be improved.

In addition, by forming a trench and a gap fill process for the pixel region separately, a device isolation layer structure specialized for the pixel region may be formed without changing the characteristics of the logic region.

As described above with reference to the drawings illustrating a semiconductor device and a method for manufacturing the same according to the present invention, the present invention is not limited by the embodiments and drawings disclosed herein, but within the technical scope of the present invention Of course, various modifications may be made by those skilled in the art.

1 to 5 are cross-sectional views showing the manufacturing process of the image sensor according to the prior art.

6 to 13 are cross-sectional views illustrating a manufacturing process of an image sensor according to an embodiment.

14 to 18 are cross-sectional views illustrating a manufacturing process of an image sensor according to another exemplary embodiment.

Claims (16)

A semiconductor substrate including a logic region and a pixel region; A first trench formed in the logic region and a second trench formed in the pixel region; A first device isolation layer formed in the first trench and having a dense film quality by annealing; A barrier layer formed to surround side and bottom surfaces of the second trench; And And a second device isolation layer formed on the second trench. The method of claim 1, The barrier layer is formed of n-type or p-type impurities. The method of claim 1, And a linear nitride film formed along a surface of the first trench or the second trench. The method of claim 1, The first device isolation layer is formed to a first depth, the second device isolation layer is formed with a second depth deeper than the first depth. The method of claim 1, The first device isolation layer and the second device isolation layer is formed of an insulating film. The method of claim 4, wherein The first device isolation layer and the second device isolation layer is formed of different materials. Preparing a semiconductor substrate having a logic region and a pixel region defined therein; Forming a first trench in the logic region; Forming a first device isolation layer having a dense film inside the first trench; Forming a second trench in the pixel region; Forming a barrier layer to surround side and bottom surfaces of the second trench; And And forming a second device isolation layer in the second trench. The method of claim 7, wherein Forming the first trench, Forming a pad insulating layer exposing a portion of the semiconductor substrate corresponding to the logic region; And And etching the exposed semiconductor substrate using the pad insulating layer as an etching mask. The method of claim 7, wherein Forming the first device isolation film, Depositing a first insulating film on the first trench and then performing a planarization process; And And annealing the first insulating film in the first trench. The method of claim 8, Forming the second trench, Selectively etching the pad insulating layer to expose a portion of the semiconductor substrate corresponding to the pixel area; And And etching the exposed semiconductor substrate using the pad insulating layer as an etching mask. The method of claim 10, The barrier layer is formed by using the pad insulating film as an ion implantation mask and ion implantation of n-type impurities or p-type impurities into the second trench. The method of claim 10, The second device isolation layer is formed by a planarization process after forming a second insulating film inside the second trench. The method of claim 7, wherein And forming a linear nitride film along the surface of the first trench after forming the first trench. The method of claim 7, wherein And forming a linear nitride film along the surface of the second trench after forming the second trench. The method of claim 7, wherein And the first trench is formed as a shallow trench having a first depth, and the second trench is formed as a deep trench having a second depth deeper than the first depth. The method of claim 15, And an HDP oxide film is gap-filled in the first trench, and at least one of polysilicon, SOD, SOG, HDP, or SEG is gap-filled in the second trench.
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Cited By (5)

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Publication number Priority date Publication date Assignee Title
CN105304663A (en) * 2015-10-27 2016-02-03 上海华力微电子有限公司 Method for reducing metal pollution of working area of contact image sensor
CN105374840A (en) * 2015-10-27 2016-03-02 上海华力微电子有限公司 Method to reduce metal pollution in work area of contact-type image sensor
US10644051B2 (en) 2017-10-13 2020-05-05 Samsung Electronics Co., Ltd. Image sensor
CN112420761A (en) * 2020-11-20 2021-02-26 上海华力微电子有限公司 Method for improving crosstalk characteristic of near-infrared image sensor
CN117637597A (en) * 2024-01-26 2024-03-01 合肥晶合集成电路股份有限公司 Manufacturing method of semiconductor structure

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105304663A (en) * 2015-10-27 2016-02-03 上海华力微电子有限公司 Method for reducing metal pollution of working area of contact image sensor
CN105374840A (en) * 2015-10-27 2016-03-02 上海华力微电子有限公司 Method to reduce metal pollution in work area of contact-type image sensor
US10644051B2 (en) 2017-10-13 2020-05-05 Samsung Electronics Co., Ltd. Image sensor
CN112420761A (en) * 2020-11-20 2021-02-26 上海华力微电子有限公司 Method for improving crosstalk characteristic of near-infrared image sensor
CN117637597A (en) * 2024-01-26 2024-03-01 合肥晶合集成电路股份有限公司 Manufacturing method of semiconductor structure
CN117637597B (en) * 2024-01-26 2024-04-09 合肥晶合集成电路股份有限公司 Manufacturing method of semiconductor structure

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