KR20100124026A - Insert carrier of semiconductor package - Google Patents

Insert carrier of semiconductor package Download PDF

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Publication number
KR20100124026A
KR20100124026A KR1020090043060A KR20090043060A KR20100124026A KR 20100124026 A KR20100124026 A KR 20100124026A KR 1020090043060 A KR1020090043060 A KR 1020090043060A KR 20090043060 A KR20090043060 A KR 20090043060A KR 20100124026 A KR20100124026 A KR 20100124026A
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South Korea
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semiconductor package
film
contact terminal
carrier body
carrier
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KR1020090043060A
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Korean (ko)
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KR101016327B1 (en
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김영웅
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주식회사 티에프이스트포스트
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Priority to KR1020090043060A priority Critical patent/KR101016327B1/en
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
    • G01R31/2863—Contacting devices, e.g. sockets, burn-in boards or mounting fixtures
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0433—Sockets for IC's or transistors
    • G01R1/0441—Details
    • G01R1/0466—Details concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2872—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation
    • G01R31/2879—Environmental, reliability or burn-in testing related to electrical or environmental aspects, e.g. temperature, humidity, vibration, nuclear radiation related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2896—Testing of IC packages; Test features related to IC packages

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Environmental & Geological Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

PURPOSE: An insert carrier of a semiconductor package is provided to simplify the structure of a semiconductor package mounting film by directly contacting the contact terminal of a semiconductor package to the conductive film of an external inspection apparatus through a contact terminal hole. CONSTITUTION: A carrier body(200) has a package fixing hole which is formed from top and bottom thereof. A latch is rotatable around a high pin on both inner wall of the package fixing hole. A latch open cover(400) is ascended from the carrier body. A semiconductor package mounting film(500) has a combination hole at four corners and is attached to the bottom of the package fixing hole of the carrier body. A bolt(600) holds the semiconductor mounting film in the carrier body.

Description

반도체패키지 인서트캐리어{Insert carrier of Semiconductor Package}Insert carrier of Semiconductor Package

본 발명은 반도체패키지 인서트캐리어에 관한 것으로서, 더욱 상세히는 반도체패키지의 전기적 검사를 용이하게 수행하기 위해서 반도체패키지가 놓이는 캐리어본체의 밑면에, 반도체패키지의 접촉단자보다 얇은 두께로 형성되고 접촉단자들과 대응되는 곳에 접촉단자홀이 형성되는 반도체패키지안착용필름을 부착시켜서 별도의 부재를 사용하지 않고 반도체패키지의 접촉단자로 직접 반도체패키지의 전기적 검사를 수행할 수 있도록 한 반도체패키지 인서트캐리어에 관한 것이다.The present invention relates to a semiconductor package insert carrier, and more particularly, to a bottom surface of a carrier body on which a semiconductor package is placed in order to easily conduct electrical inspection of the semiconductor package, and having a thinner thickness than that of the contact terminal of the semiconductor package. The present invention relates to a semiconductor package insert carrier for attaching a semiconductor package seating film having a contact terminal hole to a corresponding place so that electrical inspection of the semiconductor package can be performed directly to the contact terminal of the semiconductor package without using a separate member.

또한, 반도체패키지안착용필름 하부에 반도체패키지안착용필름의 사방 테두리를 받쳐주는 필름고정커버를 구비하여, 얇은 필름으로 형성되는 반도체패키지안착용필름의 처짐현상을 방지할 수 있도록 한 반도체패키지 인서트캐리어에 관한 것이다.In addition, a semiconductor package insert carrier having a film fixing cover that supports the edges of the semiconductor package seating film under the semiconductor package seating film to prevent sagging of the semiconductor package seating film formed into a thin film. It is about.

일반적으로 반도체패키지의 제조공정은 제조하고자 하는 반도체소자에 따라 조금씩 공정이 추가될 것이나, 기본적으로 18단계의 공통과정에 의하여 제조된다.In general, the manufacturing process of the semiconductor package will be added little by little depending on the semiconductor device to be manufactured, but is basically manufactured by a common process of 18 steps.

1단계는 단결정성장단계로 고순도로 정제된 실리콘 용융액에 시드(Seed) 결 정을 접촉하고 회전시키면서 단결정규소봉(Ingot)을 성장시키는 단계이고, 2단계는 규소봉절단로 성장된 규소봉을 균일한 두께의 얇은 웨이퍼로 잘라내는 단계, 3단계는 웨이퍼 표면연마단계로 웨이퍼의 한쪽면을 연마(Polishing)하여 거울면처럼 만들어주며, 이 연마된 면에 회로패턴을 형성하는 단계이며, 4단계로는 회로설계단계로 CAD(Computer Aided Design)시스템을 사용하여 전자회로와 실제 웨이퍼 위에 그려질 회로패턴을 설계하는 단계이다.The first step is to grow the single crystal silicon rods by contacting and rotating the seed crystals to the silicon melt, which is purified to high purity, in the single crystal growth step, and the second step is to uniformly grow the silicon rods grown by silicon rod cutting. In the step of cutting into a thin wafer of one thickness, step 3 is a step of polishing the surface of the wafer to make one surface of the wafer like a mirror surface, and to form a circuit pattern on the polished surface. In the circuit design stage, a CAD (Computer Aided Design) system is used to design a circuit pattern to be drawn on an electronic circuit and an actual wafer.

그리고 5단계는 마스크(Mask)제작단계로 설계된 회로패턴을 유리판 위에 그려 마스크를 만드는 단계이고, 6단계는 산화(Oxidation)공정단계로 800~1200℃의 고온에서 산소나 수증기를 실리콘 웨이퍼표면과 화학반응시켜 얇고 균일한 실리콘산화막(SiO2)을 형성하는 단계, 7단계로는 감광액 도포(Photo Resist Coating)단계로 빛에 민감한 물질인 감광액(PR)을 웨이퍼 표면에 고르게 도포시키는 단계이며, 8단계는 노광(Exposure)공정단계로 노광기(Stepper)를 사용하여 마스크에 그려진 회로패턴에 빛을 통과시켜 감광막이 형성된 웨이퍼 위에 회로패턴을 사진 찍는단계이다.The fifth step is to make a mask by drawing a circuit pattern designed as a mask manufacturing step on a glass plate, and the sixth step is an oxidation process step. Reacting to form a thin and uniform silicon oxide film (SiO2), Step 7 is a photo-resist coating step to apply a light-sensitive material (PR) evenly to the surface of the wafer, Step 8 An exposure process is a step in which a circuit pattern is photographed on a wafer on which a photoresist film is formed by passing light through a circuit pattern drawn on a mask using an exposure machine.

또 9단계는 현상(Development)공정단계로 웨이퍼 표면에서 빛을 받은 부분의 막을 현상시키는 단계이고, 10단계는 식각(Etching)공정단계로 회로패턴을 형성시켜 주기 위해 화학물질이나 반응성 가스를 사용하여 필요없는 부분을 선택적으로 제거시키는 공정단계, 11단계는 이온주입(Ion Implantation)공정단계로 회로패턴과 연결된 부분에 불순물을 미세한 가스입자 형태로 가속하여 웨이퍼의 내부에 침투시킴으로써 전자소자의 특성을 만들어 주며, 이러한 불순물주입은 고온의 전기로 속 에서 불순물입자를 웨이퍼 내부로 확산시켜 주입하는 확산공정에 의해서도 이루어지는 단계이다.In addition, Step 9 is a development process to develop a film of the lighted part on the wafer surface, and Step 10 is an etching process to use a chemical or reactive gas to form a circuit pattern. Process step for selectively removing unnecessary parts, step 11 is ion implantation process step to accelerate the impurities in the form of fine gas particles in the part connected to the circuit pattern to penetrate the inside of the wafer to make the characteristics of the electronic device The impurity injection is also a step performed by a diffusion process in which impurity particles are diffused into a wafer in a high temperature electric furnace.

그리고 12단계로 화학기상증착(CVD:Chemical Vapor Deposition)공정단계로 반응가스간의 화학반응으로 형성된 입자들을 웨이퍼표면에 증착하여 절연막이나 전도성막을 형성시키는 공정단계이고, 13단계는 금속배선(Metallization)공정단계로 웨이퍼 표면에 형성된 각 회로를 알루미늄선으로 연결시키는 공정단계, 14단계는 웨이퍼 자동선별(EDS Test)단계로 웨이퍼에 형성된 IC칩들의 전기적 동작여부를 컴퓨터로 검사하여 불량품을 자동선별단계이며, 15단계는 웨이퍼 절단(Sawing)단계로 웨이퍼상의 수많은 칩들을 분리하기 위해 다이아몬드 톱을 사용하여 웨이퍼를 전달하는 단계, 16단계는 칩 집착(Die Bonding)단계로 낱개로 분리되어 있는 칩 중 EDS 테스트에서 양품으로 판정된 칩을 리드 프레임 위에 붙이는 공정단계, 17단계는 금속연결(Wire Bonding)단계로 칩 내부의 외부연결단자와 리드프레임을 가는 금선으로 연결하여 주는 공정단계이고, 마지막으로 18단계은 성형(Molding)단계로 연결 금선 부분을 보호하기 위해 화학수지로 밀봉해 주는 공정으로 반도체소자가 최종적으로 완성된다.The chemical vapor deposition (CVD) process is carried out in 12 steps. A process of forming an insulating film or a conductive film by depositing particles formed by a chemical reaction between reaction gases on the wafer surface, and in step 13, a metallization process. Step 14 is a process of connecting each circuit formed on the wafer surface with an aluminum wire, and step 14 is an automatic wafer selection (EDS test) step, which checks the electrical operation of IC chips formed on the wafer by a computer, and automatically selects defective products. Step 15 is a wafer cutting step, in which a wafer is transferred using a diamond saw to separate a large number of chips on the wafer, and step 16 is a die bonding step, in an EDS test. The process step of attaching the chip judged as good on the lead frame, the step 17 is a wire bonding step to the outside of the chip inside The process of connecting the connection terminal and the lead frame with a thin gold wire. Finally, the 18th step is a molding step, in which a semiconductor device is finally completed by sealing with a chemical resin to protect the connection gold wire part.

이러한, 복잡한 공정을 거쳐 생산되는 반도체패키지는 반도체패키지에 형성되는 접촉단자를 통한 전기적 검사를 수행하게 되는 것이다.The semiconductor package produced through such a complicated process is to perform an electrical inspection through the contact terminal formed in the semiconductor package.

즉, 도 1 은 종래의 반도체패키지 인서트캐리어에 반도체패키지가 장착된 모습을 보여주는 단면도이고, 도 2 는 종래의 반도체패키지 인서트캐리어의 받침부재를 보여주는 요부확대도, 도 3 은 종래의 반도체패키지 인서트캐리어가 외부 검사 장비와 결합한 모습을 보여주는 단면도이다.That is, FIG. 1 is a cross-sectional view showing a state in which a semiconductor package is mounted on a conventional semiconductor package insert carrier. FIG. 2 is an enlarged view illustrating a supporting member of a conventional semiconductor package insert carrier. FIG. 3 is a conventional semiconductor package insert carrier. Is a cross-sectional view showing the combination with external inspection equipment.

이와 같은 반도체패키지(10)는 캐리어본체(20)에 장착되어 전기적 검사를 수행하게 되는데, 이때 반도체패키지(10) 밑면에 부착되는 받침부재(30)는 필름(31) 사이에 반도체패키지(10)의 접촉단자(15)와 대응되는 위치에 도전부(35)가 구비되어, 반도체패키지(10)의 접촉단자(15)와 외부의 검사장비(50)에 구비되는 전도성핀(55) 사이에서 전기적 신호를 전달하는 역할을 수행하게 되는 것이다. The semiconductor package 10 is mounted on the carrier body 20 to perform an electrical inspection. At this time, the supporting member 30 attached to the bottom surface of the semiconductor package 10 is a semiconductor package 10 between the films 31. The conductive portion 35 is provided at a position corresponding to the contact terminal 15 of the semiconductor package 10, and is electrically connected between the contact terminal 15 of the semiconductor package 10 and the conductive pin 55 provided in the external inspection equipment 50. It will play a role of transmitting a signal.

하지만, 이와 같은 반도체패키지 인서트캐리어는 다음과 같은 문제점이 있었다.However, such a semiconductor package insert carrier has the following problems.

즉, 반도체패키지 밑면에 부착되는 받침부재가 반도체패키지의 접촉단자와 외부 검사장비의 전도성핀 사이에서 전기적 신호를 전달하기 위하여, 접촉단자와 전도성핀의 대응되는 곳에 도전부가 구비되어야함으로써, 받침부재의 구조가 복잡해져 생산단가가 상승하고 작업능률이 떨어지는 문제점이 있었다,That is, in order for the support member attached to the bottom of the semiconductor package to transmit an electrical signal between the contact terminal of the semiconductor package and the conductive pin of the external inspection equipment, the conductive part must be provided at the corresponding position of the contact terminal and the conductive pin. Due to the complicated structure, there was a problem that the production cost increased and the work efficiency decreased.

또한, 받침부재의 구조가 복잡해져 반도체패키지의 전기적 검사를 수행할때In addition, the structure of the supporting member is complicated, and when performing the electrical inspection of the semiconductor package

오작동으로 인해 오류가 발생하는 문제점도 있었다.There was also a problem that an error occurs due to a malfunction.

따라서 본 발명의 목적은 반도체패키지의 전기적 검사를 용이하게 수행하기 위해서 반도체패키지가 놓이는 캐리어본체의 밑면에, 반도체패키지의 접촉단자보다 얇은 두께로 형성되고 접촉단자들과 대응되는 곳에 접촉단자홀이 형성되는 반도체 패키지안착용필름을 부착시켜서 별도의 부재를 사용하지 않고 반도체패키지의 접촉단자와 외부 검사장비의 전도성핀을 직접 접촉시켜 반도체패키지의 전기적 검사를 수행할 수 있도록 한 반도체패키지 인서트캐리어를 제공하는데 있다.Therefore, an object of the present invention is to form a thinner than the contact terminal of the semiconductor package, the contact terminal hole is formed on the bottom of the carrier body on which the semiconductor package is placed in order to facilitate the electrical inspection of the semiconductor package To provide a semiconductor package insert carrier by attaching a semiconductor package seating film attached to directly contact the contact terminal of the semiconductor package and the conductive pin of the external inspection equipment without using a separate member to perform electrical inspection of the semiconductor package. have.

또한, 반도체패키지의 접촉단자보다 얇은 두께의 필름으로 형성되는 반도체패키지안착용필름의 처짐현상을 방지할 수 있도록 반도체패키지안착용필름 하부에 반도체패키지안착용필름의 사방 테두리를 받쳐주는 필름고정커버를 구비한 반도체패키지 인서트캐리어를 제공하는데 있다.In addition, a film fixing cover that supports the edges of the semiconductor package mounting film on the lower portion of the semiconductor package mounting film to prevent sagging of the semiconductor package mounting film formed of a film thinner than the contact terminal of the semiconductor package. To provide a semiconductor package insert carrier provided.

이와 같은 본 발명은 반도체패키지의 전기적 검사를 수행하기 위하여, 반도체패키지가 놓이는 패키지고정홀이 중앙부위의 상부에서부터 하부까지 관통되어 형성된 캐리어본체와; 패키지고정홀의 양쪽 내벽에서 힌지핀을 중심으로 회동되게 설치되며, 반도체패키지의 공급 및 인출시 오픈되는 래치와; 캐리어본체 위에서 승강되게 설치되며, 하강시 래치를 오픈시키는 래치오픈커버; 로 반도체패키지를 운반하는 반도체패키지 인서트캐리어를 구성함에 있어서, 사방의 모서리 부위에 결합홀이 형성되어 캐리어본체의 패키지고정홀 밑면에 부착되고, 반도체패키지의 접촉단자들과 대응되는 곳에 접촉단자홀이 다수 형성되며, 접촉단자의 돌출 길이에 비해 얇은 두께로 형성되어 접촉단자가 돌출되게 끼워지는 반도체패키지안착용필름;과 반도체패키지안착용필름 사방의 결합홀에 끼워져 캐리어본체에 반도체패키지안착용필름을 고정시켜주는 볼트;로 이루어지며, 특히 반도체패키지안착용필름의 하부에 는, 반도체패키지안착용필름의 결합홀과 대응되는 곳에 고정홀이 형성되고, 반도체패키지안착용필름의 접촉단자홀이 있는 중앙 부위와 대응되는 곳은 관통되어 반도체패키지안착용필름의 사방 테두리를 받쳐주는 필름고정커버를 구비하여, 반도체패키지안착용필름의 처짐을 방지할 수 있도록 한 것이다.Such a present invention comprises: a carrier body formed by penetrating a package fixing hole in which a semiconductor package is placed from an upper portion to a lower portion thereof in order to perform an electrical inspection of the semiconductor package; A latch installed at both inner walls of the package fixing hole about the hinge pin and opened when the semiconductor package is supplied and withdrawn; A latch open cover installed to be elevated on a carrier body and opening a latch when descending; In constructing a semiconductor package insert carrier for carrying a semiconductor package, coupling holes are formed at four corners and attached to the bottom of the package fixing hole of the carrier body, and contact terminal holes correspond to the contact terminals of the semiconductor package. A plurality of semiconductor package seating film is formed, the thickness of the contact terminal is formed thinner than the protruding length of the contact terminal; The semiconductor package seating film and the semiconductor package seating film sandwiched in the coupling holes of the four sides of the semiconductor package seating film to the carrier body It consists of a bolt for fixing, in particular in the lower portion of the semiconductor package seating film, a fixing hole is formed in a portion corresponding to the bonding hole of the semiconductor package seating film, the center of the contact terminal hole of the semiconductor package seating film Film fixing cover that penetrates the corresponding area to support the edges of the semiconductor package mounting film It is provided with, to prevent sagging of the semiconductor package mounting film.

그리고, 반도체패키지안착용필름의 소재를 정전 처리된 필름으로 형성하여, 반도체패키지의 손상을 방지할 수 있도록 것을 하며, 반도체패키지안착용필름은, 표면저항을 10∧6 ~ 10∧9 의 범위 내로 형성하여 반도체패키지가 쇼트 및 과부하로부터 보호되게 하므로서 본 발명의 목적을 달성할 수 있는 것이다.Then, the worn not the semiconductor package forming material of the film to the electrostatic treatment film, and that to avoid damage to the semiconductor package, not the semiconductor package worn film, the surface resistance in the range of 10 ∧ 6 ~ 10 ∧ 9 It is possible to achieve the object of the present invention by forming a semiconductor package to be protected from short and overload.

이와 같은 본 발명은 반도체패키지를 운반하는 인서트캐리어 밑면에, 반도체패키지의 접촉단자보다 얇은 두께로 형성되며, 반도체패키지의 접촉단자와 대응되는 곳에 접촉단자홀이 형성되는 반도체패키지안착용필름을 부착하여, 반도체패키지의 접촉단자가 반도체패키지안착용필름의 접촉단자홀을 통해 외부 검사장비의 전도성핀에 직접 첩촉함으로써 반도체패키지안착용필름의 구조가 단순해져 생산단가를 낮추고 작업성을 향상시키며, 또한 오작동으로 인한 오류가 발생하는 것을 방지하는 효과가 있는 것이다. In the present invention as described above, a semiconductor package seating film is formed on a bottom surface of an insert carrier for carrying a semiconductor package, the thickness of which is thinner than that of the semiconductor package, and a contact terminal hole is formed at a position corresponding to the contact terminal of the semiconductor package. By contacting the contact terminal of the semiconductor package directly to the conductive pin of the external inspection equipment through the contact terminal hole of the semiconductor package seating film, the structure of the semiconductor package seating film is simplified, thereby lowering the production cost and improving workability. There is an effect to prevent the error caused by.

또한, 반도체패키지안착용필름 하부에 반도체패키지안착용필름의 사방 테두리를 받쳐주는 필름고정커버를 구비하여, 얇은 필름으로 형성되는 반도체패키지안 착용필름의 처짐현상을 방지하는 효과도 있는 것이다.In addition, there is a film fixing cover that supports the four sides of the semiconductor package mounting film on the lower portion of the semiconductor package mounting film, there is also an effect of preventing the sagging phenomenon of the semiconductor package wearing film formed of a thin film.

이하 본 발명의 특징을 효과적으로 달성할 수 있는 바람직한 실시 예로서 그 기술구성 및 작용효과를 첨부된 도면에 의하여 상세히 설명하면 다음과 같다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

즉, 도 4 는 본 발명에 따른 반도체패키지 인서트캐리어의 모습을 보여주는 분리사시도이고, 도 5 는 본 발명에 따른 반도체패키지 인서트캐리어의 구조를 보여주는 단면도, 도 6 은 본 발명에 따른 반도체패키지 인서트캐리어의 구조를 보여주는 요부확대도이며, 도 7 은 본 발명에 따른 반도체패키지 인서트캐리어의 구조를 보여주는 분리단면도, 도 8 은 본 발명에 따른 반도체패키지 인서트캐리어의 구조를 보여주는 조립단면도이다.That is, FIG. 4 is an exploded perspective view showing a shape of a semiconductor package insert carrier according to the present invention, FIG. 5 is a cross-sectional view showing the structure of a semiconductor package insert carrier according to the present invention, and FIG. 6 is a view of a semiconductor package insert carrier according to the present invention. 7 is an exploded cross-sectional view showing the structure of a semiconductor package insert carrier according to the present invention, and FIG. 8 is an assembled cross-sectional view showing the structure of a semiconductor package insert carrier according to the present invention.

이와 같은 본 발명은 반도체패키지(100)의 전기적 검사를 수행하기 위하여, 반도체패키지(100)가 놓이는 패키지고정홀(210)이 중앙부위의 상부에서부터 하부까지 관통되어 형성된 캐리어본체(200)와; 패키지고정홀(210)의 양쪽 내벽에서 힌지핀(310)을 중심으로 회동되게 설치되며, 반도체패키지(100)의 공급 및 인출시 오픈되는 래치(300)와; 캐리어본체(200) 위에서 승강되게 설치되며, 하강시 래치(300)를 오픈시키는 래치오픈커버(400); 로 반도체패키지(100)를 운반하는 반도체패키지 인서트캐리어를 구성함에 있어서, 사방의 모서리 부위에 결합홀(510)이 형성되어 캐리어본체(200)의 패키지고정홀(210) 밑면에 부착되고, 반도체패키지(100)의 접촉단자(150)들과 대응되는 곳에 접촉단자홀(520)이 다수 형성되며, 접촉단자(150)의 돌출 길이에 비해 얇은 두께로 형성되어 접촉단자(150)가 돌출되게 끼워지는 반도체패키지안착용필름(500);과 반도체패키지안착용필름(500) 사방의 결합홀(510)에 끼워져 캐리어본체(200)에 반도체패키지안착용필름(500)을 고정시켜주는 볼트(600);로 이루어진 것을 특징으로 하는 것이다.As described above, the present invention provides a carrier body 200 in which a package fixing hole 210 in which the semiconductor package 100 is placed is penetrated from an upper portion to a lower portion thereof in order to perform an electrical inspection of the semiconductor package 100; A latch 300 installed at both inner walls of the package fixing hole 210 so as to be pivoted about the hinge pins 310 and opened when the semiconductor package 100 is supplied and withdrawn; A latch open cover 400 installed above the carrier body 200 to open the latch 300 when descending; In constructing a semiconductor package insert carrier carrying the semiconductor package 100, coupling holes 510 are formed at four corners of the semiconductor package 100 to be attached to the bottom of the package fixing hole 210 of the carrier body 200. A plurality of contact terminal holes 520 are formed at positions corresponding to the contact terminals 150 of 100, and are formed to have a thickness thinner than the protruding length of the contact terminal 150 so that the contact terminals 150 are protruded. A semiconductor package mounting film 500; and a bolt 600 fixed to the coupling body 510 of the semiconductor package mounting film 500 to fix the semiconductor package mounting film 500 to the carrier body 200; It is characterized by consisting of.

그리고, 반도체패키지안착용필름(500)의 하부에는, 반도체패키지안착용필름(500)의 결합홀(510)과 대응되는 곳에 고정홀(710)이 형성되고, 반도체패키지안착용필름(500)의 접촉단자홀(520)이 있는 중앙 부위와 대응되는 곳은 관통되어 반도체패키지안착용필름(500)의 사방 테두리를 받쳐주는 필름고정커버(700)를 구비하여, 반도체패키지안착용필름(500)의 처짐을 방지할 수 있도록 하고, 반도체패키지안착용필름(500)의 소재를 정전 처리된 필름으로 형성하여, 반도체패키지(100)의 손상을 방지할 수 있도록 하며, 반도체패키지안착용필름(500)은, 표면저항을 10∧6 ~ 10∧9 의 범위 내로 형성하여 반도체패키지가 쇼트 및 과부하로부터 보호되게 한 것을 특징으로 하는 것이다.In addition, a fixing hole 710 is formed at a lower portion of the semiconductor package mounting film 500 to correspond to the coupling hole 510 of the semiconductor package mounting film 500. A portion corresponding to the center portion of the contact terminal hole 520 is provided with a film fixing cover 700 which penetrates and supports the edges of the semiconductor package seating film 500. It is possible to prevent sag, and by forming the material of the semiconductor package seating film 500 as an electrostatically treated film, to prevent damage to the semiconductor package 100, the semiconductor package seating film 500 In this case, the surface resistance is formed within the range of 10 ∧ 6 to 10 ∧ 9 so that the semiconductor package is protected from short and overload.

즉, 이와 같은 본 발명은 반도체패키지(100)의 전기적 검사를 수행하기 위해 반도체패키지(100)를 캐리어본체(200)에 형성되는 패키지고정홀(210)에 고정시키게 되는데, 패키지고정홀(210)의 양쪽 내벽에 힌지핀(310)을 중심으로 회동되게 설치되는 래치(300)에 의해 반도체패키지(100)가 캐리어본체(200)에 고정되는 것이다.That is, according to the present invention, the semiconductor package 100 is fixed to the package fixing hole 210 formed in the carrier body 200 in order to perform the electrical inspection of the semiconductor package 100. The package fixing hole 210 The semiconductor package 100 is fixed to the carrier body 200 by latches 300 which are installed on both inner walls of the hinge pins 310 so as to be rotated about the inner wall.

이때, 반도체패키지(100)를 캐리어본체(200)에 고정시키는 래치(300)는, 캐리어본체(200) 상부에서 승,하강되는 래치오픈커버(400)에 의해 개,폐되어 반도체 패키지(100)를 캐리어본체(200)에서 탈,부착하게 되는 것이다.At this time, the latch 300 for fixing the semiconductor package 100 to the carrier body 200 is opened and closed by a latch open cover 400 which is raised and lowered on the carrier body 200 and thus the semiconductor package 100. It will be attached to, detached from the carrier body 200.

이렇게, 캐리어본체(200)에 고정된 반도체패키지(100)는 캐리어본체(200) 밑면에 부착되는 반도체패키지안착용필름(500)을 통해 외부의 검사장비와 전기적 신호를 통해 이상유무를 점검하여햐 하는데, 반도체패키지안착용필름(500)에는 반도체패키지(100)의 접촉단자(150)와 대응되는 곳에 접촉단자홀(520)이 형성되어 있어서 별도의 전도체를 구비하지 않고 반도체패키지안착용필름(500)의 접촉단자홀(520)을 통해 반도체패키지(100)의 접촉단자(150)가 외부 검사장비의 전도성핀과 접촉하여 검사를 수행할 수 있게 되는 것이다.Thus, the semiconductor package 100 fixed to the carrier body 200 is to check the abnormality through the external inspection equipment and electrical signals through the semiconductor package seating film 500 attached to the carrier body 200 bottom. In the semiconductor package seating film 500, a contact terminal hole 520 is formed at a portion corresponding to the contact terminal 150 of the semiconductor package 100, so that the semiconductor package seating film 500 is not provided with a separate conductor. The contact terminal 150 of the semiconductor package 100 through the contact terminal hole 520 of the contact with the conductive pin of the external inspection equipment to be able to perform the inspection.

특히, 반도체패키지안착용필름(500)의 두께는 반도체패키지(100)의 접촉단자(150)의 돌출길이보다 얇은 두께로 형성되어 접촉단자(150)가 용이하게 반도체패키지안착용필름(500) 하부로 노출되어 외부 검사장비와 접촉할수 있게 되는 것이다.In particular, the thickness of the semiconductor package seating film 500 is formed to be thinner than the protruding length of the contact terminal 150 of the semiconductor package 100 so that the contact terminal 150 can be easily mounted on the bottom of the semiconductor package seating film 500. It will be exposed to the external inspection equipment.

이때, 반도체패키지안착용필름(500)의 소재를 정전 처리된 필름으로 형성하여 반도체패키지(100)의 전기적 검사를 수행하는 동안 반도체패키지(100)가 손상되는 것을 방지할 수 있게 되는 것이다.In this case, the semiconductor package mounting film 500 may be formed of an electrostatically treated film to prevent the semiconductor package 100 from being damaged during the electrical inspection of the semiconductor package 100.

그리고, 반도체패키지안착용필름(500)의 표면저항을 10∧6 ~ 10∧9 의 범위 내로 형성하여, 반도체패키지안착용필름(500)의 표면저항이 10∧6 이하일 경우 정전기가 반도체패키지안착용필름(500)을 너무 빨리 빠져나가 반도체패키지(100)가 전기적 쇼크를 받아서 기능을 상실하게되는 현상을 방지하게 되는 것이다.Then, the surface resistance of the semiconductor package seating film 500 is formed in the range of 10 ∧ 6 to 10 ∧ 9, and when the surface resistance of the semiconductor package seating film 500 is 10 ∧ 6 or less, static electricity is applied to the semiconductor package seating. The film 500 may be pulled out too quickly to prevent the semiconductor package 100 from receiving an electric shock and losing its function.

하지만, 이렇게 캐리어본체(200) 밑면에 부착되는 반도체패키지안착용필름(500)은 두께가 얇아서 하부로 처지게 되는데, 이러한 처짐현상을 방지하기 위해서 반도체패키지안착용필름(500) 하부에 반도체패키지안착용필름(500)의 사방 테두리를 받쳐주는 필름고정커버(700)를 설치하게 되는 것이다.However, the semiconductor package mounting film 500 attached to the bottom surface of the carrier body 200 is so thin that it sags to the bottom. In order to prevent such sagging, the semiconductor package is placed under the semiconductor package mounting film 500. The film fixing cover 700 supporting the four sides of the wearing film 500 is to be installed.

이때, 필름고정커버(700) 사방의 모서리에 형성되는 고정홀(710)과 반도체패키지안착용필름(500) 사방의 모서리에 형성되는 결합홀(510)을 볼트(600)로 관통하여 캐리어본체(200)에 고정결합하게 되는 것이다.At this time, the fixing body 710 formed in the four corners of the film fixing cover 700 and the coupling hole 510 formed in the corners of the semiconductor package seating film 500 through the bolt 600 through the carrier body ( It will be fixed to the 200).

도 1 은 종래의 반도체패키지 인서트캐리어에 반도체패키지가 장착된 모습을 보여주는 단면도.1 is a cross-sectional view showing a state in which a semiconductor package is mounted on a conventional semiconductor package insert carrier.

도 2 는 종래의 반도체패키지 인서트캐리어의 받침부재를 보여주는 요부확대도.2 is an enlarged view illustrating main parts of a supporting member of a conventional semiconductor package insert carrier.

도 3 은 종래의 반도체패키지 인서트캐리어가 외부 검사장비와 결합한 모습을 보여주는 단면도. 3 is a cross-sectional view showing a conventional semiconductor package insert carrier combined with an external inspection equipment.

도 4 는 본 발명에 따른 반도체패키지 인서트캐리어의 모습을 보여주는 분리사시도.Figure 4 is an exploded perspective view showing the appearance of a semiconductor package insert carrier according to the present invention.

도 5 는 본 발명에 따른 반도체패키지 인서트캐리어의 구조를 보여주는 단면도.5 is a cross-sectional view showing a structure of a semiconductor package insert carrier according to the present invention.

도 6 은 본 발명에 따른 반도체패키지 인서트캐리어의 구조를 보여주는 요부확대도.Figure 6 is an enlarged view showing the main structure of the semiconductor package insert carrier according to the present invention.

도 7 은 본 발명에 따른 반도체패키지 인서트캐리어의 구조를 보여주는 분리단면도.Figure 7 is an exploded cross-sectional view showing the structure of a semiconductor package insert carrier according to the present invention.

도 8 은 본 발명에 따른 반도체패키지 인서트캐리어의 구조를 보여주는 조립단면도.8 is an assembled cross-sectional view showing the structure of a semiconductor package insert carrier according to the present invention.

도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings

100 : 반도체패키지 150 : 접촉단자100: semiconductor package 150: contact terminal

200 : 캐리어본체 210 : 패키지고정홀200: carrier body 210: package fixing hole

300 : 래치 310 : 힌지핀300: latch 310: hinge pin

400 : 래치오픈커버 500 : 반도체패키지안착용필름400: latch open cover 500: semiconductor package mounting film

510 : 결합홀 520 : 접촉단자홀510: coupling hole 520: contact terminal hole

600 : 볼트 700 : 필름고정커버600: bolt 700: film fixing cover

710 : 고정홀 710: fixing hole

Claims (4)

반도체패키지(100)의 전기적 검사를 수행하기 위하여, In order to perform the electrical inspection of the semiconductor package 100, 반도체패키지(100)가 놓이는 패키지고정홀(210)이 중앙부위의 상부에서부터 하부까지 관통되어 형성된 캐리어본체(200)와;A carrier body 200 in which the package fixing hole 210 in which the semiconductor package 100 is placed penetrates from an upper portion to a lower portion of a central portion thereof; 패키지고정홀(210)의 양쪽 내벽에서 힌지핀(310)을 중심으로 회동되게 설치되며, 반도체패키지(100)의 공급 및 인출시 오픈되는 래치(300)와;A latch 300 installed at both inner walls of the package fixing hole 210 so as to be pivoted about the hinge pins 310 and opened when the semiconductor package 100 is supplied and withdrawn; 캐리어본체(200) 위에서 승강되게 설치되며, 하강시 래치(300)를 오픈시키는 래치오픈커버(400); 로 반도체패키지(100)를 운반하는 반도체패키지 인서트캐리어를 구성함에 있어서,A latch open cover 400 installed above the carrier body 200 to open the latch 300 when descending; In constructing a semiconductor package insert carrier for carrying the semiconductor package 100, 사방의 모서리 부위에 결합홀(510)이 형성되어 캐리어본체(200)의 패키지고정홀(210) 밑면에 부착되고, 반도체패키지(100)의 접촉단자(150)들과 대응되는 곳에 접촉단자홀(520)이 다수 형성되며, 접촉단자(150)의 돌출 길이에 비해 얇은 두께로 형성되어 접촉단자(150)가 돌출되게 끼워지는 반도체패키지안착용필름(500);과Coupling holes 510 are formed at the corners of the four sides, and are attached to the bottom of the package fixing hole 210 of the carrier body 200, and contact terminal holes corresponding to the contact terminals 150 of the semiconductor package 100. A plurality of 520 is formed, the semiconductor package seating film 500 is formed to a thickness thinner than the protruding length of the contact terminal 150 is fitted so that the contact terminal 150 protrudes; And 반도체패키지안착용필름(500) 사방의 결합홀(510)에 끼워져 캐리어본체(200)에 반도체패키지안착용필름(500)을 고정시켜주는 볼트(600);Bolts 600 for fixing the semiconductor package mounting film 500 to the carrier body 200 is inserted into the coupling hole 510 of the semiconductor package seating film 500; 로 이루어진 것을 특징으로 하는 반도체패키지 인서트캐리어.Semiconductor package insert carrier, characterized in that consisting of. 제 1 항에 있어서,The method of claim 1, 반도체패키지안착용필름(500)의 하부에는,In the lower portion of the semiconductor package mounting film 500, 반도체패키지안착용필름(500)의 결합홀(510)과 대응되는 곳에 고정홀(710)이 형성되고, 반도체패키지안착용필름(500)의 접촉단자홀(520)이 있는 중앙 부위와 대응되는 곳은 관통되어 반도체패키지안착용필름(500)의 사방 테두리를 받쳐주는 필름고정커버(700)를 구비하여,Where the fixing hole 710 is formed in a position corresponding to the coupling hole 510 of the semiconductor package mounting film 500, and the center portion where the contact terminal hole 520 of the semiconductor package mounting film 500 is located. Is penetrated is provided with a film fixing cover 700 for supporting the edges of the semiconductor package seating film 500, 반도체패키지안착용필름(500)의 처짐을 방지할 수 있도록 한 것을 특징으로 하는 반도체패키지 인서트캐리어.A semiconductor package insert carrier characterized in that to prevent sagging of the semiconductor package mounting film (500). 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 반도체패키지안착용필름(500)의 소재를 정전 처리된 필름으로 형성하여,By forming the material of the semiconductor package seating film 500 into an electrostatically treated film, 반도체패키지(100)의 손상을 방지할 수 있도록 것을 특징으로 하는 반도체패키지 인서트캐리어.Semiconductor package insert carrier, characterized in that to prevent damage to the semiconductor package (100). 제 1 항 또는 제 2 항에 있어서, The method according to claim 1 or 2, 반도체패키지안착용필름(500)은, Semiconductor package mounting film 500, 표면저항을 10∧6 ~ 10∧9 의 범위 내로 형성하여 반도체패키지가 쇼트 및 과부하로 부터 보호되게 한 것을 특징으로 하는 반도체패키지 인서트캐리어.A semiconductor package insert carrier characterized in that the semiconductor package is protected from short and overload by forming a surface resistance within the range of 10 ∧ 6 to 10 ∧ 9.
KR1020090043060A 2009-05-18 2009-05-18 Insert carrier of Semiconductor Package KR101016327B1 (en)

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101315444B1 (en) * 2012-06-14 2013-10-08 주식회사 오킨스전자 Semiconductor package carrier
KR101336649B1 (en) * 2012-04-17 2013-12-04 주식회사 티에프이 Insert carrier for testing semiconductor
KR200470387Y1 (en) * 2012-04-30 2013-12-11 세메스 주식회사 Semiconductor package socket
KR101345812B1 (en) * 2011-10-24 2014-01-10 주식회사 오킨스전자 Latch and the insert for loading semiconductor device comprising the same
KR101367926B1 (en) * 2012-08-31 2014-02-28 리노공업주식회사 A testing apparatus of the semiconductor device
KR20140057700A (en) * 2012-10-26 2014-05-14 (주)테크윙 Insert for test handler
KR20150063732A (en) * 2013-12-02 2015-06-10 세메스 주식회사 Insert assembly of test tray
KR20170014112A (en) * 2015-07-29 2017-02-08 삼성전자주식회사 Specimen holder

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101345812B1 (en) * 2011-10-24 2014-01-10 주식회사 오킨스전자 Latch and the insert for loading semiconductor device comprising the same
KR101336649B1 (en) * 2012-04-17 2013-12-04 주식회사 티에프이 Insert carrier for testing semiconductor
KR200470387Y1 (en) * 2012-04-30 2013-12-11 세메스 주식회사 Semiconductor package socket
KR101315444B1 (en) * 2012-06-14 2013-10-08 주식회사 오킨스전자 Semiconductor package carrier
KR101367926B1 (en) * 2012-08-31 2014-02-28 리노공업주식회사 A testing apparatus of the semiconductor device
KR20140057700A (en) * 2012-10-26 2014-05-14 (주)테크윙 Insert for test handler
CN106862093A (en) * 2012-10-26 2017-06-20 泰克元有限公司 Testing, sorting machine plug-in unit
KR20150063732A (en) * 2013-12-02 2015-06-10 세메스 주식회사 Insert assembly of test tray
KR20170014112A (en) * 2015-07-29 2017-02-08 삼성전자주식회사 Specimen holder

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