KR20100117799A - Overlay pattern and measuring method thereby - Google Patents

Abstract

PURPOSE: An overlay pattern and an overlay measuring method thereof are provided to accurately measure a misalignment with a nondestructive method by electrically measuring a first layer and a second layer. CONSTITUTION: A first layer(100) is used as a target layer. A second layer(110a,110b,110c,110d) is located on the first layer. The second layer measures the misalignment of the first layer. A first or a fourth terminal pattern is formed into the same metal material and the same size. The first or the fourth terminal pattern is located on the upper part of the first layer in order to minimize fringing influence and to improve accuracy.

Description

Overlay pattern and overlay measurement method using the same {OVERLAY PATTERN AND MEASURING METHOD THEREBY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an overlay pattern and an overlay measurement method capable of quickly and accurately measuring misalignment through an electrical measurement method.

In general, the photo process in the semiconductor manufacturing process is a process for drawing the circuit actually required on the wafer using a photo resist, and irradiates light to a photo mask or reticle on which the circuit pattern to be designed is drawn. By exposing and developing the photoresist applied on the wafer, a desired pattern can be formed on the wafer.

In addition, the overlay performed during the photo process is to accurately stack patterns formed in each layer in the process of forming each layer in the semiconductor device, which is one of the important processes in the photo process.

In other words, as the process progresses to the upper layer, the overlay process margin between each layer has a significant influence on the characteristics of the actual semiconductor device. In particular, as the size of the pattern is gradually reduced due to the improvement of photo lithography technology, the overlay margin also requires considerable precision.

1A and 1B are plan views illustrating overlay measurement patterns according to the prior art.

As shown in FIGS. 1A and 1B, the overlay box is used to confirm the alignment between the patterns of the front and back processes in the photolithography process, and the alignment of the center line 20 and the overlay box generated in the front and rear processes is used. By measuring, the degree of alignment of the before and after processes can be determined.

In the mask used in each step, an overlay box is drawn, and the overlay box formed in the previous process, that is, the outer box 10 becomes the mother of the reference key, and the overlay box formed in the subsequent process, that is, the inner box box) 12 becomes the son of the measurement key.

Here, by measuring the ratio of the distance between the inner side of the outer box 10 and the outer side of the inner box 12, the pattern displacement according to the overlay can be measured. That is, when the outer box 10 and the inner box 12 have a misalignment, the centerline 20 of the inner box 12 is moved to one side, and thus the centerline where the initial centerline 20 and the misalignment are generated. The difference of 21 is measured.

This conventional overlay measurement method has the advantage of automatically measuring the misalignment, while the cost increases because the expensive equipment must be purchased or retained.

The technical problem to be achieved by the present invention is to provide an overlay pattern and an overlay measuring method that can quickly and accurately measure the misalignment through an electrical measurement method.

An overlay pattern and an overlay measuring method according to an embodiment of the present invention for achieving the above object is an overlay for measuring the misalignment generated between the pattern of the previous process step and the pattern of the current process step in the semiconductor device manufacturing process A measurement pattern, comprising: a first layer having a rectangular shape and a center for measuring a misalignment located on an upper portion of the first layer so as to overlap a partial region of the first layer in a central portion of each side of the first layer; And a second layer including the first to fourth terminal patterns.

An overlay pattern and an overlay measuring method according to an embodiment of the present invention have the following effects.

Electrically measuring the first and second layers enables accurate measurement of miss alignments in a non-destructive manner without the need for additional equipment such as SEM without additional investment.

In addition, it is possible to find the physical misalignment value by measuring the misalignment between two layers electrically, and to determine the physical value based on the electrical value. It is easy and easy for bad analysis.

Hereinafter, the technical objects and features of the present invention will be apparent from the description of the accompanying drawings and the embodiments. Looking at the present invention in detail.

2 is a plan view illustrating an overlay measurement pattern according to the present invention.

The overlay measurement pattern illustrated in FIG. 2 is a square first layer 100 and second layers 110a, 110b, 110c and 110d positioned on the first layer 100 to measure a misalignment. It consists of. The second layers 110a, 110b, 110c, and 110d may be formed of bar-shaped first to fourth terminal patterns 110a, 110b, 110c, and 110d at the center of each side of the first layer 100, respectively. It is positioned to partially overlap with the first layer 100.

Here, the first layer 100 refers to a layer that is an alignment target as a target layer, and the second layers 110a, 110b, 110c, and 110d measure miss alignment of the first layer 100. Means a layer for

The first to fourth terminal patterns 110a, 110b, 110c, and 110d are formed of the same size and the same metal material, and an electrode is placed at the end to measure the capacitance value of the overlapped portion by electrical measurement. The first to fourth terminal patterns 110a, 110b, 110c, and 110d are not limited to one shape, such as a rectangular bar, but may have various shapes having an angle, that is, a rectangle, a triangle, and an arbitrary shape. It can also be formed in the form of bars. The first to fourth terminal patterns 110a, 110b, 110c, and 110d are used as the upper layer by being positioned on the first layer 100 to minimize fringing effects and to increase accuracy.

The overlapping portions of the terminal patterns 110a, 110b, 110c, and 110d and the first layer 100 are the first to fourth overlapping regions 112a, 112b, 112c, and 112d, respectively, and the same areas overlap each other. .

Each center line of each of the terminal patterns 110a, 110b, 110c, and 110d and the centerline of the first layer 100 are designed to coincide with the centerline of the reference line 130.

As such, when the first layer 100 coincides with the center line of the reference line 130 and there is no misalignment, the terminal patterns 110a, 110b, 110c, and 110d and the overlapping regions 112a, 112b, and 112c, respectively. , 112d) is the same as Equation (1).

C represents a capacitance value between the first layer 100 and each terminal pattern 110a, 110b, 110c, and 110d, and T1 to T4 represent the first to fourth terminal patterns 110a, 110b, 110c, and 110d. ). If there is no misalignment between the first layer 100 and the reference line 130, the areas of the overlap regions 112a, 112b, 112c, and 112d are the same, and thus the capacitance ratios may be the same.

3 is a plan view illustrating an overlay measurement pattern in which misalignment occurs.

As shown in FIG. 3, when the first layer 100 has a misalignment in the -X axis and the + Y axis based on the reference line 130, for example, the first terminal pattern 110a is the second layer. Since the area of the overlapping region overlapping the first layer 100 is larger than the terminal pattern 110b, capacitance values of the first terminal pattern 110a and the first layer 100 are greater than the second terminal pattern 110b and the first layer 100. It can be seen that it is larger than the capacitance value of the layer 100.

That is, C (T1) is larger than C (T2).

In addition, the capacitance of the third terminal pattern 110c and the first layer 100 is greater because the area of the overlapping region where the third terminal pattern 110c overlaps the first layer 100 is larger than that of the fourth terminal pattern 110d. It can be seen that the value is larger than the capacitance values of the fourth terminal pattern 100d and the first layer 100.

That is, C (T3) is larger than C (T4).

Therefore, it can be seen qualitatively that the misalignment occurs in the first layer 100 at the upper left side, that is, the quadrant 2, than the reference line.

As such, it can be seen by the following equation how much misalignment has occurred in the X-axis or the Y-axis according to the capacitance ratio.

Here, C represents a capacitance value between the first layer 100 and each terminal pattern 110a, 110b, 110c, and 110d, and T1 to T4 represent the first to fourth terminal patterns 110a, 110b, and 110c. , 110f), Cf is the edge capacitance value of the first layer 100 and the terminal patterns 110a, 110b, 110c, 110d, Cg is the ground capacitance value, W is each terminal The width of the pattern, L, represents the length of each terminal pattern overlapped with the first layer 100.

Here, since the values of Cf (T1) and Cf (T2) are the same, and the function values of C (T1, W1) and C (T2, W2) are the same, the difference between C (T1) and C (T2) is as follows. same.

Miss alignment is purely expressed as a change in L.

Equations 5 and 6 below are basic parallel plate capacitance equations. However, it is possible to calculate using other equations and simulations rather than being limited to such equations.

That is, equations (5) and (6) are the same as equations (7).

Where ε represents the dielectric constant and d represents the dielectric thickness.

The values of L1 and L2 are already known. If they are aligned properly, the value of L1 / L2 is 1, and if L1 / L2 is multiplied by L1, the misaligned distance can be known. At this time, if the ratio of L1 / L2 is 1 or more, it is misaligned to the + Y axis and less than 1 to the -Y axis.

The measurement of the value in which the misalignment is generated on the X-axis can be known by calculating the ratio of C (T3) / C (T4) as shown in Equation (7).

With C (T1) / C (T2) and C (T3) / C (T4) calculated in this way, the misaligned values in the Y-axis as well as the X-axis can be known quantitatively.

In this way, the first layer 100 and the second layer (110a, 110b, 110c, 110d) by measuring the electrical alignment can be accurately measured by the non-destructive method without using additional equipment such as SEM without additional investment .

In addition, it is possible to find the physical misalignment value by measuring the misalignment between two layers electrically, and to determine the physical value based on the electrical value. It is easy and easy for bad analysis.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1A and 1B are plan views illustrating overlay measurement patterns according to the prior art.

2 is a plan view illustrating an overlay measurement pattern according to the present invention.

3 is a plan view illustrating an overlay measurement pattern in which misalignment occurs.

Claims (7)

In the overlay pattern for measuring the misalignment generated between the pattern of the previous process step and the pattern of the current process step in the semiconductor device manufacturing process, The first layer of square shape, A second layer including a first to fourth terminal pattern positioned at an upper portion of the first layer to measure a misalignment in a central portion of each side of the first layer so as to overlap a partial region of the first layer; Overlay pattern characterized in that it comprises a. The method of claim 1, And the first to fourth terminal patterns are formed in any one of a rectangle, a triangle, and an arbitrary bar shape. The method of claim 1, And the first to fourth terminal patterns are formed of the same metal material at the same size. The method of claim 1, The misalignment value between the first layer and the second layer is expressed as C (T) = Cf (T) + C (T, W) + Cg (T, L), where C is the first layer and each terminal pattern. Is the capacitance value of and T is the first to fourth terminal pattern, Cf is the edge capacitance value of the first layer and each terminal pattern, Cg is the ground capacitance value, W Is the width of the first to fourth terminal patterns, L denotes the length of each terminal pattern superimposed with the first layer. In the overlay pattern for measuring the misalignment generated between the pattern of the previous process step and the pattern of the current process step in the semiconductor device manufacturing process, Forming a rectangular first layer such that the center and the center of the reference line coincide with each other; A second layer including a first to fourth terminal pattern positioned at an upper portion of the first layer to measure a misalignment in a central portion of each side of the first layer so as to overlap a partial region of the first layer; Forming step, And measuring a capacitance value between the first layer and the first to fourth terminal patterns to measure a center of the reference line and a misalignment degree of the first layer. The method of claim 5, The first to fourth terminal patterns are formed in one of rectangular, triangular, and arbitrary bar shapes, and are formed of the same metal material in the same size. The method of claim 5, The misalignment value between the first layer and the second layer is expressed as C (T) = Cf (T) + C (T, W) + Cg (T, L), where C is the first layer and each terminal pattern. Is the capacitance value of and T is the first to fourth terminal pattern, Cf is the edge capacitance value of the first layer and each terminal pattern, Cg is the ground capacitance value, W Is the width of the first to fourth terminal patterns, L denotes the length of each terminal pattern superimposed with the first layer.

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