KR20100111915A - Processor, multi-processor system and method for controlling access authority for shared memory in multi-processor system - Google Patents

Abstract

PURPOSE: A processor, a multi-processor system and a method for controlling access authority for shared memory in multi-processor system are provided to reduce the delay time for checking the access authority to a shared memory area by confirming the access authority by a first and second semaphore register included in the processor devices. CONSTITUTION: A semaphore register(131) stores the same data as data showing the access authority saved in a register(460). An access management unit(132) reads out data showing the access authority based on the access command about the common memory address offered from a processor(110) from the semaphore register. The access authority of the shared memory area is confirmed. The semaphore register is synchronized in the register included in the multi-port memory(400), and the data showing the access authority is recorded.

Description

Processor, Multi-processor System And Method For Controlling Access Authority For Shared Memory In Multi-processor System

The present invention relates to a multiprocessor system, and more particularly, to a processor device, a multiprocessor system, and a method of controlling shared memory access rights of a multiprocessor system capable of reducing an access delay time of a shared memory area.

Since the late 1990s, the mobile multimedia terminal market such as mobile phones, PDAs (Personal Digital Assistants), Portable Multimedia Players (PMPs), digital cameras, etc. has been rapidly developed, and in order to satisfy various needs of users as well as mobile communication functions. And playback of various multimedia data, such as games.

In order to support various functions as described above, a mobile multimedia terminal includes two or more processors, and each processor is implemented as a multiprocessor system in which each processor shares a memory area.

For example, a mobile multimedia terminal includes a baseband processor that performs a mobile communication function and an application processor for processing multimedia data, and performs data transmission and reception between two processors at high speed. It has dual port memory which can improve processing performance and reduce memory footprint.

1 is a block diagram showing the configuration of a general multiprocessor system.

Referring to FIG. 1, a multiprocessor system is mainly composed of a baseband processor 10, an application processor 20, and a dual port memory 30.

The dual port memory 30 may include a first dedicated memory area 31 dedicated to the baseband processor 10 through the first port 15, and an application processor 20 through the second port 25. A second dedicated memory area 33 used exclusively and a shared memory area 35 shared and used by the baseband processor 10 and the application processor 20 are included.

In addition, the dual port memory 30 ensures mutual exclusion of the baseband processor 10 and the application processor 20 to the shared memory area 35 and to ensure synchronized operation between the processors. And a synchronization control unit 36 for control. Here, the synchronization controller may be configured as a hardware semaphore.

The synchronization controller 36 includes a semaphore register 37 that stores access right information, an access right request command or a shared memory area 35 from the baseband processor 10 or the application processor 20 to the shared memory area 35. It is composed of an authorization request register (39) for storing information about the size and location of the data to be stored in the ()) and to be transmitted to the relative port.

When the baseband processor 10 writes to the authorization request register 39 through the first port 15, the application processor 20 reads through the second port 25. When the application processor 20 performs a write operation to the authorization request register 39 through the second port 25, the baseband processor 10 may perform a read operation through the first port 15. Do.

In addition, when a write operation is performed to the authority request register 39 through one of the first port 15 and the second port 25, an interrupt signal is generated at the other port accordingly. The data recorded in the authorization request register 39 is maintained until a read operation for the authorization request is performed through the generated port.

The conventional multiprocessor system obtains the access right to the shared memory area 35 through the synchronization control unit 36 of the dual port memory 30. Therefore, in order to obtain access to the shared memory area 35, a processor without access to the shared memory area 35 must first request the access right and then wait until the access right is acquired. It is a major obstacle in systems requiring high speed data processing and transmission.

FIG. 2 is a timing diagram illustrating a process of obtaining access right to a shared memory area of the multiprocessor system shown in FIG. 1. Represents the process of obtaining access rights.

Referring to FIG. 2, the first port reads a semaphore register at time t0 to check an access right to access a shared memory area. Since the second port has access rights to the shared memory area, the first port recognizes that there is no access right, and writes a message requesting access rights of the shared memory area to the authority request register at time t1.

As the first port writes an access request message to the authorization request register, an interrupt signal is generated to the second port, and the second port reads the message written to the authorization request register at time t2 corresponding to the generated interrupt signal. Check the authorization request register.

Then, at time t3, the second port releases access to the shared memory area and writes data corresponding to the release of access to the semaphore register.

At time t4, the first port reads the semaphore register to confirm the access right to the shared memory area, recognizes that the access right to the shared memory area has changed as a result, and accesses the shared memory area at time t5.

As a result, the first port attempts to access the shared memory area at time t0 to access the shared memory area at time t5. Therefore, the access delay time for the shared memory area of the first port is time t0 to t5.

In FIG. 2, the first port recognizes that the access right has been changed at time t4 after the access right to the shared memory region has been changed at time t3. Because it is unknown, the semaphore registers of the dual port memory are read repeatedly.

In addition, in FIG. 2, the execution of a plurality of instructions is indicated at one time interval, but since a plurality of clocks corresponding to an instruction execution cycle is required to substantially execute one instruction, the first port may access the shared memory region. The delay is so large that it can't be ignored. Since the process shown in FIG. 2 must be repeated every time the access to the shared memory area is attempted, the access delay time increases exponentially as the usage time of the shared memory area increases.

As shown in FIG. 2, the conventional multiprocessor system has a delay time caused by an unauthorized port reading a semaphore register to access a shared memory area, and an unlicensed port uses the shared memory area. There is a delay between waiting for access and requesting authorization, and an interrupt caused by an unauthorized port writing authorization request data to an authorization request register, causing the authorized port to read and write an authorization request register. As a result, there is a problem in that high-speed data processing becomes an obstacle.

Accordingly, a first object of the present invention is to provide a processor device capable of reducing an access delay time for a shared memory area.

It is also a second object of the present invention to provide a multiprocessor system capable of reducing access delay time for a shared memory area.

In addition, a third object of the present invention is to provide a shared memory access method of a multiprocessor system capable of reducing access delay time for a shared memory region.

A processor device according to an aspect of the present invention for achieving the first object of the present invention described above, accesses a multi-port memory having a shared memory area and a register for storing data representing access rights to the shared memory area. A processor device comprising: a processor executing an instruction, a semaphore register storing data identical to data representing an access right stored in the register, and an access instruction to the shared memory region provided from the processor; And an access manager that reads data representing the access right and checks the access right of the shared memory area. The semaphore register may record data indicating the access right in synchronization with the register provided in the multi-port memory. If it is determined that there is no access right to the shared memory area, the access manager may transmit a message requesting access right to the shared memory area to the multi-port memory. The access manager reads the data representing the access right from the register of the multi-port memory after requesting the access right to the shared memory area, and if the data indicating the access right is changed, the semaphore register. Can be written on. The processor device may further include an instruction storage unit in which instructions provided from the processor are sequentially stored. The access manager determines whether a command for accessing the shared memory area in the command storage unit while a predetermined command is executed, and determines that the command for accessing the shared memory area exists in the command storage unit. After the execution of the predetermined command is terminated, a message for requesting permission to access the shared memory area may be transmitted to the multi-port memory. The access manager may release the access right to the shared memory area when the command for accessing the shared memory area does not exist in the command storage unit after obtaining the access right to the shared memory area. In addition, the multi-processor system according to an aspect of the present invention for achieving the second object of the present invention is a shared memory area, a semaphore register that stores access rights data indicating access rights to the shared memory area and the shared memory area A dual-port memory having a permission request register for storing a message requesting access permission for the first access point, and a first semaphore register for storing the same data as the access right data in synchronization with the semaphore register; A first processor device configured to read the access right data from the register to check access rights to the shared memory area, and a second semaphore register configured to store the same data as the access right data in synchronization with the semaphore register; From the second semaphore register It reads out the access rights data and a second processor unit to determine the access to the shared memory region. If it is determined that there is no access right to the shared memory area, the first processor device may write a message requesting access right of the shared memory area to the right request register. The second processor device receives an interrupt signal indicating that a message has been written to the permission request register, checks a message written to the permission request register, and accesses the shared memory area to the semaphore register and the second semaphore register. You can record access rights data indicating the release of privileges. The first processor device reads the access right data from the semaphore register after requesting the access right to the shared memory area, and writes the changed access right data to the first semaphore register when the access right data is changed. Can be. The first processor device may further include a first instruction storage unit to sequentially store instructions provided from the first processor. The first processor device determines whether an instruction for accessing the shared memory area is present in the first instruction storage unit while a predetermined instruction is executed, and the instruction for accessing the shared memory region in the first instruction storage unit is determined. If it is determined to exist, after the execution of the predetermined command is terminated, a message requesting the access right to the shared memory area may be recorded in the authority request register. After the first processor device acquires the access right to the shared memory area and there is no command to access the shared memory area in the first command storage unit, the first processor device access indicating to release the access right to the shared memory area. Authorization data can be recorded. The second processor device may further include a second instruction storage unit in which instructions provided from the second processor are sequentially stored.

In addition, a shared memory access method of a multiprocessor system according to an aspect of the present invention for achieving a third object of the present invention is a shared memory of a multiprocessor system including a first processor device, a second processor device, and a dual port memory. In the access method, the first processor device to read the first semaphore register provided therein to determine the access rights to the shared memory area of the dual-port memory, and the access rights to the shared memory area does not have Requesting the dual port memory to access the shared memory area; and after the second processor checks the permission request register of the dual port memory, the semaphore register and the second processor provided in the dual port memory. A second semaphore register provided therein for the shared memory area. Recording data indicating one release of an access right; and acquiring, by the first processor, the semaphore register to obtain access to the shared memory area. If there is no access right to the shared memory area, requesting access rights to the shared memory area from the dual port memory may include requesting the shared memory area to a first instruction storage provided in the first processor device. It may be determined whether there is a command to access, and if there is a command to access the shared memory area in the first command storage, the access right to the shared memory area may be requested after the execution of the command currently being executed. have. In the method of accessing a shared memory of the multiprocessor system, after the first processor acquires an access right to the shared memory area, determining whether there is an instruction to access the shared memory area in the first command storage unit. And a semaphore register provided in the dual port memory and a first semaphore register in the first instruction storage unit, when the instruction for accessing the shared memory region does not exist. The method may further include recording.

According to the shared memory access method of the processor device, the multi-processor system and the multi-processor system as described above, the first processor device and the second processor device, respectively, the first semaphore register and the second synchronized with the semaphore register provided in the dual port memory Determining the first semaphore register and the second semaphore register included in the processor device for checking the authority of the shared memory area and including the semaphore register, respectively, reduces the delay time required for checking the access right to the shared memory area.

In addition, each of the first processor device and the second processor device may include a first instruction storage unit and a second instruction storage unit for storing a predetermined number of instructions, and if the instruction storage unit includes an instruction for accessing the shared memory region, the next instruction unit may include: By prefetching and requesting the access right before execution, the delay time waiting for access right after requesting access right to the shared memory area is reduced.

In addition, based on the access frequency of the shared memory area, the first processor device and the second processor device give the access priority to the shared memory area, and a processor device having a low access priority may store instructions stored in its instruction storage unit. By removing the access right only when there is no command to access the shared memory area, the delay time caused by frequent request and release of the shared memory area is reduced.

As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

When a component is said to be "connected" or "connected" to another component, it may be directly connected to or connected to that other component, but other components may be present in the middle. It should be understood. On the other hand, when a component is said to be "directly connected" or "directly connected" to another component, it should be understood that there is no other component in between.

The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art and shall not be construed in ideal or excessively formal meanings unless expressly defined in this application. Do not.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention. In the following description of the present invention, the same reference numerals are used for the same elements in the drawings, and redundant descriptions of the same elements will be omitted.

3 is a block diagram illustrating a configuration of a multiprocessor system according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the multiprocessor system may include a first processor device 100, a second processor device 200, and a dual port memory 400. The first processor device 100 accesses the dual port memory 400 through the first port 310, and the second processor device 200 accesses the dual port memory 400 through the second port 320. do.

The first processor device 100 may include a first processor 110 and a first access control unit 130, and the first access control unit 130 may include a first semaphore register 131 and a first access management unit 132. And the first external bus interface 139.

The first processor 110 may be configured as, for example, a baseband processor of a mobile communication terminal, and the first access control unit 130 may access the shared memory area 450 based on instructions provided from the first processor 110. Performs processes such as checking access rights, requesting access rights, and releasing access rights.

The first semaphore register 131 stores data representing an access right to the shared memory area 450 of the dual port memory 400.

The first semaphore register 131 may be configured with bits corresponding to the number of processor devices and / or the number of shared memory areas. For example, when two processor devices share a shared memory area, the first semaphore register 131 may be configured with one bit, and the access right data stored in the first semaphore register 131 is '0'. ', The first processor device 100 obtains the access right to the shared memory area 450, and if the access right data is' 1', the second processor device accesses the shared memory area 450. It may be configured to obtain a right.

In addition, the first semaphore register 131 is operated in synchronization with the semaphore register 461 of the dual port memory 400. Specifically, when the multiprocessor system is booted, the semaphore register 461 of the dual port memory 400 has a default value (for example, '1'), and the first semaphore register 131 also stores data stored in the semaphore register 461. Will have the same data (ie '1'). Thereafter, when the access right to the shared memory area 450 is changed, the same data is recorded in the semaphore register 461 and the first semaphore register 131 of the dual port memory 400.

The first access manager 132 performs a process such as requesting an access right for the shared memory area 450 of the dual port memory 400 and releasing the access right based on the command provided from the first processor 110.

For example, the first access manager 132 reads the access right data recorded in the first semaphore register 131 when a command for instructing access to the shared memory area 450 is provided from the first processor 110. The access authority for the shared memory region 450 is determined, and if it is determined that there is no access authority, the shared memory region 450 is stored in the authority request register 463 of the dual port memory 400 through the first port 310. Record the message requesting the access rights of.

The first external bus interface 139 serves as a kind of memory controller and may be configured as a synchronous DRAM (SDRAM) or a pseudo SRAM (PSRAM) external bus interface.

The second processor device 200 may include a second processor 210 and a second access control unit 230, and the second access control unit 230 may include a second semaphore register 231 and a second access management unit 232. ) And a second external bus interface 239.

The second processor 210 may be, for example, an application processor of a mobile communication terminal, and the second access control unit 230 may perform an operation on the shared memory area 450 based on instructions provided from the second processor 210. Performs processes such as checking access rights, requesting access rights and canceling access rights.

The second semaphore register 231 stores data representing an access right to the shared memory area 450 of the dual port memory 400.

The second semaphore register 231 may be configured with the same bits as the first semaphore register 131 and the semaphore register 461, and operate in synchronization with the semaphore register 461.

The second access manager 232 performs a process such as requesting an access right for the shared memory area 450 of the dual port memory 400 and releasing the access right based on a command provided from the second processor 210.

For example, the second access manager 232 receives the access right data recorded in the second semaphore register 231 when a command for instructing access to the shared memory area 450 is provided from the second processor 210. Read and determine the access right to the shared memory area 450, if it is determined that there is no access right through the second port 320 in the permission request register 463 of the dual port memory 400 shared memory area 450 Record a message requesting permission to access).

The second external bus interface 139 serves as a kind of memory controller and may be configured as an SDRAM or PSRAM external bus interface.

The dual port memory 400 includes a first memory interface 410, a second memory interface 420, a first dedicated memory area 430, a second dedicated memory area 440, a shared memory area 450, and a synchronization controller. 460.

The first memory interface 410 and the second memory interface 420 may be configured as SDRAM or PSRAM interfaces, respectively, and may include a command decoder, a row decoder, a column decoder, an input / output buffer, and the like corresponding to each interface. .

The first memory interface 410 and the second memory interface 420 receive an address, a control signal, a clock, and data through corresponding ports, respectively, and decode the address into a row address and a column address to perform a read or write operation. The memory area to be determined is determined, and data is read from or written to the predetermined memory area in accordance with an operation timing such as reading, writing, and refreshing the predetermined memory area.

The first dedicated memory area 430 is a memory area that the first processor device 100 can access exclusively through the first port 310, and the second dedicated memory area 440 is the second processor device 200. ) Is a memory region that can be accessed exclusively through the second port 320.

In addition, the shared memory area 450 is a memory area accessible by the first processor device 100 and the second processor device 200 through the first port 310 and the second port 320, respectively. In order to prevent an access conflict between the first processor device 100 and the second processor device 200, mutually exclusive access should be guaranteed.

The first dedicated memory area 430, the second dedicated memory area 440, and the shared memory area 450 may each have a unit memory cell structure of a DRAM, and may be configured in bank units having a predetermined size. have. Alternatively, each memory area may be configured in block units having a predetermined size in one bank.

The synchronization controller 460 is to ensure mutually exclusive access of the first processor device 100 and the second processor device 200 to the shared memory area 450 and includes a semaphore register 461 and a permission request register 463. ) May be included.

The semaphore register 461 operates in synchronization with the first semaphore register 131 of the first processor device 100 and the second semaphore register 231 of the second processor device 200, and operates in the shared memory area 450. Access rights data indicating access rights is stored.

The authorization request register 463 may consist of certain bits (eg, 32 bits) and is used for the transmission of short messages or instructions. For example, the permission request register 463 may include a message for requesting access to the shared memory area 450 or information about the size and location of data stored in the shared memory area 450 to be transmitted to the counterpart processor device. Is recorded.

FIG. 4 is a timing diagram illustrating an operation process of the multiprocessor system illustrated in FIG. 3, and illustrates an operation of a processor device that obtains an access right to a shared memory area compared with a conventional multiprocessor system.

In FIG. 4, a processor that obtains access to a shared memory region sequentially executes a first instruction, a second instruction, a third instruction, and a fourth instruction, as shown in FIG. And the third command performs access to the dedicated memory area, and the second command and fourth command perform access to the shared memory area.

First, a conventional processor that does not have a semaphore register synchronized with a semaphore register of a dual-port memory in the processor device is time t1 and time for executing the second and fourth instructions as shown in FIG. At t4, we need to check the access rights data recorded in the semaphore register of the dual port memory.

However, in the multiprocessor system according to the exemplary embodiment of the present invention, since the processor device includes a semaphore register synchronized with the semaphore register of the dual port memory, the dual device accesses and accesses the dual port memory to confirm the access right to the shared memory area. It is not necessary to check the authority, only the semaphore registers provided in the processor device need to be checked, which reduces the delay time for checking the access right to the shared memory area.

As shown in (b) of FIG. 4, in the multiprocessor system according to an embodiment of the present invention, since the processor device includes a semaphore register synchronized with the semaphore register of the dual port memory, the access right to the shared memory area is checked. The delay time for doing so can be drastically reduced.

FIG. 5 is a timing diagram illustrating a semaphore register synchronization process of the multiprocessor system of FIG. 3. In FIG. 5, it is assumed that when the access right data stored in the semaphore register is '1', the first processor device acquires the access right, and when it is '0', the second processor device acquires the access right. In addition, when the multiprocessor system is booted, it is assumed that the semaphore register has a default value of '1' (that is, the second processor device obtains access authority) as access authority data.

Referring to FIG. 5, when the multiprocessor system is booted, the semaphore register of the dual port memory, the first semaphore register of the first processor device, and the second semaphore register of the second processor device are synchronized to '1', which is the access right data by default. do.

Subsequently, at time t0, the first processor device checks the first semaphore register to access the shared memory area, confirms that there is no access right, and requests permission of the dual port memory through the first port. Write to register.

An interrupt signal is provided to the second processor device due to the writing of the authorization request register, and correspondingly, at time t1, the second processor device reads the authorization request register through the second port to write an authorization request message recorded by the first processor device. Check it. Here, the interrupt signal indicates that a message has been written to the authority request register.

Subsequently, at time t2, the second processor device writes '0' in the semaphore register of the dual port memory to change the access right data from '1' to '0' to change the access right of the second processor device to the shared memory area. Release it.

As described above, when the access right data stored in the semaphore register is changed, the second semaphore register is also synchronized with the semaphore register of the dual port memory at time t3 to change the access right data to '0'.

The first processor device reads the semaphore register of the dual port memory at time t3 and confirms that the access right data is '0'. At time t4, '0' is written to the first semaphore register, and access to the shared memory area is performed.

As shown in FIG. 5, in a multiprocessor system according to an exemplary embodiment of the present invention, a processor device that obtains an access right to a shared memory area corresponds to a semaphore register of a dual port memory and its semaphore register. The access authority is released by recording the data, and the processor device without the access authority reads the semaphore register of the dual port memory according to the instruction operation cycle to check the access authority, and then changes the value of the semaphore register of the dual port memory. Synchronizes the register with the semaphore register provided in each processor device.

FIG. 6 is a block diagram illustrating a configuration of a multiprocessor system according to another exemplary embodiment of the present invention, and the same reference numerals are used for components that perform the same functions as the components of the multiprocessor system illustrated in FIG. 3.

Referring to FIG. 6, a multiprocessor system according to another embodiment of the present invention may include a first processor device 100, a second processor device 200, and a dual port memory 400.

The first processor device 100 may include a first processor 110 and a first access control unit 130a, and the first access control unit 130 may include a first semaphore register 131 and a first access management unit 132. ), A first command storage unit 133, and a first external bus interface 139.

The first processor 110 may be configured as, for example, a baseband processor of a mobile communication terminal.

The first access controller 130a performs a process such as checking an access right on the shared memory area 450, requesting an access right, and releasing an access right based on the instructions provided from the first processor 110.

In addition, the first access controller 130a temporarily stores the instructions provided from the first processor 110 and prefetches and processes the instructions related to the access of the shared memory region among the temporarily stored instructions, thereby processing the shared memory region. Reduce access wait time.

Since the first semaphore register 131 and the first external bus interface 139 perform the same functions as those shown and described with reference to FIG. 3, description thereof will be omitted to avoid duplication.

The first access manager 132 performs a process such as requesting an access right for the shared memory area 450 of the dual port memory 400 and releasing the access right based on the command provided from the first processor 110.

For example, the first access manager 132 determines whether there is a command for accessing the shared memory area 450 among the commands stored in the first command storage 133, and determines whether the command accesses the shared memory area 450. If it is determined that an access command exists, the access information for the shared memory area 450 is read by reading the first semaphore register 131, and if there is no access right, the access request is requested after the currently executed command. Message is written to the authority request register 463 of the dual port memory 400 through the first port 310.

The first instruction storage unit 133 may be configured as a queue in which instructions provided from the first processor 110 are sequentially stored. In this case, the command provided from the first processor 110 may be stored in the first command storage unit 133 and transmitted to the dual port memory through the first external bus interface 139. . The processor device according to another embodiment of the present invention assumes that the first instruction storage unit 133 has a size that can store four instructions.

The second processor device 200 may include a second processor 210 and a second access controller 230a, and the second access controller 230a may include a second semaphore register 231 and a second access manager 232. ), A second command storage unit 233, and a second external bus interface 239.

The second processor 210 may be, for example, an application processor of a mobile communication terminal.

The second access controller 230a performs a process such as checking an access right on the shared memory area 450, requesting an access right, and releasing an access right based on the command provided from the second processor 210.

In addition, the second access controller 230a temporarily stores the instructions provided from the second processor 210 and prefetches and processes the instructions related to the access of the shared memory region among the temporarily stored instructions, thereby accessing the shared memory region. Decreases.

Since the second semaphore register 231 and the first external bus interface 239 each perform the same functions as shown and described with reference to FIG. 3, description thereof will be omitted to avoid duplication.

The second access manager 232 performs a process such as requesting an access right for the shared memory area 450 of the dual port memory 400 and releasing the access right based on a command provided from the second processor 210.

For example, the second access manager 232 determines whether there is a command for accessing the shared memory area 450 among the commands stored in the second command storage unit 233, and determines whether the command is for the shared memory area 450. If it is determined that the access command exists, the second semaphore register 231 is read to check the access right to the shared memory area 450, and if there is no access right, the access right is next to the currently executed command. The request message is recorded in the authority request register 463 of the dual port memory 400 through the second port 320.

The second instruction storage unit 233 may be configured as a queue in which instructions provided from the second processor 210 are sequentially stored. Here, the second instruction storage unit 233 may be configured to have a size capable of temporarily storing four instructions from among instructions provided from the second processor 210.

The dual port memory 400 includes the same components as shown and described in FIG. 3, and each component performs the same function as the components of the same reference numeral shown in FIG. Omit.

FIG. 7 is a timing diagram illustrating an operation of a multiprocessor system according to another exemplary embodiment of the present invention illustrated in FIG. 6, and compares a shared memory access delay time with a conventional multiprocessor system that does not use prefetch. For convenience of explanation, it is assumed that the operation shown in FIG. 7 is performed in the first processor device, and the first processor device does not have an access right to the shared memory area.

Referring to FIG. 7A, the first to fourth instructions are sequentially stored in the first instruction storage unit 133 in the order provided by the first processor 110, and the first instruction at time t0. Is being performed. Herein, the first to third commands are commands for accessing the first dedicated memory area 430 of the dual port memory 400, and the fourth commands are commands for accessing the shared memory area 450.

First, a conventional multiprocessor system that does not perform prefetch sequentially executes the first instruction, the second instruction, and the third instruction from time t0 to t3 in the order stored in the queue, and then performs the fourth instruction. At the time t4, the authority request message is written to the authority request register 463, waits for the time when the access authority is changed (that is, t4 to t5), and at the time t5, the semaphore register 461 is read to check the access authority. When the access right is obtained, the fourth command is performed at time t6.

In contrast, in the multiprocessor system according to another exemplary embodiment of the present invention, the shared memory area 450 of the instructions stored in the first instruction storage unit 133 by the first access manager 132 while executing the first instruction at time t0. ), After checking the existence of the command (i.e., the fourth command) and executing the first command, before the execution of the second command, an access permission request message for executing the fourth command to the permission request register 463. Record it.

Thereafter, after executing the second and third instructions at times t2 and t3, the semaphore register 461 is read at time t4 to check the access right to the shared memory area 450, and at time t5, the fourth instruction is read. Perform

That is, in the multiprocessor system according to another exemplary embodiment of the present invention, when there is an instruction for accessing the shared memory area 450 by examining the first instruction storage unit 133 during execution of the first instruction, Before execution, the access permission of the shared memory area 450 is first requested, and then subsequent commands (ie, second and third commands) are sequentially executed. In addition, the first processor device accesses the shared memory area because the second processor device releases the authority for the shared memory area during the time of executing the second command and the third command by the method as shown in FIG. 5. Access rights can be obtained without additional waiting time.

FIG. 8 is a timing diagram illustrating a method of automatically releasing the shared memory access right of the multiprocessor system illustrated in FIG. 6, and illustrates a method of releasing the access right by the processor device having obtained the access right to the shared memory area. For convenience of explanation, it is assumed that the operation illustrated in FIG. 8 is performed in the first processor device, and the first processor device is in a state in which an access right to the shared memory area is acquired.

Referring to FIG. 8A, the first to fourth instructions are sequentially stored in the first instruction storage unit 133 in the order provided by the first processor 110, and the first instruction at time t0. Is running. In addition, only the first command among the commands stored in the first command storage unit 133 is a command for accessing the shared memory area, and the second to fourth commands are commands for accessing the first dedicated memory area 430.

In this case, since the first access management unit 132 has no instruction to access the shared memory area 450 in addition to the first instruction currently executed in the first instruction storage unit 133, the execution of the first instruction is completed. After that, at the time t2, the access right to the shared memory area 450 is released, and the second to fourth commands are sequentially executed from the time t2.

In FIG. 8B, the first to fourth instructions are sequentially stored in the first instruction storage unit 133, and the first instruction to access the shared memory area 450 is executed at time t0. In addition to the first command, a fourth command for accessing the shared memory area is stored after the second command and the third command.

As illustrated in (b) of FIG. 8, when a command for accessing the shared memory area 450 is stored in addition to the command currently executed in the first command storage unit 133, the first access manager 132 may be used. After performing a command for accessing all the shared memory areas 450 stored in the first command storage unit 133, the access permission for the shared memory area 450 is released.

That is, the first access manager 132 releases the access right to the shared memory area 450 at time t4 after performing the first to fourth commands from time t0 to time t4. Herein, in order to release the access right to the shared memory area 450, the first access manager 132 instructs the semaphore register 461 and the first semaphore register 131 to release the access right in the same manner as illustrated in FIG. 5. Can be performed by recording data.

As shown in FIG. 8, in a multiprocessor system according to another exemplary embodiment of the present invention, a processor device having a high frequency of using a shared memory area (eg, a second processor device) in order to reduce a delay time caused by an access permission request. By assigning a high priority to the shared memory area to give priority to the shared memory area, and a low priority processor device (for example, the first processor device) obtained by requesting the access right to the shared memory area After the access to the shared memory area is finished, the access right is automatically released.

In addition, when the low priority processor device frequently executes the release of access to the shared memory area, an interrupt occurs frequently in the corresponding high priority processor device, which causes an additional delay.

Therefore, in the present invention, when a processor device having a lower priority wants to release the access right to the shared memory area, the processor device first checks the instruction storage unit in which the command is stored and then accesses the shared memory area. By automatically releasing the access right, it prevents the delay due to frequent request and release of access to the shared memory area.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

1 is a block diagram showing the configuration of a general multiprocessor system.

FIG. 2 is a timing diagram illustrating a process of obtaining access rights to a shared memory area of the multiprocessor system shown in FIG. 1.

3 is a block diagram illustrating a configuration of a multiprocessor system according to an exemplary embodiment of the present invention.

4 is a timing diagram illustrating an operation process of the multiprocessor system illustrated in FIG. 3.

FIG. 5 is a timing diagram illustrating a semaphore register synchronization process of the multiprocessor system of FIG. 3.

6 is a block diagram illustrating a configuration of a multiprocessor system according to another exemplary embodiment of the present invention.

FIG. 7 is a timing diagram illustrating an operation of a multiprocessor system according to another exemplary embodiment of the present invention illustrated in FIG. 6.

FIG. 8 is a timing diagram illustrating a method of automatically releasing a shared memory access right of the multiprocessor system shown in FIG. 6.

<Explanation of symbols for the main parts of the drawings>

110: first processor 131: first semaphore register

132: first access management unit 133: first command storage unit

139: first external bus interface 210: second processor

231: second semaphore register 232: second access management unit

233: second command storage unit 239: second external bus interface

310: first port 320: second port

400: Dual Port Memory 450: Shared Memory Area

461: semaphore register 463: permission request register

Claims (18)

A processor device for accessing a multi-port memory having a shared memory area and a register storing data representing access rights to the shared memory area, A processor that executes instructions; A semaphore register in which data identical to data representing an access right stored in the register is stored; And And an access manager configured to read data representing the access authority from the semaphore register based on an access instruction to the shared memory region provided from the processor to confirm access authority of the shared memory region. The method of claim 1, wherein the semaphore register And the data indicative of the access right is synchronized with the register provided in the multi-port memory. The method of claim 1, wherein the access management unit And when it is determined that there is no access right to the shared memory area, transmitting a message requesting access right to the shared memory area to the multi-port memory. The method of claim 1, wherein the access management unit After requesting an access right to the shared memory area, data representing the access right is read from the register of the multi-port memory, and if the data representing the access right is changed, the changed data is written to the semaphore register. Processor unit. The system of claim 1, wherein the processor device is And an instruction storage unit for sequentially storing instructions provided from the processor. The method of claim 5, wherein the access management unit The command storage unit determines whether a command for accessing the shared memory area exists while the command storage unit is executed, and if it is determined that the command for accessing the shared memory area exists in the command storage unit, the command And after the execution of the processor is terminated, transmitting a message requesting access to the shared memory area to the multi-port memory. The method of claim 5, wherein the access management unit And acquiring the access right to the shared memory area if the command for accessing the shared memory area does not exist in the command storage unit after acquiring the access right to the shared memory area. A dual port memory having a shared memory region, a semaphore register storing access authority data representing access authority to the shared memory region, and an authority request register storing a message requesting access authority to the shared memory region; A first semaphore register configured to store the same data as the access right data in synchronization with the semaphore register, and to read the access right data from the first semaphore register to confirm access right to the shared memory area. A processor device; And A second semaphore register configured to store the same data as the access right data in synchronization with the semaphore register, and to read the access right data from the second semaphore register to confirm access right to the shared memory area. A multiprocessor system comprising a processor unit. The method of claim 8, wherein the first processor device is And if it is determined that there is no access right to the shared memory area, writing a message requesting access right of the shared memory area to the permission request register. The method of claim 8, wherein the second processor device is An access signal indicating an release of an access right to the shared memory area from the semaphore register and the second semaphore register after receiving an interrupt signal indicating that a message has been written to the authority request register; Multiprocessor system, characterized in that recording data. The method of claim 8, wherein the first processor device is Multi-processor characterized by reading the access right data from the semaphore register after requesting the access right to the shared memory area, and writing the changed access right data to the first semaphore register if the access right data is changed. system. The method of claim 8, wherein the first processor device is And a first instruction storage configured to sequentially store instructions provided from the first processor. The method of claim 12, wherein the first processor device is When the first command storage unit determines whether a command for accessing the shared memory area exists while a predetermined command is executed, and when it is determined that the command for accessing the shared memory area exists in the first command storage unit. And after the execution of the predetermined instruction is terminated, writes a message requesting access authority to the shared memory area in the authority request register. The method of claim 12, wherein the first processor device is After acquiring the access right to the shared memory area, if the command for accessing the shared memory area does not exist in the first command storage, recording access right data indicating the release of the access right to the shared memory area. Characterized in a multiprocessor system. The method of claim 8, wherein the second processor device is And a second instruction storage unit configured to sequentially store instructions provided from the second processor. In the shared memory access method of a multiprocessor system including a first processor device, a second processor device and a dual port memory, Reading, by the first processor device, a first semaphore register provided therein to determine an access right to a shared memory area of the dual port memory; Requesting access rights to the shared memory area from the dual port memory when there is no access right to the shared memory area; After the second processor checks the authorization request register of the dual port memory, the semaphore register provided in the dual port memory and the second semaphore register provided in the second processor indicate release of an access right to the shared memory area. Recording data; And And acquiring, by the first processor, the semaphore register to obtain an access right to the shared memory area. The method of claim 16, wherein the requesting for the access right to the shared memory area from the dual port memory when the access right to the shared memory area is not performed comprises: It is determined whether there is an instruction for accessing the shared memory region in the first instruction storage unit provided in the first processor device, and if the instruction for accessing the shared memory region in the first instruction storage unit exists, And requesting permission to access the shared memory area after the execution of the command being executed. 18. The method of claim 17, wherein the shared memory access method of the multiprocessor system Determining, by the first processor, that an instruction for accessing the shared memory area exists in the first instruction storage unit after acquiring an access right for the shared memory area; And When there is no command to access the shared memory area in the first command storage unit, data indicating the release of access to the shared memory area is recorded in the semaphore register and the first semaphore register provided in the dual port memory. Shared memory access method of a multiprocessor system, characterized in that it further comprises the step of.

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