KR20100079012A

KR20100079012A - Method for manufacturing of semiconductor device

Info

Publication number: KR20100079012A
Application number: KR1020080137411A
Authority: KR
Inventors: 신현수
Original assignee: 주식회사 동부하이텍
Priority date: 2008-12-30
Filing date: 2008-12-30
Publication date: 2010-07-08

Abstract

PURPOSE: A manufacturing method of the semiconductor device injects the P+ dopant into the area in which the ESD(Electro Static Discharge) protecting element of the top of the substrate is formed. The RDSON property is maximized without the separate dopant implant. CONSTITUTION: A substrate(100) is classified into the second part for the first area(110) for the semiconductor element formation and ESD protecting circuit formation. The trench(112b) is formed in the first area. The ESD poly film(151) is formed on the first area and the second part in which the trench accomplishes. The P+ dopant for the P+ domain formation is inserted on the top of the second part. The N+ dopant for the area-source formation is inserted in the first area and the second part. The Zener diode is formed on the domain in which the N+ dopant of the second part and the first area is inserted.

Description

Method for manufacturing a semiconductor device

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device including an electrostatic discharge (ESD) protection device.

In general, when a semiconductor device is exposed to an electrostatic discharge, the internal circuit is damaged, resulting in a malfunction of the device or a problem in reliability.

This damage to the internal circuit is caused by junction spiking where it is vulnerable due to Joule heat caused by charge injected through the input terminal during electrostatic discharge and finally exiting the other circuit through the internal circuit. This is because an oxide film rupture phenomenon occurs.

Therefore, in order to solve this problem, it is necessary to insert an electrostatic discharge protection circuit capable of discharging the injected charge directly to the power supply terminal before the injected charge is discharged through the internal circuit. This can be prevented.

Therefore, the semiconductor device is provided with an electrostatic discharge (hereinafter referred to as "ESD") protection element for protecting the electrostatic discharge as described above.

A process of forming the ESD protection device as described above will be briefly described.

That is, the semiconductor substrate is defined as a first region where a semiconductor element is formed and a second region where the ESD protection element is formed.

Next, a trench is completed in the first region, and ESD poly is deposited on the entire substrate including the first region in which the trench is completed.

Next, a P + dopant for forming a P + region is implanted into the entire upper portion of the deposited ESD poly, and the ESD poly film of the first region is etched.

Next, a source is formed by implanting N + dopants in the remaining regions except for the region in which the trench of the first region and the P + dopant of the second region are implanted.

Finally, a Zener diode is formed in a region in which the trench of the first region and the N + dopant of the second region are implanted to complete a semiconductor device including an ESD protection device.

However, there is a problem in that P + dopants are unnecessarily injected to the first region to make the ESD protection element in the second region during the manufacturing process of the semiconductor device including the conventional ESD protection element.

In addition, in order to form the N + region in the second region where the ESD protection device is formed, an amount of N + dopant must be implanted more than the amount of N + dopant required to form a general semiconductor device source during the source implant process.

Thus, although an ESD protection element for protecting the gate region is formed, since the N + dopant is injected into the semiconductor element more than necessary, there is a problem that the RDSON characteristics of the semiconductor element are inferior.

The present invention provides a method of manufacturing a semiconductor device capable of optimizing both the characteristics of the ESD protection device and the RDSON properties of the semiconductor device by minimizing the deterioration of the RDSON properties of the semiconductor device in order to solve the above problems. There is this.

According to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: dividing a substrate into a first region for forming a semiconductor element and a second region for forming an electrostatic discharge (hereinafter, referred to as "ESD") protection element; ; Completing a trench in the first region; Forming an ESD poly film on the first region and the second region of which the trench is completed; Implanting a P + dopant for forming a P + region only in an upper portion of the second region; Implanting an N + dopant for forming a source region in the first region and the second region; And forming a zener diode on the region implanted with N + dopants in the first region and the second region.

In this case, the P + dopant implantation step may be implanted using an ESD implantation mask for exposing only the second region on the substrate.

The trench completion may include forming a trench on the first region using a hard mask; Forming a gate oxide film on the formed trench; And filling the polysilicon into the trench in which the gate oxide layer is formed to complete the trench.

In addition, the method of manufacturing a semiconductor device according to the present invention may further include forming a polyoxide film between the ESD poly film and the entire surface of the substrate except the trench.

The N + dopant implantation may further include etching the ESD poly film in the first region; Exposing a trench in the first region using a photoresist mask and exposing a region other than the region implanted with the P + dopant in the second region; And implanting N + dopant in the exposed regions.

In the method of manufacturing a semiconductor device according to the present invention, by injecting a P + dopant only into a region where an ESD protection element is formed on a substrate, unnecessary dopant injection is not necessary, thereby maximizing RDSON characteristics of the semiconductor device.

The manufacturing method of the semiconductor device according to the present invention may be configured to include a process other than the process to be described later, if necessary, but other than the above-described components are not directly related to the present invention for simplicity of explanation. Detailed description thereof is omitted below.

On the other hand, when the process is implemented in the actual application, it should be noted that two or more processes may be combined into one process as necessary, or one process may be divided into two or more processes.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of the embodiments.

A preferred embodiment of the method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

1A to 1G are flowcharts illustrating a process of manufacturing a semiconductor device including an ESD protection device according to the present invention.

First, as shown in FIG. 1A, the semiconductor substrate 100 is defined as a first region 110 for forming a semiconductor element and a second region 120 for forming an ESD protection element, and a hard mask 111 is defined. Trenches 112a are formed.

Next, as shown in FIG. 1B, the hard mask 111 is removed, the gate oxide film 113 is formed in the trench 112a, and the trench 112a in which the gate oxide film is formed is formed. The polysilicon 112b is filled, and a polyoxide film 114 is formed on the substrate 100 in the remaining region except for the trench 112a.

Next, as shown in FIG. 1C, an ESD poly film 151 is formed on the poly oxide film 114.

Next, as shown in FIG. 1D, a P + dopant implantation process for forming a P + region on the ESD poly film 151 is performed. In the present invention, an ESD protection device is formed in the second region 150. P + dopants are not unnecessarily implanted into the first region 110.

That is, in the present invention, the P + dopant is implanted into the second region 150 only by using the ESD injection mask 152 exposing only the second region 150 on the substrate 100 to form the ESD poly film 151. The P + region 153a is formed.

Next, as shown in FIG. 1E, the ESD injection mask 152 is removed, and the polyoxide 114 and the ESD poly film 151 of the first region 110 are etched.

Next, as shown in FIG. 1F, the trench 112a of the first region 110 is exposed using the photoresist mask 152, and the P + dopant of the second region 150 is implanted. Except the region 153a, the remaining region is exposed.

Subsequently, an N + dopant is implanted into the exposed region to form a source region 115 and a body region 116 on the left and right sides of the trench 112a of the first region 110, and the second region ( N + regions 153b are formed on the left and right sides of the P + region 153a of 150.

Lastly, as shown in FIG. 1G, a Zener diode 117 is formed on the trench 112a of the first region 110, except for the P + region 153a of the second region 150. The zener diode 117 is formed on the region to complete the semiconductor device including the ESD protection device.

It will be apparent to those skilled in the art that the present invention can be embodied in other specific forms without departing from the spirit and essential features of the present invention.

For example, it will be very easy for those skilled in the art to use the above-described embodiments in combination with each other.

Accordingly, the above detailed description should not be construed as limiting in all respects but should be considered as illustrative.

The scope of the invention should be determined by reasonable interpretation of the appended claims, and all changes within the equivalent scope of the invention are included in the scope of the invention.

Claims

Dividing the substrate into a first region for forming a semiconductor element and a second region for forming an electrostatic discharge (hereinafter, "ESD") protection circuit;

Completing a trench in the first region;

Forming an ESD poly film on the first region and the second region of which the trench is completed;

Implanting a P + dopant for forming a P + region only in an upper portion of the second region;

Implanting N + dopants for forming source regions in the first and second regions; And

And forming a Zener diode on the regions implanted with N + dopants in the first region and the second region.

According to claim 1,

The P + dopant implantation method is a semiconductor device manufacturing method, characterized in that for implanting using an ESD injection mask for exposing only the second region on the substrate.

The method of claim 1, wherein the trench completion step,

Forming a trench on the first region using a hard mask;

Forming a gate oxide film on the formed trench; And

And filling the polysilicon in the trench in which the gate oxide film is formed to complete the trench.

The method of claim 3,

And forming a poly oxide film between the ESD poly film and the entire surface of the substrate except the trench.

The method of claim 1, wherein the N + dopant implantation step,

Etching the ESD poly film in the first region;

Exposing a trench in the first region using a photoresist mask and exposing a region other than the region implanted with the P + dopant in the second region; And

Implanting N + dopant in the exposed regions.